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31#include "qemu/osdep.h"
32#include "hw/hw.h"
33#include "hw/pci-host/gpex.h"
34
35
36
37
38
39static void gpex_set_irq(void *opaque, int irq_num, int level)
40{
41 GPEXHost *s = opaque;
42
43 qemu_set_irq(s->irq[irq_num], level);
44}
45
46static void gpex_host_realize(DeviceState *dev, Error **errp)
47{
48 PCIHostState *pci = PCI_HOST_BRIDGE(dev);
49 GPEXHost *s = GPEX_HOST(dev);
50 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
51 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev);
52 int i;
53
54 pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX);
55 memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX);
56 memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024);
57
58 sysbus_init_mmio(sbd, &pex->mmio);
59 sysbus_init_mmio(sbd, &s->io_mmio);
60 sysbus_init_mmio(sbd, &s->io_ioport);
61 for (i = 0; i < GPEX_NUM_IRQS; i++) {
62 sysbus_init_irq(sbd, &s->irq[i]);
63 }
64
65 pci->bus = pci_register_bus(dev, "pcie.0", gpex_set_irq,
66 pci_swizzle_map_irq_fn, s, &s->io_mmio,
67 &s->io_ioport, 0, 4, TYPE_PCIE_BUS);
68
69 qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus));
70 qdev_init_nofail(DEVICE(&s->gpex_root));
71}
72
73static const char *gpex_host_root_bus_path(PCIHostState *host_bridge,
74 PCIBus *rootbus)
75{
76 return "0000:00";
77}
78
79static void gpex_host_class_init(ObjectClass *klass, void *data)
80{
81 DeviceClass *dc = DEVICE_CLASS(klass);
82 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
83
84 hc->root_bus_path = gpex_host_root_bus_path;
85 dc->realize = gpex_host_realize;
86 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
87 dc->fw_name = "pci";
88}
89
90static void gpex_host_initfn(Object *obj)
91{
92 GPEXHost *s = GPEX_HOST(obj);
93 GPEXRootState *root = &s->gpex_root;
94
95 object_initialize(root, sizeof(*root), TYPE_GPEX_ROOT_DEVICE);
96 object_property_add_child(obj, "gpex_root", OBJECT(root), NULL);
97 qdev_prop_set_uint32(DEVICE(root), "addr", PCI_DEVFN(0, 0));
98 qdev_prop_set_bit(DEVICE(root), "multifunction", false);
99}
100
101static const TypeInfo gpex_host_info = {
102 .name = TYPE_GPEX_HOST,
103 .parent = TYPE_PCIE_HOST_BRIDGE,
104 .instance_size = sizeof(GPEXHost),
105 .instance_init = gpex_host_initfn,
106 .class_init = gpex_host_class_init,
107};
108
109
110
111
112
113static const VMStateDescription vmstate_gpex_root = {
114 .name = "gpex_root",
115 .version_id = 1,
116 .minimum_version_id = 1,
117 .fields = (VMStateField[]) {
118 VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState),
119 VMSTATE_END_OF_LIST()
120 }
121};
122
123static void gpex_root_class_init(ObjectClass *klass, void *data)
124{
125 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
126 DeviceClass *dc = DEVICE_CLASS(klass);
127
128 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
129 dc->desc = "QEMU generic PCIe host bridge";
130 dc->vmsd = &vmstate_gpex_root;
131 k->vendor_id = PCI_VENDOR_ID_REDHAT;
132 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST;
133 k->revision = 0;
134 k->class_id = PCI_CLASS_BRIDGE_HOST;
135
136
137
138
139 dc->cannot_instantiate_with_device_add_yet = true;
140}
141
142static const TypeInfo gpex_root_info = {
143 .name = TYPE_GPEX_ROOT_DEVICE,
144 .parent = TYPE_PCI_DEVICE,
145 .instance_size = sizeof(GPEXRootState),
146 .class_init = gpex_root_class_init,
147};
148
149static void gpex_register(void)
150{
151 type_register_static(&gpex_root_info);
152 type_register_static(&gpex_host_info);
153}
154
155type_init(gpex_register)
156