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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/i386/pc.h"
28#include "hw/pci/pci.h"
29#include "hw/pci/pci_host.h"
30#include "hw/isa/isa.h"
31#include "hw/sysbus.h"
32#include "qapi/error.h"
33#include "qemu/range.h"
34#include "hw/xen/xen.h"
35#include "hw/pci-host/pam.h"
36#include "sysemu/sysemu.h"
37#include "hw/i386/ioapic.h"
38#include "qapi/visitor.h"
39#include "qemu/error-report.h"
40
41
42
43
44
45
46#define I440FX_PCI_HOST_BRIDGE(obj) \
47 OBJECT_CHECK(I440FXState, (obj), TYPE_I440FX_PCI_HOST_BRIDGE)
48
49typedef struct I440FXState {
50 PCIHostState parent_obj;
51 PcPciInfo pci_info;
52 uint64_t pci_hole64_size;
53 uint32_t short_root_bus;
54} I440FXState;
55
56#define PIIX_NUM_PIC_IRQS 16
57#define PIIX_NUM_PIRQS 4ULL
58#define XEN_PIIX_NUM_PIRQS 128ULL
59#define PIIX_PIRQC 0x60
60
61
62
63
64
65#define RCR_IOPORT 0xcf9
66
67typedef struct PIIX3State {
68 PCIDevice dev;
69
70
71
72
73
74
75
76
77
78
79#if PIIX_NUM_PIC_IRQS * PIIX_NUM_PIRQS > 64
80#error "unable to encode pic state in 64bit in pic_levels."
81#endif
82 uint64_t pic_levels;
83
84 qemu_irq *pic;
85
86
87 int32_t pci_irq_levels_vmstate[PIIX_NUM_PIRQS];
88
89
90 uint8_t rcr;
91
92
93 MemoryRegion rcr_mem;
94} PIIX3State;
95
96#define TYPE_PIIX3_PCI_DEVICE "pci-piix3"
97#define PIIX3_PCI_DEVICE(obj) \
98 OBJECT_CHECK(PIIX3State, (obj), TYPE_PIIX3_PCI_DEVICE)
99
100#define I440FX_PCI_DEVICE(obj) \
101 OBJECT_CHECK(PCII440FXState, (obj), TYPE_I440FX_PCI_DEVICE)
102
103struct PCII440FXState {
104
105 PCIDevice parent_obj;
106
107
108 MemoryRegion *system_memory;
109 MemoryRegion *pci_address_space;
110 MemoryRegion *ram_memory;
111 PAMMemoryRegion pam_regions[13];
112 MemoryRegion smram_region;
113 MemoryRegion smram, low_smram;
114};
115
116
117#define I440FX_PAM 0x59
118#define I440FX_PAM_SIZE 7
119#define I440FX_SMRAM 0x72
120
121
122
123
124#define I440FX_COREBOOT_RAM_SIZE 0x57
125
126static void piix3_set_irq(void *opaque, int pirq, int level);
127static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pci_intx);
128static void piix3_write_config_xen(PCIDevice *dev,
129 uint32_t address, uint32_t val, int len);
130
131
132
133
134static int pci_slot_get_pirq(PCIDevice *pci_dev, int pci_intx)
135{
136 int slot_addend;
137 slot_addend = (pci_dev->devfn >> 3) - 1;
138 return (pci_intx + slot_addend) & 3;
139}
140
141static void i440fx_update_memory_mappings(PCII440FXState *d)
142{
143 int i;
144 PCIDevice *pd = PCI_DEVICE(d);
145
146 memory_region_transaction_begin();
147 for (i = 0; i < 13; i++) {
148 pam_update(&d->pam_regions[i], i,
149 pd->config[I440FX_PAM + ((i + 1) / 2)]);
150 }
151 memory_region_set_enabled(&d->smram_region,
152 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN));
153 memory_region_set_enabled(&d->smram,
154 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME);
155 memory_region_transaction_commit();
156}
157
158
159static void i440fx_write_config(PCIDevice *dev,
160 uint32_t address, uint32_t val, int len)
161{
162 PCII440FXState *d = I440FX_PCI_DEVICE(dev);
163
164
165 pci_default_write_config(dev, address, val, len);
166 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) ||
167 range_covers_byte(address, len, I440FX_SMRAM)) {
168 i440fx_update_memory_mappings(d);
169 }
170}
171
172static int i440fx_load_old(QEMUFile* f, void *opaque, int version_id)
173{
174 PCII440FXState *d = opaque;
175 PCIDevice *pd = PCI_DEVICE(d);
176 int ret, i;
177 uint8_t smm_enabled;
178
179 ret = pci_device_load(pd, f);
180 if (ret < 0)
181 return ret;
182 i440fx_update_memory_mappings(d);
183 qemu_get_8s(f, &smm_enabled);
184
185 if (version_id == 2) {
186 for (i = 0; i < PIIX_NUM_PIRQS; i++) {
187 qemu_get_be32(f);
188 }
189 }
190
191 return 0;
192}
193
194static int i440fx_post_load(void *opaque, int version_id)
195{
196 PCII440FXState *d = opaque;
197
198 i440fx_update_memory_mappings(d);
199 return 0;
200}
201
202static const VMStateDescription vmstate_i440fx = {
203 .name = "I440FX",
204 .version_id = 3,
205 .minimum_version_id = 3,
206 .minimum_version_id_old = 1,
207 .load_state_old = i440fx_load_old,
208 .post_load = i440fx_post_load,
209 .fields = (VMStateField[]) {
210 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState),
211
212
213
214 VMSTATE_UNUSED(1),
215 VMSTATE_END_OF_LIST()
216 }
217};
218
219static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v,
220 const char *name, void *opaque,
221 Error **errp)
222{
223 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
224 uint32_t value = s->pci_info.w32.begin;
225
226 visit_type_uint32(v, name, &value, errp);
227}
228
229static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v,
230 const char *name, void *opaque,
231 Error **errp)
232{
233 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj);
234 uint32_t value = s->pci_info.w32.end;
235
236 visit_type_uint32(v, name, &value, errp);
237}
238
239static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v,
240 const char *name,
241 void *opaque, Error **errp)
242{
243 PCIHostState *h = PCI_HOST_BRIDGE(obj);
244 Range w64;
245
246 pci_bus_get_w64_range(h->bus, &w64);
247
248 visit_type_uint64(v, name, &w64.begin, errp);
249}
250
251static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v,
252 const char *name, void *opaque,
253 Error **errp)
254{
255 PCIHostState *h = PCI_HOST_BRIDGE(obj);
256 Range w64;
257
258 pci_bus_get_w64_range(h->bus, &w64);
259
260 visit_type_uint64(v, name, &w64.end, errp);
261}
262
263static void i440fx_pcihost_initfn(Object *obj)
264{
265 PCIHostState *s = PCI_HOST_BRIDGE(obj);
266 I440FXState *d = I440FX_PCI_HOST_BRIDGE(obj);
267
268 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s,
269 "pci-conf-idx", 4);
270 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s,
271 "pci-conf-data", 4);
272
273 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int",
274 i440fx_pcihost_get_pci_hole_start,
275 NULL, NULL, NULL, NULL);
276
277 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int",
278 i440fx_pcihost_get_pci_hole_end,
279 NULL, NULL, NULL, NULL);
280
281 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int",
282 i440fx_pcihost_get_pci_hole64_start,
283 NULL, NULL, NULL, NULL);
284
285 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int",
286 i440fx_pcihost_get_pci_hole64_end,
287 NULL, NULL, NULL, NULL);
288
289 d->pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS;
290}
291
292static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
293{
294 PCIHostState *s = PCI_HOST_BRIDGE(dev);
295 SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
296
297 sysbus_add_io(sbd, 0xcf8, &s->conf_mem);
298 sysbus_init_ioports(sbd, 0xcf8, 4);
299
300 sysbus_add_io(sbd, 0xcfc, &s->data_mem);
301 sysbus_init_ioports(sbd, 0xcfc, 4);
302}
303
304static void i440fx_realize(PCIDevice *dev, Error **errp)
305{
306 dev->config[I440FX_SMRAM] = 0x02;
307
308 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) {
309 error_report("warning: i440fx doesn't support emulated iommu");
310 }
311}
312
313PCIBus *i440fx_init(const char *host_type, const char *pci_type,
314 PCII440FXState **pi440fx_state,
315 int *piix3_devfn,
316 ISABus **isa_bus, qemu_irq *pic,
317 MemoryRegion *address_space_mem,
318 MemoryRegion *address_space_io,
319 ram_addr_t ram_size,
320 ram_addr_t below_4g_mem_size,
321 ram_addr_t above_4g_mem_size,
322 MemoryRegion *pci_address_space,
323 MemoryRegion *ram_memory)
324{
325 DeviceState *dev;
326 PCIBus *b;
327 PCIDevice *d;
328 PCIHostState *s;
329 PIIX3State *piix3;
330 PCII440FXState *f;
331 unsigned i;
332 I440FXState *i440fx;
333
334 dev = qdev_create(NULL, host_type);
335 s = PCI_HOST_BRIDGE(dev);
336 b = pci_bus_new(dev, NULL, pci_address_space,
337 address_space_io, 0, TYPE_PCI_BUS);
338 s->bus = b;
339 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev), NULL);
340 qdev_init_nofail(dev);
341
342 d = pci_create_simple(b, 0, pci_type);
343 *pi440fx_state = I440FX_PCI_DEVICE(d);
344 f = *pi440fx_state;
345 f->system_memory = address_space_mem;
346 f->pci_address_space = pci_address_space;
347 f->ram_memory = ram_memory;
348
349 i440fx = I440FX_PCI_HOST_BRIDGE(dev);
350 i440fx->pci_info.w32.begin = below_4g_mem_size;
351
352
353 pc_pci_as_mapping_init(OBJECT(f), f->system_memory,
354 f->pci_address_space);
355
356
357 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region",
358 f->pci_address_space, 0xa0000, 0x20000);
359 memory_region_add_subregion_overlap(f->system_memory, 0xa0000,
360 &f->smram_region, 1);
361 memory_region_set_enabled(&f->smram_region, true);
362
363
364 memory_region_init(&f->smram, OBJECT(d), "smram", 1ull << 32);
365 memory_region_set_enabled(&f->smram, true);
366 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low",
367 f->ram_memory, 0xa0000, 0x20000);
368 memory_region_set_enabled(&f->low_smram, true);
369 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram);
370 object_property_add_const_link(qdev_get_machine(), "smram",
371 OBJECT(&f->smram), &error_abort);
372
373 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
374 &f->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE);
375 for (i = 0; i < 12; ++i) {
376 init_pam(dev, f->ram_memory, f->system_memory, f->pci_address_space,
377 &f->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE,
378 PAM_EXPAN_SIZE);
379 }
380
381
382
383
384
385 if (xen_enabled()) {
386 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
387 -1, true, "PIIX3-xen");
388 piix3 = PIIX3_PCI_DEVICE(pci_dev);
389 pci_bus_irqs(b, xen_piix3_set_irq, xen_pci_slot_get_pirq,
390 piix3, XEN_PIIX_NUM_PIRQS);
391 } else {
392 PCIDevice *pci_dev = pci_create_simple_multifunction(b,
393 -1, true, "PIIX3");
394 piix3 = PIIX3_PCI_DEVICE(pci_dev);
395 pci_bus_irqs(b, piix3_set_irq, pci_slot_get_pirq, piix3,
396 PIIX_NUM_PIRQS);
397 pci_bus_set_route_irq_fn(b, piix3_route_intx_pin_to_irq);
398 }
399 piix3->pic = pic;
400 *isa_bus = ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0"));
401
402 *piix3_devfn = piix3->dev.devfn;
403
404 ram_size = ram_size / 8 / 1024 / 1024;
405 if (ram_size > 255) {
406 ram_size = 255;
407 }
408 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size;
409
410 i440fx_update_memory_mappings(f);
411
412 return b;
413}
414
415PCIBus *find_i440fx(void)
416{
417 PCIHostState *s = OBJECT_CHECK(PCIHostState,
418 object_resolve_path("/machine/i440fx", NULL),
419 TYPE_PCI_HOST_BRIDGE);
420 return s ? s->bus : NULL;
421}
422
423
424static void piix3_set_irq_pic(PIIX3State *piix3, int pic_irq)
425{
426 qemu_set_irq(piix3->pic[pic_irq],
427 !!(piix3->pic_levels &
428 (((1ULL << PIIX_NUM_PIRQS) - 1) <<
429 (pic_irq * PIIX_NUM_PIRQS))));
430}
431
432static void piix3_set_irq_level_internal(PIIX3State *piix3, int pirq, int level)
433{
434 int pic_irq;
435 uint64_t mask;
436
437 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
438 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
439 return;
440 }
441
442 mask = 1ULL << ((pic_irq * PIIX_NUM_PIRQS) + pirq);
443 piix3->pic_levels &= ~mask;
444 piix3->pic_levels |= mask * !!level;
445}
446
447static void piix3_set_irq_level(PIIX3State *piix3, int pirq, int level)
448{
449 int pic_irq;
450
451 pic_irq = piix3->dev.config[PIIX_PIRQC + pirq];
452 if (pic_irq >= PIIX_NUM_PIC_IRQS) {
453 return;
454 }
455
456 piix3_set_irq_level_internal(piix3, pirq, level);
457
458 piix3_set_irq_pic(piix3, pic_irq);
459}
460
461static void piix3_set_irq(void *opaque, int pirq, int level)
462{
463 PIIX3State *piix3 = opaque;
464 piix3_set_irq_level(piix3, pirq, level);
465}
466
467static PCIINTxRoute piix3_route_intx_pin_to_irq(void *opaque, int pin)
468{
469 PIIX3State *piix3 = opaque;
470 int irq = piix3->dev.config[PIIX_PIRQC + pin];
471 PCIINTxRoute route;
472
473 if (irq < PIIX_NUM_PIC_IRQS) {
474 route.mode = PCI_INTX_ENABLED;
475 route.irq = irq;
476 } else {
477 route.mode = PCI_INTX_DISABLED;
478 route.irq = -1;
479 }
480 return route;
481}
482
483
484static void piix3_update_irq_levels(PIIX3State *piix3)
485{
486 int pirq;
487
488 piix3->pic_levels = 0;
489 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
490 piix3_set_irq_level(piix3, pirq,
491 pci_bus_get_irq_level(piix3->dev.bus, pirq));
492 }
493}
494
495static void piix3_write_config(PCIDevice *dev,
496 uint32_t address, uint32_t val, int len)
497{
498 pci_default_write_config(dev, address, val, len);
499 if (ranges_overlap(address, len, PIIX_PIRQC, 4)) {
500 PIIX3State *piix3 = PIIX3_PCI_DEVICE(dev);
501 int pic_irq;
502
503 pci_bus_fire_intx_routing_notifier(piix3->dev.bus);
504 piix3_update_irq_levels(piix3);
505 for (pic_irq = 0; pic_irq < PIIX_NUM_PIC_IRQS; pic_irq++) {
506 piix3_set_irq_pic(piix3, pic_irq);
507 }
508 }
509}
510
511static void piix3_write_config_xen(PCIDevice *dev,
512 uint32_t address, uint32_t val, int len)
513{
514 xen_piix_pci_write_config_client(address, val, len);
515 piix3_write_config(dev, address, val, len);
516}
517
518static void piix3_reset(void *opaque)
519{
520 PIIX3State *d = opaque;
521 uint8_t *pci_conf = d->dev.config;
522
523 pci_conf[0x04] = 0x07;
524 pci_conf[0x05] = 0x00;
525 pci_conf[0x06] = 0x00;
526 pci_conf[0x07] = 0x02;
527 pci_conf[0x4c] = 0x4d;
528 pci_conf[0x4e] = 0x03;
529 pci_conf[0x4f] = 0x00;
530 pci_conf[0x60] = 0x80;
531 pci_conf[0x61] = 0x80;
532 pci_conf[0x62] = 0x80;
533 pci_conf[0x63] = 0x80;
534 pci_conf[0x69] = 0x02;
535 pci_conf[0x70] = 0x80;
536 pci_conf[0x76] = 0x0c;
537 pci_conf[0x77] = 0x0c;
538 pci_conf[0x78] = 0x02;
539 pci_conf[0x79] = 0x00;
540 pci_conf[0x80] = 0x00;
541 pci_conf[0x82] = 0x00;
542 pci_conf[0xa0] = 0x08;
543 pci_conf[0xa2] = 0x00;
544 pci_conf[0xa3] = 0x00;
545 pci_conf[0xa4] = 0x00;
546 pci_conf[0xa5] = 0x00;
547 pci_conf[0xa6] = 0x00;
548 pci_conf[0xa7] = 0x00;
549 pci_conf[0xa8] = 0x0f;
550 pci_conf[0xaa] = 0x00;
551 pci_conf[0xab] = 0x00;
552 pci_conf[0xac] = 0x00;
553 pci_conf[0xae] = 0x00;
554
555 d->pic_levels = 0;
556 d->rcr = 0;
557}
558
559static int piix3_post_load(void *opaque, int version_id)
560{
561 PIIX3State *piix3 = opaque;
562 int pirq;
563
564
565
566
567
568
569
570
571
572 piix3->pic_levels = 0;
573 for (pirq = 0; pirq < PIIX_NUM_PIRQS; pirq++) {
574 piix3_set_irq_level_internal(piix3, pirq,
575 pci_bus_get_irq_level(piix3->dev.bus, pirq));
576 }
577 return 0;
578}
579
580static void piix3_pre_save(void *opaque)
581{
582 int i;
583 PIIX3State *piix3 = opaque;
584
585 for (i = 0; i < ARRAY_SIZE(piix3->pci_irq_levels_vmstate); i++) {
586 piix3->pci_irq_levels_vmstate[i] =
587 pci_bus_get_irq_level(piix3->dev.bus, i);
588 }
589}
590
591static bool piix3_rcr_needed(void *opaque)
592{
593 PIIX3State *piix3 = opaque;
594
595 return (piix3->rcr != 0);
596}
597
598static const VMStateDescription vmstate_piix3_rcr = {
599 .name = "PIIX3/rcr",
600 .version_id = 1,
601 .minimum_version_id = 1,
602 .needed = piix3_rcr_needed,
603 .fields = (VMStateField[]) {
604 VMSTATE_UINT8(rcr, PIIX3State),
605 VMSTATE_END_OF_LIST()
606 }
607};
608
609static const VMStateDescription vmstate_piix3 = {
610 .name = "PIIX3",
611 .version_id = 3,
612 .minimum_version_id = 2,
613 .post_load = piix3_post_load,
614 .pre_save = piix3_pre_save,
615 .fields = (VMStateField[]) {
616 VMSTATE_PCI_DEVICE(dev, PIIX3State),
617 VMSTATE_INT32_ARRAY_V(pci_irq_levels_vmstate, PIIX3State,
618 PIIX_NUM_PIRQS, 3),
619 VMSTATE_END_OF_LIST()
620 },
621 .subsections = (const VMStateDescription*[]) {
622 &vmstate_piix3_rcr,
623 NULL
624 }
625};
626
627
628static void rcr_write(void *opaque, hwaddr addr, uint64_t val, unsigned len)
629{
630 PIIX3State *d = opaque;
631
632 if (val & 4) {
633 qemu_system_reset_request();
634 return;
635 }
636 d->rcr = val & 2;
637}
638
639static uint64_t rcr_read(void *opaque, hwaddr addr, unsigned len)
640{
641 PIIX3State *d = opaque;
642
643 return d->rcr;
644}
645
646static const MemoryRegionOps rcr_ops = {
647 .read = rcr_read,
648 .write = rcr_write,
649 .endianness = DEVICE_LITTLE_ENDIAN
650};
651
652static void piix3_realize(PCIDevice *dev, Error **errp)
653{
654 PIIX3State *d = PIIX3_PCI_DEVICE(dev);
655
656 if (!isa_bus_new(DEVICE(d), get_system_memory(),
657 pci_address_space_io(dev), errp)) {
658 return;
659 }
660
661 memory_region_init_io(&d->rcr_mem, OBJECT(dev), &rcr_ops, d,
662 "piix3-reset-control", 1);
663 memory_region_add_subregion_overlap(pci_address_space_io(dev), RCR_IOPORT,
664 &d->rcr_mem, 1);
665
666 qemu_register_reset(piix3_reset, d);
667}
668
669static void pci_piix3_class_init(ObjectClass *klass, void *data)
670{
671 DeviceClass *dc = DEVICE_CLASS(klass);
672 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
673
674 dc->desc = "ISA bridge";
675 dc->vmsd = &vmstate_piix3;
676 dc->hotpluggable = false;
677 k->realize = piix3_realize;
678 k->vendor_id = PCI_VENDOR_ID_INTEL;
679
680 k->device_id = PCI_DEVICE_ID_INTEL_82371SB_0;
681 k->class_id = PCI_CLASS_BRIDGE_ISA;
682
683
684
685
686 dc->cannot_instantiate_with_device_add_yet = true;
687}
688
689static const TypeInfo piix3_pci_type_info = {
690 .name = TYPE_PIIX3_PCI_DEVICE,
691 .parent = TYPE_PCI_DEVICE,
692 .instance_size = sizeof(PIIX3State),
693 .abstract = true,
694 .class_init = pci_piix3_class_init,
695};
696
697static void piix3_class_init(ObjectClass *klass, void *data)
698{
699 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
700
701 k->config_write = piix3_write_config;
702}
703
704static const TypeInfo piix3_info = {
705 .name = "PIIX3",
706 .parent = TYPE_PIIX3_PCI_DEVICE,
707 .class_init = piix3_class_init,
708};
709
710static void piix3_xen_class_init(ObjectClass *klass, void *data)
711{
712 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
713
714 k->config_write = piix3_write_config_xen;
715};
716
717static const TypeInfo piix3_xen_info = {
718 .name = "PIIX3-xen",
719 .parent = TYPE_PIIX3_PCI_DEVICE,
720 .class_init = piix3_xen_class_init,
721};
722
723static void i440fx_class_init(ObjectClass *klass, void *data)
724{
725 DeviceClass *dc = DEVICE_CLASS(klass);
726 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
727
728 k->realize = i440fx_realize;
729 k->config_write = i440fx_write_config;
730 k->vendor_id = PCI_VENDOR_ID_INTEL;
731 k->device_id = PCI_DEVICE_ID_INTEL_82441;
732 k->revision = 0x02;
733 k->class_id = PCI_CLASS_BRIDGE_HOST;
734 dc->desc = "Host bridge";
735 dc->vmsd = &vmstate_i440fx;
736
737
738
739
740 dc->cannot_instantiate_with_device_add_yet = true;
741 dc->hotpluggable = false;
742}
743
744static const TypeInfo i440fx_info = {
745 .name = TYPE_I440FX_PCI_DEVICE,
746 .parent = TYPE_PCI_DEVICE,
747 .instance_size = sizeof(PCII440FXState),
748 .class_init = i440fx_class_init,
749};
750
751
752typedef struct {
753 uint8_t offset;
754 uint8_t len;
755} IGDHostInfo;
756
757
758static const IGDHostInfo igd_host_bridge_infos[] = {
759 {0x08, 2},
760 {0x2c, 2},
761 {0x2e, 2},
762 {0x50, 2},
763 {0x52, 2},
764 {0xa4, 4},
765 {0xa8, 4},
766};
767
768static int host_pci_config_read(int pos, int len, uint32_t *val)
769{
770 char path[PATH_MAX];
771 int config_fd;
772 ssize_t size = sizeof(path);
773
774 int rc = snprintf(path, size, "/sys/bus/pci/devices/%04x:%02x:%02x.%d/%s",
775 0, 0, 0, 0, "config");
776 int ret = 0;
777
778 if (rc >= size || rc < 0) {
779 return -ENODEV;
780 }
781
782 config_fd = open(path, O_RDWR);
783 if (config_fd < 0) {
784 return -ENODEV;
785 }
786
787 if (lseek(config_fd, pos, SEEK_SET) != pos) {
788 ret = -errno;
789 goto out;
790 }
791
792 do {
793 rc = read(config_fd, (uint8_t *)val, len);
794 } while (rc < 0 && (errno == EINTR || errno == EAGAIN));
795 if (rc != len) {
796 ret = -errno;
797 }
798
799out:
800 close(config_fd);
801 return ret;
802}
803
804static int igd_pt_i440fx_initfn(struct PCIDevice *pci_dev)
805{
806 uint32_t val = 0;
807 int rc, i, num;
808 int pos, len;
809
810 num = ARRAY_SIZE(igd_host_bridge_infos);
811 for (i = 0; i < num; i++) {
812 pos = igd_host_bridge_infos[i].offset;
813 len = igd_host_bridge_infos[i].len;
814 rc = host_pci_config_read(pos, len, &val);
815 if (rc) {
816 return -ENODEV;
817 }
818 pci_default_write_config(pci_dev, pos, val, len);
819 }
820
821 return 0;
822}
823
824static void igd_passthrough_i440fx_class_init(ObjectClass *klass, void *data)
825{
826 DeviceClass *dc = DEVICE_CLASS(klass);
827 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
828
829 k->init = igd_pt_i440fx_initfn;
830 dc->desc = "IGD Passthrough Host bridge";
831}
832
833static const TypeInfo igd_passthrough_i440fx_info = {
834 .name = TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE,
835 .parent = TYPE_I440FX_PCI_DEVICE,
836 .instance_size = sizeof(PCII440FXState),
837 .class_init = igd_passthrough_i440fx_class_init,
838};
839
840static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge,
841 PCIBus *rootbus)
842{
843 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge);
844
845
846 if (s->short_root_bus) {
847 return "0000";
848 }
849 return "0000:00";
850}
851
852static Property i440fx_props[] = {
853 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState,
854 pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE),
855 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0),
856 DEFINE_PROP_END_OF_LIST(),
857};
858
859static void i440fx_pcihost_class_init(ObjectClass *klass, void *data)
860{
861 DeviceClass *dc = DEVICE_CLASS(klass);
862 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass);
863
864 hc->root_bus_path = i440fx_pcihost_root_bus_path;
865 dc->realize = i440fx_pcihost_realize;
866 dc->fw_name = "pci";
867 dc->props = i440fx_props;
868}
869
870static const TypeInfo i440fx_pcihost_info = {
871 .name = TYPE_I440FX_PCI_HOST_BRIDGE,
872 .parent = TYPE_PCI_HOST_BRIDGE,
873 .instance_size = sizeof(I440FXState),
874 .instance_init = i440fx_pcihost_initfn,
875 .class_init = i440fx_pcihost_class_init,
876};
877
878static void i440fx_register_types(void)
879{
880 type_register_static(&i440fx_info);
881 type_register_static(&igd_passthrough_i440fx_info);
882 type_register_static(&piix3_pci_type_info);
883 type_register_static(&piix3_info);
884 type_register_static(&piix3_xen_info);
885 type_register_static(&i440fx_pcihost_info);
886}
887
888type_init(i440fx_register_types)
889