LXR qemu/hw/scsi/mptsas.h

   1#ifndef MPTSAS_H
   2#define MPTSAS_H
   3
   4#include "mpi.h"
   5
   6#define MPTSAS_NUM_PORTS 8
   7#define MPTSAS_MAX_FRAMES 2048     /* Firmware limit at 65535 */
   8
   9#define MPTSAS_REQUEST_QUEUE_DEPTH 128
  10#define MPTSAS_REPLY_QUEUE_DEPTH   128
  11
  12#define MPTSAS_MAXIMUM_CHAIN_DEPTH 0x22
  13
  14typedef struct MPTSASState MPTSASState;
  15typedef struct MPTSASRequest MPTSASRequest;
  16
  17enum {
  18    DOORBELL_NONE,
  19    DOORBELL_WRITE,
  20    DOORBELL_READ
  21};
  22
  23struct MPTSASState {
  24    PCIDevice dev;
  25    MemoryRegion mmio_io;
  26    MemoryRegion port_io;
  27    MemoryRegion diag_io;
  28    QEMUBH *request_bh;
  29
  30    uint32_t msi_available;
  31    uint64_t sas_addr;
  32
  33    bool msi_in_use;
  34
  35    /* Doorbell register */
  36    uint32_t state;
  37    uint8_t who_init;
  38    uint8_t doorbell_state;
  39
  40    /* Buffer for requests that are sent through the doorbell register.  */
  41    uint32_t doorbell_msg[256];
  42    int doorbell_idx;
  43    int doorbell_cnt;
  44
  45    uint16_t doorbell_reply[256];
  46    int doorbell_reply_idx;
  47    int doorbell_reply_size;
  48
  49    /* Other registers */
  50    uint8_t diagnostic_idx;
  51    uint32_t diagnostic;
  52    uint32_t intr_mask;
  53    uint32_t intr_status;
  54
  55    /* Request queues */
  56    uint32_t request_post[MPTSAS_REQUEST_QUEUE_DEPTH + 1];
  57    uint16_t request_post_head;
  58    uint16_t request_post_tail;
  59
  60    uint32_t reply_post[MPTSAS_REPLY_QUEUE_DEPTH + 1];
  61    uint16_t reply_post_head;
  62    uint16_t reply_post_tail;
  63
  64    uint32_t reply_free[MPTSAS_REPLY_QUEUE_DEPTH + 1];
  65    uint16_t reply_free_head;
  66    uint16_t reply_free_tail;
  67
  68    /* IOC Facts */
  69    hwaddr host_mfa_high_addr;
  70    hwaddr sense_buffer_high_addr;
  71    uint16_t max_devices;
  72    uint16_t max_buses;
  73    uint16_t reply_frame_size;
  74
  75    SCSIBus bus;
  76    QTAILQ_HEAD(, MPTSASRequest) pending;
  77};
  78
  79void mptsas_fix_scsi_io_endianness(MPIMsgSCSIIORequest *req);
  80void mptsas_fix_scsi_io_reply_endianness(MPIMsgSCSIIOReply *reply);
  81void mptsas_fix_scsi_task_mgmt_endianness(MPIMsgSCSITaskMgmt *req);
  82void mptsas_fix_scsi_task_mgmt_reply_endianness(MPIMsgSCSITaskMgmtReply *reply);
  83void mptsas_fix_ioc_init_endianness(MPIMsgIOCInit *req);
  84void mptsas_fix_ioc_init_reply_endianness(MPIMsgIOCInitReply *reply);
  85void mptsas_fix_ioc_facts_endianness(MPIMsgIOCFacts *req);
  86void mptsas_fix_ioc_facts_reply_endianness(MPIMsgIOCFactsReply *reply);
  87void mptsas_fix_config_endianness(MPIMsgConfig *req);
  88void mptsas_fix_config_reply_endianness(MPIMsgConfigReply *reply);
  89void mptsas_fix_port_facts_endianness(MPIMsgPortFacts *req);
  90void mptsas_fix_port_facts_reply_endianness(MPIMsgPortFactsReply *reply);
  91void mptsas_fix_port_enable_endianness(MPIMsgPortEnable *req);
  92void mptsas_fix_port_enable_reply_endianness(MPIMsgPortEnableReply *reply);
  93void mptsas_fix_event_notification_endianness(MPIMsgEventNotify *req);
  94void mptsas_fix_event_notification_reply_endianness(MPIMsgEventNotifyReply *reply);
  95
  96void mptsas_reply(MPTSASState *s, MPIDefaultReply *reply);
  97
  98void mptsas_process_config(MPTSASState *s, MPIMsgConfig *req);
  99
 100#endif /* MPTSAS_H */
 101