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27#include "qemu/osdep.h"
28#include "hw/sysbus.h"
29#include "sysemu/sysemu.h"
30#include "qemu/log.h"
31#include "qemu/fifo8.h"
32
33#include "hw/ssi/ssi.h"
34
35#ifdef XILINX_SPI_ERR_DEBUG
36#define DB_PRINT(...) do { \
37 fprintf(stderr, ": %s: ", __func__); \
38 fprintf(stderr, ## __VA_ARGS__); \
39 } while (0);
40#else
41 #define DB_PRINT(...)
42#endif
43
44#define R_DGIER (0x1c / 4)
45#define R_DGIER_IE (1 << 31)
46
47#define R_IPISR (0x20 / 4)
48#define IRQ_DRR_NOT_EMPTY (1 << (31 - 23))
49#define IRQ_DRR_OVERRUN (1 << (31 - 26))
50#define IRQ_DRR_FULL (1 << (31 - 27))
51#define IRQ_TX_FF_HALF_EMPTY (1 << 6)
52#define IRQ_DTR_UNDERRUN (1 << 3)
53#define IRQ_DTR_EMPTY (1 << (31 - 29))
54
55#define R_IPIER (0x28 / 4)
56#define R_SRR (0x40 / 4)
57#define R_SPICR (0x60 / 4)
58#define R_SPICR_TXFF_RST (1 << 5)
59#define R_SPICR_RXFF_RST (1 << 6)
60#define R_SPICR_MTI (1 << 8)
61#define R_SPICR_MANUAL_SS_EN (1 << 7)
62
63#define R_SPISR (0x64 / 4)
64#define SR_TX_FULL (1 << 3)
65#define SR_TX_EMPTY (1 << 2)
66#define SR_RX_FULL (1 << 1)
67#define SR_RX_EMPTY (1 << 0)
68
69#define R_SPIDTR (0x68 / 4)
70#define R_SPIDRR (0x6C / 4)
71#define R_SPISSR (0x70 / 4)
72#define R_TX_FF_OCY (0x74 / 4)
73#define R_RX_FF_OCY (0x78 / 4)
74#define R_MAX (0x7C / 4)
75
76#define FIFO_CAPACITY 256
77
78#define TYPE_XILINX_SPI "xlnx.xps-spi"
79#define XILINX_SPI(obj) OBJECT_CHECK(XilinxSPI, (obj), TYPE_XILINX_SPI)
80
81typedef struct XilinxSPI {
82 SysBusDevice parent_obj;
83
84 MemoryRegion mmio;
85
86 qemu_irq irq;
87 int irqline;
88
89 uint8_t num_cs;
90 qemu_irq *cs_lines;
91
92 SSIBus *spi;
93
94 Fifo8 rx_fifo;
95 Fifo8 tx_fifo;
96
97 uint32_t regs[R_MAX];
98} XilinxSPI;
99
100static void txfifo_reset(XilinxSPI *s)
101{
102 fifo8_reset(&s->tx_fifo);
103
104 s->regs[R_SPISR] &= ~SR_TX_FULL;
105 s->regs[R_SPISR] |= SR_TX_EMPTY;
106}
107
108static void rxfifo_reset(XilinxSPI *s)
109{
110 fifo8_reset(&s->rx_fifo);
111
112 s->regs[R_SPISR] |= SR_RX_EMPTY;
113 s->regs[R_SPISR] &= ~SR_RX_FULL;
114}
115
116static void xlx_spi_update_cs(XilinxSPI *s)
117{
118 int i;
119
120 for (i = 0; i < s->num_cs; ++i) {
121 qemu_set_irq(s->cs_lines[i], !(~s->regs[R_SPISSR] & 1 << i));
122 }
123}
124
125static void xlx_spi_update_irq(XilinxSPI *s)
126{
127 uint32_t pending;
128
129 s->regs[R_IPISR] |=
130 (!fifo8_is_empty(&s->rx_fifo) ? IRQ_DRR_NOT_EMPTY : 0) |
131 (fifo8_is_full(&s->rx_fifo) ? IRQ_DRR_FULL : 0);
132
133 pending = s->regs[R_IPISR] & s->regs[R_IPIER];
134
135 pending = pending && (s->regs[R_DGIER] & R_DGIER_IE);
136 pending = !!pending;
137
138
139
140 if (pending != s->irqline) {
141 s->irqline = pending;
142 DB_PRINT("irq_change of state %d ISR:%x IER:%X\n",
143 pending, s->regs[R_IPISR], s->regs[R_IPIER]);
144 qemu_set_irq(s->irq, pending);
145 }
146
147}
148
149static void xlx_spi_do_reset(XilinxSPI *s)
150{
151 memset(s->regs, 0, sizeof s->regs);
152
153 rxfifo_reset(s);
154 txfifo_reset(s);
155
156 s->regs[R_SPISSR] = ~0;
157 xlx_spi_update_irq(s);
158 xlx_spi_update_cs(s);
159 s->regs[R_SPICR] = R_SPICR_MTI | R_SPICR_MANUAL_SS_EN;
160}
161
162static void xlx_spi_reset(DeviceState *d)
163{
164 xlx_spi_do_reset(XILINX_SPI(d));
165}
166
167static inline int spi_master_enabled(XilinxSPI *s)
168{
169 return !(s->regs[R_SPICR] & R_SPICR_MTI);
170}
171
172static void spi_flush_txfifo(XilinxSPI *s)
173{
174 uint32_t tx;
175 uint32_t rx;
176
177 while (!fifo8_is_empty(&s->tx_fifo)) {
178 tx = (uint32_t)fifo8_pop(&s->tx_fifo);
179 DB_PRINT("data tx:%x\n", tx);
180 rx = ssi_transfer(s->spi, tx);
181 DB_PRINT("data rx:%x\n", rx);
182 if (fifo8_is_full(&s->rx_fifo)) {
183 s->regs[R_IPISR] |= IRQ_DRR_OVERRUN;
184 } else {
185 fifo8_push(&s->rx_fifo, (uint8_t)rx);
186 if (fifo8_is_full(&s->rx_fifo)) {
187 s->regs[R_SPISR] |= SR_RX_FULL;
188 s->regs[R_IPISR] |= IRQ_DRR_FULL;
189 }
190 }
191
192 s->regs[R_SPISR] &= ~SR_RX_EMPTY;
193 s->regs[R_SPISR] &= ~SR_TX_FULL;
194 s->regs[R_SPISR] |= SR_TX_EMPTY;
195
196 s->regs[R_IPISR] |= IRQ_DTR_EMPTY;
197 s->regs[R_IPISR] |= IRQ_DRR_NOT_EMPTY;
198 }
199
200}
201
202static uint64_t
203spi_read(void *opaque, hwaddr addr, unsigned int size)
204{
205 XilinxSPI *s = opaque;
206 uint32_t r = 0;
207
208 addr >>= 2;
209 switch (addr) {
210 case R_SPIDRR:
211 if (fifo8_is_empty(&s->rx_fifo)) {
212 DB_PRINT("Read from empty FIFO!\n");
213 return 0xdeadbeef;
214 }
215
216 s->regs[R_SPISR] &= ~SR_RX_FULL;
217 r = fifo8_pop(&s->rx_fifo);
218 if (fifo8_is_empty(&s->rx_fifo)) {
219 s->regs[R_SPISR] |= SR_RX_EMPTY;
220 }
221 break;
222
223 case R_SPISR:
224 r = s->regs[addr];
225 break;
226
227 default:
228 if (addr < ARRAY_SIZE(s->regs)) {
229 r = s->regs[addr];
230 }
231 break;
232
233 }
234 DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, r);
235 xlx_spi_update_irq(s);
236 return r;
237}
238
239static void
240spi_write(void *opaque, hwaddr addr,
241 uint64_t val64, unsigned int size)
242{
243 XilinxSPI *s = opaque;
244 uint32_t value = val64;
245
246 DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr, value);
247 addr >>= 2;
248 switch (addr) {
249 case R_SRR:
250 if (value != 0xa) {
251 DB_PRINT("Invalid write to SRR %x\n", value);
252 } else {
253 xlx_spi_do_reset(s);
254 }
255 break;
256
257 case R_SPIDTR:
258 s->regs[R_SPISR] &= ~SR_TX_EMPTY;
259 fifo8_push(&s->tx_fifo, (uint8_t)value);
260 if (fifo8_is_full(&s->tx_fifo)) {
261 s->regs[R_SPISR] |= SR_TX_FULL;
262 }
263 if (!spi_master_enabled(s)) {
264 goto done;
265 } else {
266 DB_PRINT("DTR and master enabled\n");
267 }
268 spi_flush_txfifo(s);
269 break;
270
271 case R_SPISR:
272 DB_PRINT("Invalid write to SPISR %x\n", value);
273 break;
274
275 case R_IPISR:
276
277 s->regs[addr] ^= value;
278 break;
279
280
281 case R_SPISSR:
282 s->regs[addr] = value;
283 xlx_spi_update_cs(s);
284 break;
285
286 case R_SPICR:
287
288 if (value & R_SPICR_RXFF_RST) {
289 rxfifo_reset(s);
290 }
291
292 if (value & R_SPICR_TXFF_RST) {
293 txfifo_reset(s);
294 }
295 value &= ~(R_SPICR_RXFF_RST | R_SPICR_TXFF_RST);
296 s->regs[addr] = value;
297
298 if (!(value & R_SPICR_MTI)) {
299 spi_flush_txfifo(s);
300 }
301 break;
302
303 default:
304 if (addr < ARRAY_SIZE(s->regs)) {
305 s->regs[addr] = value;
306 }
307 break;
308 }
309
310done:
311 xlx_spi_update_irq(s);
312}
313
314static const MemoryRegionOps spi_ops = {
315 .read = spi_read,
316 .write = spi_write,
317 .endianness = DEVICE_NATIVE_ENDIAN,
318 .valid = {
319 .min_access_size = 4,
320 .max_access_size = 4
321 }
322};
323
324static int xilinx_spi_init(SysBusDevice *sbd)
325{
326 DeviceState *dev = DEVICE(sbd);
327 XilinxSPI *s = XILINX_SPI(dev);
328 int i;
329
330 DB_PRINT("\n");
331
332 s->spi = ssi_create_bus(dev, "spi");
333
334 sysbus_init_irq(sbd, &s->irq);
335 s->cs_lines = g_new0(qemu_irq, s->num_cs);
336 ssi_auto_connect_slaves(dev, s->cs_lines, s->spi);
337 for (i = 0; i < s->num_cs; ++i) {
338 sysbus_init_irq(sbd, &s->cs_lines[i]);
339 }
340
341 memory_region_init_io(&s->mmio, OBJECT(s), &spi_ops, s,
342 "xilinx-spi", R_MAX * 4);
343 sysbus_init_mmio(sbd, &s->mmio);
344
345 s->irqline = -1;
346
347 fifo8_create(&s->tx_fifo, FIFO_CAPACITY);
348 fifo8_create(&s->rx_fifo, FIFO_CAPACITY);
349
350 return 0;
351}
352
353static const VMStateDescription vmstate_xilinx_spi = {
354 .name = "xilinx_spi",
355 .version_id = 1,
356 .minimum_version_id = 1,
357 .fields = (VMStateField[]) {
358 VMSTATE_FIFO8(tx_fifo, XilinxSPI),
359 VMSTATE_FIFO8(rx_fifo, XilinxSPI),
360 VMSTATE_UINT32_ARRAY(regs, XilinxSPI, R_MAX),
361 VMSTATE_END_OF_LIST()
362 }
363};
364
365static Property xilinx_spi_properties[] = {
366 DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1),
367 DEFINE_PROP_END_OF_LIST(),
368};
369
370static void xilinx_spi_class_init(ObjectClass *klass, void *data)
371{
372 DeviceClass *dc = DEVICE_CLASS(klass);
373 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
374
375 k->init = xilinx_spi_init;
376 dc->reset = xlx_spi_reset;
377 dc->props = xilinx_spi_properties;
378 dc->vmsd = &vmstate_xilinx_spi;
379}
380
381static const TypeInfo xilinx_spi_info = {
382 .name = TYPE_XILINX_SPI,
383 .parent = TYPE_SYS_BUS_DEVICE,
384 .instance_size = sizeof(XilinxSPI),
385 .class_init = xilinx_spi_class_init,
386};
387
388static void xilinx_spi_register_types(void)
389{
390 type_register_static(&xilinx_spi_info);
391}
392
393type_init(xilinx_spi_register_types)
394
