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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "sysemu/sysemu.h"
33#include "hw/boards.h"
34#include "hw/loader.h"
35#include "elf.h"
36#include "exec/memory.h"
37#include "exec/address-spaces.h"
38#include "hw/char/serial.h"
39#include "net/net.h"
40#include "hw/sysbus.h"
41#include "hw/block/flash.h"
42#include "sysemu/block-backend.h"
43#include "sysemu/char.h"
44#include "sysemu/device_tree.h"
45#include "qemu/error-report.h"
46#include "bootparam.h"
47
48typedef struct LxBoardDesc {
49 hwaddr flash_base;
50 size_t flash_size;
51 size_t flash_boot_base;
52 size_t flash_sector_size;
53 size_t sram_size;
54} LxBoardDesc;
55
56typedef struct Lx60FpgaState {
57 MemoryRegion iomem;
58 uint32_t leds;
59 uint32_t switches;
60} Lx60FpgaState;
61
62static void lx60_fpga_reset(void *opaque)
63{
64 Lx60FpgaState *s = opaque;
65
66 s->leds = 0;
67 s->switches = 0;
68}
69
70static uint64_t lx60_fpga_read(void *opaque, hwaddr addr,
71 unsigned size)
72{
73 Lx60FpgaState *s = opaque;
74
75 switch (addr) {
76 case 0x0:
77 return 0x09272011;
78
79 case 0x4:
80 return 10000000;
81
82 case 0x8:
83 return s->leds;
84
85 case 0xc:
86 return s->switches;
87 }
88 return 0;
89}
90
91static void lx60_fpga_write(void *opaque, hwaddr addr,
92 uint64_t val, unsigned size)
93{
94 Lx60FpgaState *s = opaque;
95
96 switch (addr) {
97 case 0x8:
98 s->leds = val;
99 break;
100
101 case 0x10:
102 if (val == 0xdead) {
103 qemu_system_reset_request();
104 }
105 break;
106 }
107}
108
109static const MemoryRegionOps lx60_fpga_ops = {
110 .read = lx60_fpga_read,
111 .write = lx60_fpga_write,
112 .endianness = DEVICE_NATIVE_ENDIAN,
113};
114
115static Lx60FpgaState *lx60_fpga_init(MemoryRegion *address_space,
116 hwaddr base)
117{
118 Lx60FpgaState *s = g_malloc(sizeof(Lx60FpgaState));
119
120 memory_region_init_io(&s->iomem, NULL, &lx60_fpga_ops, s,
121 "lx60.fpga", 0x10000);
122 memory_region_add_subregion(address_space, base, &s->iomem);
123 lx60_fpga_reset(s);
124 qemu_register_reset(lx60_fpga_reset, s);
125 return s;
126}
127
128static void lx60_net_init(MemoryRegion *address_space,
129 hwaddr base,
130 hwaddr descriptors,
131 hwaddr buffers,
132 qemu_irq irq, NICInfo *nd)
133{
134 DeviceState *dev;
135 SysBusDevice *s;
136 MemoryRegion *ram;
137
138 dev = qdev_create(NULL, "open_eth");
139 qdev_set_nic_properties(dev, nd);
140 qdev_init_nofail(dev);
141
142 s = SYS_BUS_DEVICE(dev);
143 sysbus_connect_irq(s, 0, irq);
144 memory_region_add_subregion(address_space, base,
145 sysbus_mmio_get_region(s, 0));
146 memory_region_add_subregion(address_space, descriptors,
147 sysbus_mmio_get_region(s, 1));
148
149 ram = g_malloc(sizeof(*ram));
150 memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384,
151 &error_fatal);
152 vmstate_register_ram_global(ram);
153 memory_region_add_subregion(address_space, buffers, ram);
154}
155
156static pflash_t *xtfpga_flash_init(MemoryRegion *address_space,
157 const LxBoardDesc *board,
158 DriveInfo *dinfo, int be)
159{
160 SysBusDevice *s;
161 DeviceState *dev = qdev_create(NULL, "cfi.pflash01");
162
163 qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo),
164 &error_abort);
165 qdev_prop_set_uint32(dev, "num-blocks",
166 board->flash_size / board->flash_sector_size);
167 qdev_prop_set_uint64(dev, "sector-length", board->flash_sector_size);
168 qdev_prop_set_uint8(dev, "width", 4);
169 qdev_prop_set_bit(dev, "big-endian", be);
170 qdev_prop_set_string(dev, "name", "lx60.io.flash");
171 qdev_init_nofail(dev);
172 s = SYS_BUS_DEVICE(dev);
173 memory_region_add_subregion(address_space, board->flash_base,
174 sysbus_mmio_get_region(s, 0));
175 return OBJECT_CHECK(pflash_t, (dev), "cfi.pflash01");
176}
177
178static uint64_t translate_phys_addr(void *opaque, uint64_t addr)
179{
180 XtensaCPU *cpu = opaque;
181
182 return cpu_get_phys_page_debug(CPU(cpu), addr);
183}
184
185static void lx60_reset(void *opaque)
186{
187 XtensaCPU *cpu = opaque;
188
189 cpu_reset(CPU(cpu));
190}
191
192static uint64_t lx60_io_read(void *opaque, hwaddr addr,
193 unsigned size)
194{
195 return 0;
196}
197
198static void lx60_io_write(void *opaque, hwaddr addr,
199 uint64_t val, unsigned size)
200{
201}
202
203static const MemoryRegionOps lx60_io_ops = {
204 .read = lx60_io_read,
205 .write = lx60_io_write,
206 .endianness = DEVICE_NATIVE_ENDIAN,
207};
208
209static void lx_init(const LxBoardDesc *board, MachineState *machine)
210{
211#ifdef TARGET_WORDS_BIGENDIAN
212 int be = 1;
213#else
214 int be = 0;
215#endif
216 MemoryRegion *system_memory = get_system_memory();
217 XtensaCPU *cpu = NULL;
218 CPUXtensaState *env = NULL;
219 MemoryRegion *ram, *rom, *system_io;
220 DriveInfo *dinfo;
221 pflash_t *flash = NULL;
222 QemuOpts *machine_opts = qemu_get_machine_opts();
223 const char *cpu_model = machine->cpu_model;
224 const char *kernel_filename = qemu_opt_get(machine_opts, "kernel");
225 const char *kernel_cmdline = qemu_opt_get(machine_opts, "append");
226 const char *dtb_filename = qemu_opt_get(machine_opts, "dtb");
227 const char *initrd_filename = qemu_opt_get(machine_opts, "initrd");
228 int n;
229
230 if (!cpu_model) {
231 cpu_model = XTENSA_DEFAULT_CPU_MODEL;
232 }
233
234 for (n = 0; n < smp_cpus; n++) {
235 cpu = cpu_xtensa_init(cpu_model);
236 if (cpu == NULL) {
237 error_report("unable to find CPU definition '%s'",
238 cpu_model);
239 exit(EXIT_FAILURE);
240 }
241 env = &cpu->env;
242
243 env->sregs[PRID] = n;
244 qemu_register_reset(lx60_reset, cpu);
245
246
247
248 cpu_reset(CPU(cpu));
249 }
250
251 ram = g_malloc(sizeof(*ram));
252 memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size,
253 &error_fatal);
254 vmstate_register_ram_global(ram);
255 memory_region_add_subregion(system_memory, 0, ram);
256
257 system_io = g_malloc(sizeof(*system_io));
258 memory_region_init_io(system_io, NULL, &lx60_io_ops, NULL, "lx60.io",
259 224 * 1024 * 1024);
260 memory_region_add_subregion(system_memory, 0xf0000000, system_io);
261 lx60_fpga_init(system_io, 0x0d020000);
262 if (nd_table[0].used) {
263 lx60_net_init(system_io, 0x0d030000, 0x0d030400, 0x0d800000,
264 xtensa_get_extint(env, 1), nd_table);
265 }
266
267 if (!serial_hds[0]) {
268 serial_hds[0] = qemu_chr_new("serial0", "null", NULL);
269 }
270
271 serial_mm_init(system_io, 0x0d050020, 2, xtensa_get_extint(env, 0),
272 115200, serial_hds[0], DEVICE_NATIVE_ENDIAN);
273
274 dinfo = drive_get(IF_PFLASH, 0, 0);
275 if (dinfo) {
276 flash = xtfpga_flash_init(system_io, board, dinfo, be);
277 }
278
279
280 if (kernel_filename) {
281 uint32_t entry_point = env->pc;
282 size_t bp_size = 3 * get_tag_size(0);
283 uint32_t tagptr = 0xfe000000 + board->sram_size;
284 uint32_t cur_tagptr;
285 BpMemInfo memory_location = {
286 .type = tswap32(MEMORY_TYPE_CONVENTIONAL),
287 .start = tswap32(0),
288 .end = tswap32(machine->ram_size),
289 };
290 uint32_t lowmem_end = machine->ram_size < 0x08000000 ?
291 machine->ram_size : 0x08000000;
292 uint32_t cur_lowmem = QEMU_ALIGN_UP(lowmem_end / 2, 4096);
293
294 rom = g_malloc(sizeof(*rom));
295 memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size,
296 &error_fatal);
297 vmstate_register_ram_global(rom);
298 memory_region_add_subregion(system_memory, 0xfe000000, rom);
299
300 if (kernel_cmdline) {
301 bp_size += get_tag_size(strlen(kernel_cmdline) + 1);
302 }
303 if (dtb_filename) {
304 bp_size += get_tag_size(sizeof(uint32_t));
305 }
306 if (initrd_filename) {
307 bp_size += get_tag_size(sizeof(BpMemInfo));
308 }
309
310
311 tagptr = (tagptr - bp_size) & ~0xff;
312 cur_tagptr = put_tag(tagptr, BP_TAG_FIRST, 0, NULL);
313 cur_tagptr = put_tag(cur_tagptr, BP_TAG_MEMORY,
314 sizeof(memory_location), &memory_location);
315
316 if (kernel_cmdline) {
317 cur_tagptr = put_tag(cur_tagptr, BP_TAG_COMMAND_LINE,
318 strlen(kernel_cmdline) + 1, kernel_cmdline);
319 }
320 if (dtb_filename) {
321 int fdt_size;
322 void *fdt = load_device_tree(dtb_filename, &fdt_size);
323 uint32_t dtb_addr = tswap32(cur_lowmem);
324
325 if (!fdt) {
326 error_report("could not load DTB '%s'", dtb_filename);
327 exit(EXIT_FAILURE);
328 }
329
330 cpu_physical_memory_write(cur_lowmem, fdt, fdt_size);
331 cur_tagptr = put_tag(cur_tagptr, BP_TAG_FDT,
332 sizeof(dtb_addr), &dtb_addr);
333 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + fdt_size, 4096);
334 }
335 if (initrd_filename) {
336 BpMemInfo initrd_location = { 0 };
337 int initrd_size = load_ramdisk(initrd_filename, cur_lowmem,
338 lowmem_end - cur_lowmem);
339
340 if (initrd_size < 0) {
341 initrd_size = load_image_targphys(initrd_filename,
342 cur_lowmem,
343 lowmem_end - cur_lowmem);
344 }
345 if (initrd_size < 0) {
346 error_report("could not load initrd '%s'", initrd_filename);
347 exit(EXIT_FAILURE);
348 }
349 initrd_location.start = tswap32(cur_lowmem);
350 initrd_location.end = tswap32(cur_lowmem + initrd_size);
351 cur_tagptr = put_tag(cur_tagptr, BP_TAG_INITRD,
352 sizeof(initrd_location), &initrd_location);
353 cur_lowmem = QEMU_ALIGN_UP(cur_lowmem + initrd_size, 4096);
354 }
355 cur_tagptr = put_tag(cur_tagptr, BP_TAG_LAST, 0, NULL);
356 env->regs[2] = tagptr;
357
358 uint64_t elf_entry;
359 uint64_t elf_lowaddr;
360 int success = load_elf(kernel_filename, translate_phys_addr, cpu,
361 &elf_entry, &elf_lowaddr, NULL, be, EM_XTENSA, 0, 0);
362 if (success > 0) {
363 entry_point = elf_entry;
364 } else {
365 hwaddr ep;
366 int is_linux;
367 success = load_uimage(kernel_filename, &ep, NULL, &is_linux,
368 translate_phys_addr, cpu);
369 if (success > 0 && is_linux) {
370 entry_point = ep;
371 } else {
372 error_report("could not load kernel '%s'",
373 kernel_filename);
374 exit(EXIT_FAILURE);
375 }
376 }
377 if (entry_point != env->pc) {
378 static const uint8_t jx_a0[] = {
379#ifdef TARGET_WORDS_BIGENDIAN
380 0x0a, 0, 0,
381#else
382 0xa0, 0, 0,
383#endif
384 };
385 env->regs[0] = entry_point;
386 cpu_physical_memory_write(env->pc, jx_a0, sizeof(jx_a0));
387 }
388 } else {
389 if (flash) {
390 MemoryRegion *flash_mr = pflash_cfi01_get_memory(flash);
391 MemoryRegion *flash_io = g_malloc(sizeof(*flash_io));
392
393 memory_region_init_alias(flash_io, NULL, "lx60.flash",
394 flash_mr, board->flash_boot_base,
395 board->flash_size - board->flash_boot_base < 0x02000000 ?
396 board->flash_size - board->flash_boot_base : 0x02000000);
397 memory_region_add_subregion(system_memory, 0xfe000000,
398 flash_io);
399 }
400 }
401}
402
403static void xtensa_lx60_init(MachineState *machine)
404{
405 static const LxBoardDesc lx60_board = {
406 .flash_base = 0x08000000,
407 .flash_size = 0x00400000,
408 .flash_sector_size = 0x10000,
409 .sram_size = 0x20000,
410 };
411 lx_init(&lx60_board, machine);
412}
413
414static void xtensa_lx200_init(MachineState *machine)
415{
416 static const LxBoardDesc lx200_board = {
417 .flash_base = 0x08000000,
418 .flash_size = 0x01000000,
419 .flash_sector_size = 0x20000,
420 .sram_size = 0x2000000,
421 };
422 lx_init(&lx200_board, machine);
423}
424
425static void xtensa_ml605_init(MachineState *machine)
426{
427 static const LxBoardDesc ml605_board = {
428 .flash_base = 0x08000000,
429 .flash_size = 0x01000000,
430 .flash_sector_size = 0x20000,
431 .sram_size = 0x2000000,
432 };
433 lx_init(&ml605_board, machine);
434}
435
436static void xtensa_kc705_init(MachineState *machine)
437{
438 static const LxBoardDesc kc705_board = {
439 .flash_base = 0x00000000,
440 .flash_size = 0x08000000,
441 .flash_boot_base = 0x06000000,
442 .flash_sector_size = 0x20000,
443 .sram_size = 0x2000000,
444 };
445 lx_init(&kc705_board, machine);
446}
447
448static void xtensa_lx60_class_init(ObjectClass *oc, void *data)
449{
450 MachineClass *mc = MACHINE_CLASS(oc);
451
452 mc->desc = "lx60 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
453 mc->init = xtensa_lx60_init;
454 mc->max_cpus = 4;
455}
456
457static const TypeInfo xtensa_lx60_type = {
458 .name = MACHINE_TYPE_NAME("lx60"),
459 .parent = TYPE_MACHINE,
460 .class_init = xtensa_lx60_class_init,
461};
462
463static void xtensa_lx200_class_init(ObjectClass *oc, void *data)
464{
465 MachineClass *mc = MACHINE_CLASS(oc);
466
467 mc->desc = "lx200 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
468 mc->init = xtensa_lx200_init;
469 mc->max_cpus = 4;
470}
471
472static const TypeInfo xtensa_lx200_type = {
473 .name = MACHINE_TYPE_NAME("lx200"),
474 .parent = TYPE_MACHINE,
475 .class_init = xtensa_lx200_class_init,
476};
477
478static void xtensa_ml605_class_init(ObjectClass *oc, void *data)
479{
480 MachineClass *mc = MACHINE_CLASS(oc);
481
482 mc->desc = "ml605 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
483 mc->init = xtensa_ml605_init;
484 mc->max_cpus = 4;
485}
486
487static const TypeInfo xtensa_ml605_type = {
488 .name = MACHINE_TYPE_NAME("ml605"),
489 .parent = TYPE_MACHINE,
490 .class_init = xtensa_ml605_class_init,
491};
492
493static void xtensa_kc705_class_init(ObjectClass *oc, void *data)
494{
495 MachineClass *mc = MACHINE_CLASS(oc);
496
497 mc->desc = "kc705 EVB (" XTENSA_DEFAULT_CPU_MODEL ")";
498 mc->init = xtensa_kc705_init;
499 mc->max_cpus = 4;
500}
501
502static const TypeInfo xtensa_kc705_type = {
503 .name = MACHINE_TYPE_NAME("kc705"),
504 .parent = TYPE_MACHINE,
505 .class_init = xtensa_kc705_class_init,
506};
507
508static void xtensa_lx_machines_init(void)
509{
510 type_register_static(&xtensa_lx60_type);
511 type_register_static(&xtensa_lx200_type);
512 type_register_static(&xtensa_ml605_type);
513 type_register_static(&xtensa_kc705_type);
514}
515
516type_init(xtensa_lx_machines_init)
517
