LXR qemu/include/exec/cpu-common.h

   1#ifndef CPU_COMMON_H
   2#define CPU_COMMON_H 1
   3
   4/* CPU interfaces that are target independent.  */
   5
   6#ifndef CONFIG_USER_ONLY
   7#include "exec/hwaddr.h"
   8#endif
   9
  10#ifndef NEED_CPU_H
  11#include "exec/poison.h"
  12#endif
  13
  14#include "qemu/bswap.h"
  15#include "qemu/queue.h"
  16#include "qemu/fprintf-fn.h"
  17
  18/**
  19 * CPUListState:
  20 * @cpu_fprintf: Print function.
  21 * @file: File to print to using @cpu_fprint.
  22 *
  23 * State commonly used for iterating over CPU models.
  24 */
  25typedef struct CPUListState {
  26    fprintf_function cpu_fprintf;
  27    FILE *file;
  28} CPUListState;
  29
  30typedef enum MMUAccessType {
  31    MMU_DATA_LOAD  = 0,
  32    MMU_DATA_STORE = 1,
  33    MMU_INST_FETCH = 2
  34} MMUAccessType;
  35
  36#if !defined(CONFIG_USER_ONLY)
  37
  38enum device_endian {
  39    DEVICE_NATIVE_ENDIAN,
  40    DEVICE_BIG_ENDIAN,
  41    DEVICE_LITTLE_ENDIAN,
  42};
  43
  44/* address in the RAM (different from a physical address) */
  45#if defined(CONFIG_XEN_BACKEND)
  46typedef uint64_t ram_addr_t;
  47#  define RAM_ADDR_MAX UINT64_MAX
  48#  define RAM_ADDR_FMT "%" PRIx64
  49#else
  50typedef uintptr_t ram_addr_t;
  51#  define RAM_ADDR_MAX UINTPTR_MAX
  52#  define RAM_ADDR_FMT "%" PRIxPTR
  53#endif
  54
  55extern ram_addr_t ram_size;
  56
  57/* memory API */
  58
  59typedef void CPUWriteMemoryFunc(void *opaque, hwaddr addr, uint32_t value);
  60typedef uint32_t CPUReadMemoryFunc(void *opaque, hwaddr addr);
  61
  62void qemu_ram_remap(ram_addr_t addr, ram_addr_t length);
  63/* This should not be used by devices.  */
  64MemoryRegion *qemu_ram_addr_from_host(void *ptr, ram_addr_t *ram_addr);
  65RAMBlock *qemu_ram_block_by_name(const char *name);
  66RAMBlock *qemu_ram_block_from_host(void *ptr, bool round_offset,
  67                                   ram_addr_t *ram_addr, ram_addr_t *offset);
  68void qemu_ram_set_idstr(ram_addr_t addr, const char *name, DeviceState *dev);
  69void qemu_ram_unset_idstr(ram_addr_t addr);
  70const char *qemu_ram_get_idstr(RAMBlock *rb);
  71
  72void cpu_physical_memory_rw(hwaddr addr, uint8_t *buf,
  73                            int len, int is_write);
  74static inline void cpu_physical_memory_read(hwaddr addr,
  75                                            void *buf, int len)
  76{
  77    cpu_physical_memory_rw(addr, buf, len, 0);
  78}
  79static inline void cpu_physical_memory_write(hwaddr addr,
  80                                             const void *buf, int len)
  81{
  82    cpu_physical_memory_rw(addr, (void *)buf, len, 1);
  83}
  84void *cpu_physical_memory_map(hwaddr addr,
  85                              hwaddr *plen,
  86                              int is_write);
  87void cpu_physical_memory_unmap(void *buffer, hwaddr len,
  88                               int is_write, hwaddr access_len);
  89void cpu_register_map_client(QEMUBH *bh);
  90void cpu_unregister_map_client(QEMUBH *bh);
  91
  92bool cpu_physical_memory_is_io(hwaddr phys_addr);
  93
  94/* Coalesced MMIO regions are areas where write operations can be reordered.
  95 * This usually implies that write operations are side-effect free.  This allows
  96 * batching which can make a major impact on performance when using
  97 * virtualization.
  98 */
  99void qemu_flush_coalesced_mmio_buffer(void);
 100
 101uint32_t ldub_phys(AddressSpace *as, hwaddr addr);
 102uint32_t lduw_le_phys(AddressSpace *as, hwaddr addr);
 103uint32_t lduw_be_phys(AddressSpace *as, hwaddr addr);
 104uint32_t ldl_le_phys(AddressSpace *as, hwaddr addr);
 105uint32_t ldl_be_phys(AddressSpace *as, hwaddr addr);
 106uint64_t ldq_le_phys(AddressSpace *as, hwaddr addr);
 107uint64_t ldq_be_phys(AddressSpace *as, hwaddr addr);
 108void stb_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 109void stw_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 110void stw_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 111void stl_le_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 112void stl_be_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 113void stq_le_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 114void stq_be_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 115
 116#ifdef NEED_CPU_H
 117uint32_t lduw_phys(AddressSpace *as, hwaddr addr);
 118uint32_t ldl_phys(AddressSpace *as, hwaddr addr);
 119uint64_t ldq_phys(AddressSpace *as, hwaddr addr);
 120void stl_phys_notdirty(AddressSpace *as, hwaddr addr, uint32_t val);
 121void stw_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 122void stl_phys(AddressSpace *as, hwaddr addr, uint32_t val);
 123void stq_phys(AddressSpace *as, hwaddr addr, uint64_t val);
 124#endif
 125
 126void cpu_physical_memory_write_rom(AddressSpace *as, hwaddr addr,
 127                                   const uint8_t *buf, int len);
 128void cpu_flush_icache_range(hwaddr start, int len);
 129
 130extern struct MemoryRegion io_mem_rom;
 131extern struct MemoryRegion io_mem_notdirty;
 132
 133typedef int (RAMBlockIterFunc)(const char *block_name, void *host_addr,
 134    ram_addr_t offset, ram_addr_t length, void *opaque);
 135
 136int qemu_ram_foreach_block(RAMBlockIterFunc func, void *opaque);
 137
 138#endif
 139
 140#endif /* !CPU_COMMON_H */
 141