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9#ifndef PXA_H
10# define PXA_H "pxa.h"
11
12#include "exec/memory.h"
13#include "target-arm/cpu-qom.h"
14
15
16# define PXA2XX_PIC_SSP3 0
17# define PXA2XX_PIC_USBH2 2
18# define PXA2XX_PIC_USBH1 3
19# define PXA2XX_PIC_KEYPAD 4
20# define PXA2XX_PIC_PWRI2C 6
21# define PXA25X_PIC_HWUART 7
22# define PXA27X_PIC_OST_4_11 7
23# define PXA2XX_PIC_GPIO_0 8
24# define PXA2XX_PIC_GPIO_1 9
25# define PXA2XX_PIC_GPIO_X 10
26# define PXA2XX_PIC_I2S 13
27# define PXA26X_PIC_ASSP 15
28# define PXA25X_PIC_NSSP 16
29# define PXA27X_PIC_SSP2 16
30# define PXA2XX_PIC_LCD 17
31# define PXA2XX_PIC_I2C 18
32# define PXA2XX_PIC_ICP 19
33# define PXA2XX_PIC_STUART 20
34# define PXA2XX_PIC_BTUART 21
35# define PXA2XX_PIC_FFUART 22
36# define PXA2XX_PIC_MMC 23
37# define PXA2XX_PIC_SSP 24
38# define PXA2XX_PIC_DMA 25
39# define PXA2XX_PIC_OST_0 26
40# define PXA2XX_PIC_RTC1HZ 30
41# define PXA2XX_PIC_RTCALARM 31
42
43
44# define PXA2XX_RX_RQ_I2S 2
45# define PXA2XX_TX_RQ_I2S 3
46# define PXA2XX_RX_RQ_BTUART 4
47# define PXA2XX_TX_RQ_BTUART 5
48# define PXA2XX_RX_RQ_FFUART 6
49# define PXA2XX_TX_RQ_FFUART 7
50# define PXA2XX_RX_RQ_SSP1 13
51# define PXA2XX_TX_RQ_SSP1 14
52# define PXA2XX_RX_RQ_SSP2 15
53# define PXA2XX_TX_RQ_SSP2 16
54# define PXA2XX_RX_RQ_ICP 17
55# define PXA2XX_TX_RQ_ICP 18
56# define PXA2XX_RX_RQ_STUART 19
57# define PXA2XX_TX_RQ_STUART 20
58# define PXA2XX_RX_RQ_MMCI 21
59# define PXA2XX_TX_RQ_MMCI 22
60# define PXA2XX_USB_RQ(x) ((x) + 24)
61# define PXA2XX_RX_RQ_SSP3 66
62# define PXA2XX_TX_RQ_SSP3 67
63
64# define PXA2XX_SDRAM_BASE 0xa0000000
65# define PXA2XX_INTERNAL_BASE 0x5c000000
66# define PXA2XX_INTERNAL_SIZE 0x40000
67
68
69DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu);
70
71
72DeviceState *pxa2xx_gpio_init(hwaddr base,
73 ARMCPU *cpu, DeviceState *pic, int lines);
74void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
75
76
77DeviceState *pxa255_dma_init(hwaddr base, qemu_irq irq);
78DeviceState *pxa27x_dma_init(hwaddr base, qemu_irq irq);
79
80
81typedef struct PXA2xxLCDState PXA2xxLCDState;
82PXA2xxLCDState *pxa2xx_lcdc_init(MemoryRegion *sysmem,
83 hwaddr base, qemu_irq irq);
84void pxa2xx_lcd_vsync_notifier(PXA2xxLCDState *s, qemu_irq handler);
85void pxa2xx_lcdc_oritentation(void *opaque, int angle);
86
87
88typedef struct PXA2xxMMCIState PXA2xxMMCIState;
89PXA2xxMMCIState *pxa2xx_mmci_init(MemoryRegion *sysmem,
90 hwaddr base,
91 BlockBackend *blk, qemu_irq irq,
92 qemu_irq rx_dma, qemu_irq tx_dma);
93void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
94 qemu_irq coverswitch);
95
96
97typedef struct PXA2xxPCMCIAState PXA2xxPCMCIAState;
98PXA2xxPCMCIAState *pxa2xx_pcmcia_init(MemoryRegion *sysmem,
99 hwaddr base);
100int pxa2xx_pcmcia_attach(void *opaque, PCMCIACardState *card);
101int pxa2xx_pcmcia_detach(void *opaque);
102void pxa2xx_pcmcia_set_irq_cb(void *opaque, qemu_irq irq, qemu_irq cd_irq);
103
104
105struct keymap {
106 int8_t column;
107 int8_t row;
108};
109typedef struct PXA2xxKeyPadState PXA2xxKeyPadState;
110PXA2xxKeyPadState *pxa27x_keypad_init(MemoryRegion *sysmem,
111 hwaddr base,
112 qemu_irq irq);
113void pxa27x_register_keypad(PXA2xxKeyPadState *kp,
114 const struct keymap *map, int size);
115
116
117typedef struct PXA2xxI2CState PXA2xxI2CState;
118PXA2xxI2CState *pxa2xx_i2c_init(hwaddr base,
119 qemu_irq irq, uint32_t page_size);
120I2CBus *pxa2xx_i2c_bus(PXA2xxI2CState *s);
121
122typedef struct PXA2xxI2SState PXA2xxI2SState;
123typedef struct PXA2xxFIrState PXA2xxFIrState;
124
125typedef struct {
126 ARMCPU *cpu;
127 DeviceState *pic;
128 qemu_irq reset;
129 MemoryRegion sdram;
130 MemoryRegion internal;
131 MemoryRegion cm_iomem;
132 MemoryRegion mm_iomem;
133 MemoryRegion pm_iomem;
134 DeviceState *dma;
135 DeviceState *gpio;
136 PXA2xxLCDState *lcd;
137 SSIBus **ssp;
138 PXA2xxI2CState *i2c[2];
139 PXA2xxMMCIState *mmc;
140 PXA2xxPCMCIAState *pcmcia[2];
141 PXA2xxI2SState *i2s;
142 PXA2xxFIrState *fir;
143 PXA2xxKeyPadState *kp;
144
145
146 hwaddr pm_base;
147 uint32_t pm_regs[0x40];
148
149
150 hwaddr cm_base;
151 uint32_t cm_regs[4];
152 uint32_t clkcfg;
153
154
155 hwaddr mm_base;
156 uint32_t mm_regs[0x1a];
157
158
159 uint32_t pmnc;
160} PXA2xxState;
161
162struct PXA2xxI2SState {
163 MemoryRegion iomem;
164 qemu_irq irq;
165 qemu_irq rx_dma;
166 qemu_irq tx_dma;
167 void (*data_req)(void *, int, int);
168
169 uint32_t control[2];
170 uint32_t status;
171 uint32_t mask;
172 uint32_t clk;
173
174 int enable;
175 int rx_len;
176 int tx_len;
177 void (*codec_out)(void *, uint32_t);
178 uint32_t (*codec_in)(void *);
179 void *opaque;
180
181 int fifo_len;
182 uint32_t fifo[16];
183};
184
185# define PA_FMT "0x%08lx"
186# define REG_FMT "0x" TARGET_FMT_plx
187
188PXA2xxState *pxa270_init(MemoryRegion *address_space, unsigned int sdram_size,
189 const char *revision);
190PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size);
191
192#endif
193
