LXR qemu/include/hw/arm/xlnx-zynqmp.h

   1/*
   2 * Xilinx Zynq MPSoC emulation
   3 *
   4 * Copyright (C) 2015 Xilinx Inc
   5 * Written by Peter Crosthwaite <peter.crosthwaite@xilinx.com>
   6 *
   7 * This program is free software; you can redistribute it and/or modify it
   8 * under the terms of the GNU General Public License as published by the
   9 * Free Software Foundation; either version 2 of the License, or
  10 * (at your option) any later version.
  11 *
  12 * This program is distributed in the hope that it will be useful, but WITHOUT
  13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
  15 * for more details.
  16 */
  17
  18#ifndef XLNX_ZYNQMP_H
  19
  20#include "qemu-common.h"
  21#include "hw/arm/arm.h"
  22#include "hw/intc/arm_gic.h"
  23#include "hw/net/cadence_gem.h"
  24#include "hw/char/cadence_uart.h"
  25#include "hw/ide/pci.h"
  26#include "hw/ide/ahci.h"
  27#include "hw/sd/sdhci.h"
  28#include "hw/ssi/xilinx_spips.h"
  29
  30#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
  31#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
  32                                       TYPE_XLNX_ZYNQMP)
  33
  34#define XLNX_ZYNQMP_NUM_APU_CPUS 4
  35#define XLNX_ZYNQMP_NUM_RPU_CPUS 2
  36#define XLNX_ZYNQMP_NUM_GEMS 4
  37#define XLNX_ZYNQMP_NUM_UARTS 2
  38#define XLNX_ZYNQMP_NUM_SDHCI 2
  39#define XLNX_ZYNQMP_NUM_SPIS 2
  40
  41#define XLNX_ZYNQMP_NUM_OCM_BANKS 4
  42#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
  43#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
  44
  45#define XLNX_ZYNQMP_GIC_REGIONS 2
  46
  47/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
  48 * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
  49 * aligned address in the 64k region. To implement each GIC region needs a
  50 * number of memory region aliases.
  51 */
  52
  53#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
  54#define XLNX_ZYNQMP_GIC_ALIASES     (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
  55
  56#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE    0x80000000ull
  57
  58#define XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE   0x800000000ull
  59#define XLNX_ZYNQMP_HIGH_RAM_START      0x800000000ull
  60
  61#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
  62                                  XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
  63
  64typedef struct XlnxZynqMPState {
  65    /*< private >*/
  66    DeviceState parent_obj;
  67
  68    /*< public >*/
  69    ARMCPU apu_cpu[XLNX_ZYNQMP_NUM_APU_CPUS];
  70    ARMCPU rpu_cpu[XLNX_ZYNQMP_NUM_RPU_CPUS];
  71    GICState gic;
  72    MemoryRegion gic_mr[XLNX_ZYNQMP_GIC_REGIONS][XLNX_ZYNQMP_GIC_ALIASES];
  73
  74    MemoryRegion ocm_ram[XLNX_ZYNQMP_NUM_OCM_BANKS];
  75
  76    MemoryRegion *ddr_ram;
  77    MemoryRegion ddr_ram_low, ddr_ram_high;
  78
  79    CadenceGEMState gem[XLNX_ZYNQMP_NUM_GEMS];
  80    CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
  81    SysbusAHCIState sata;
  82    SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
  83    XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
  84
  85    char *boot_cpu;
  86    ARMCPU *boot_cpu_ptr;
  87}  XlnxZynqMPState;
  88
  89#define XLNX_ZYNQMP_H
  90#endif
  91