LXR qemu/include/hw/block/flash.h

   1#ifndef HW_FLASH_H
   2#define HW_FLASH_H 1
   3
   4/* NOR flash devices */
   5
   6#include "exec/memory.h"
   7
   8typedef struct pflash_t pflash_t;
   9
  10/* pflash_cfi01.c */
  11pflash_t *pflash_cfi01_register(hwaddr base,
  12                                DeviceState *qdev, const char *name,
  13                                hwaddr size,
  14                                BlockBackend *blk,
  15                                uint32_t sector_len, int nb_blocs, int width,
  16                                uint16_t id0, uint16_t id1,
  17                                uint16_t id2, uint16_t id3, int be);
  18
  19/* pflash_cfi02.c */
  20pflash_t *pflash_cfi02_register(hwaddr base,
  21                                DeviceState *qdev, const char *name,
  22                                hwaddr size,
  23                                BlockBackend *blk, uint32_t sector_len,
  24                                int nb_blocs, int nb_mappings, int width,
  25                                uint16_t id0, uint16_t id1,
  26                                uint16_t id2, uint16_t id3,
  27                                uint16_t unlock_addr0, uint16_t unlock_addr1,
  28                                int be);
  29
  30MemoryRegion *pflash_cfi01_get_memory(pflash_t *fl);
  31
  32/* nand.c */
  33DeviceState *nand_init(BlockBackend *blk, int manf_id, int chip_id);
  34void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
  35                  uint8_t ce, uint8_t wp, uint8_t gnd);
  36void nand_getpins(DeviceState *dev, int *rb);
  37void nand_setio(DeviceState *dev, uint32_t value);
  38uint32_t nand_getio(DeviceState *dev);
  39uint32_t nand_getbuswidth(DeviceState *dev);
  40
  41#define NAND_MFR_TOSHIBA        0x98
  42#define NAND_MFR_SAMSUNG        0xec
  43#define NAND_MFR_FUJITSU        0x04
  44#define NAND_MFR_NATIONAL       0x8f
  45#define NAND_MFR_RENESAS        0x07
  46#define NAND_MFR_STMICRO        0x20
  47#define NAND_MFR_HYNIX          0xad
  48#define NAND_MFR_MICRON         0x2c
  49
  50/* onenand.c */
  51void *onenand_raw_otp(DeviceState *onenand_device);
  52
  53/* ecc.c */
  54typedef struct {
  55    uint8_t cp;         /* Column parity */
  56    uint16_t lp[2];     /* Line parity */
  57    uint16_t count;
  58} ECCState;
  59
  60uint8_t ecc_digest(ECCState *s, uint8_t sample);
  61void ecc_reset(ECCState *s);
  62extern VMStateDescription vmstate_ecc_state;
  63
  64#endif
  65