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20#ifndef QEMU_APIC_INTERNAL_H
21#define QEMU_APIC_INTERNAL_H
22
23#include "cpu.h"
24#include "exec/memory.h"
25#include "qemu/timer.h"
26
27
28#define APIC_LVT_TIMER 0
29#define APIC_LVT_THERMAL 1
30#define APIC_LVT_PERFORM 2
31#define APIC_LVT_LINT0 3
32#define APIC_LVT_LINT1 4
33#define APIC_LVT_ERROR 5
34#define APIC_LVT_NB 6
35
36
37#define APIC_DM_FIXED 0
38#define APIC_DM_LOWPRI 1
39#define APIC_DM_SMI 2
40#define APIC_DM_NMI 4
41#define APIC_DM_INIT 5
42#define APIC_DM_SIPI 6
43#define APIC_DM_EXTINT 7
44
45
46#define APIC_DESTMODE_FLAT 0xf
47#define APIC_DESTMODE_CLUSTER 1
48
49#define APIC_TRIGGER_EDGE 0
50#define APIC_TRIGGER_LEVEL 1
51
52#define APIC_VECTOR_MASK 0xff
53#define APIC_DCR_MASK 0xf
54
55#define APIC_LVT_TIMER_SHIFT 17
56#define APIC_LVT_MASKED_SHIFT 16
57#define APIC_LVT_LEVEL_TRIGGER_SHIFT 15
58#define APIC_LVT_REMOTE_IRR_SHIFT 14
59#define APIC_LVT_INT_POLARITY_SHIFT 13
60#define APIC_LVT_DELIV_STS_SHIFT 12
61#define APIC_LVT_DELIV_MOD_SHIFT 8
62
63#define APIC_LVT_TIMER_TSCDEADLINE (2 << APIC_LVT_TIMER_SHIFT)
64#define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
65#define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
66#define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
67#define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
68#define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
69#define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
70#define APIC_LVT_DELIV_MOD (7 << APIC_LVT_DELIV_MOD_SHIFT)
71
72#define APIC_ESR_ILL_ADDRESS_SHIFT 7
73#define APIC_ESR_RECV_ILL_VECT_SHIFT 6
74#define APIC_ESR_SEND_ILL_VECT_SHIFT 5
75#define APIC_ESR_RECV_ACCEPT_SHIFT 3
76#define APIC_ESR_SEND_ACCEPT_SHIFT 2
77#define APIC_ESR_RECV_CHECK_SUM_SHIFT 1
78
79#define APIC_ESR_ILLEGAL_ADDRESS (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
80#define APIC_ESR_RECV_ILLEGAL_VECT (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
81#define APIC_ESR_SEND_ILLEGAL_VECT (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
82#define APIC_ESR_RECV_ACCEPT (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
83#define APIC_ESR_SEND_ACCEPT (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
84#define APIC_ESR_RECV_CHECK_SUM (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
85#define APIC_ESR_SEND_CHECK_SUM 1
86
87#define APIC_ICR_DEST_SHIFT 24
88#define APIC_ICR_DEST_SHORT_SHIFT 18
89#define APIC_ICR_TRIGGER_MOD_SHIFT 15
90#define APIC_ICR_LEVEL_SHIFT 14
91#define APIC_ICR_DELIV_STS_SHIFT 12
92#define APIC_ICR_DEST_MOD_SHIFT 11
93#define APIC_ICR_DELIV_MOD_SHIFT 8
94
95#define APIC_ICR_DEST_SHORT (3 << APIC_ICR_DEST_SHORT_SHIFT)
96#define APIC_ICR_TRIGGER_MOD (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
97#define APIC_ICR_LEVEL (1 << APIC_ICR_LEVEL_SHIFT)
98#define APIC_ICR_DELIV_STS (1 << APIC_ICR_DELIV_STS_SHIFT)
99#define APIC_ICR_DEST_MOD (1 << APIC_ICR_DEST_MOD_SHIFT)
100#define APIC_ICR_DELIV_MOD (7 << APIC_ICR_DELIV_MOD_SHIFT)
101
102#define APIC_PR_CLASS_SHIFT 4
103#define APIC_PR_SUB_CLASS 0xf
104
105#define APIC_LOGDEST_XAPIC_SHIFT 4
106#define APIC_LOGDEST_XAPIC_ID 0xf
107
108#define APIC_LOGDEST_X2APIC_SHIFT 16
109#define APIC_LOGDEST_X2APIC_ID 0xffff
110
111#define APIC_SPURIO_FOCUS_SHIFT 9
112#define APIC_SPURIO_ENABLED_SHIFT 8
113
114#define APIC_SPURIO_FOCUS (1 << APIC_SPURIO_FOCUS_SHIFT)
115#define APIC_SPURIO_ENABLED (1 << APIC_SPURIO_ENABLED_SHIFT)
116
117#define APIC_SV_DIRECTED_IO (1 << 12)
118#define APIC_SV_ENABLE (1 << 8)
119
120#define VAPIC_ENABLE_BIT 0
121#define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
122
123#define MAX_APICS 255
124
125typedef struct APICCommonState APICCommonState;
126
127#define TYPE_APIC_COMMON "apic-common"
128#define APIC_COMMON(obj) \
129 OBJECT_CHECK(APICCommonState, (obj), TYPE_APIC_COMMON)
130#define APIC_COMMON_CLASS(klass) \
131 OBJECT_CLASS_CHECK(APICCommonClass, (klass), TYPE_APIC_COMMON)
132#define APIC_COMMON_GET_CLASS(obj) \
133 OBJECT_GET_CLASS(APICCommonClass, (obj), TYPE_APIC_COMMON)
134
135typedef struct APICCommonClass
136{
137 DeviceClass parent_class;
138
139 DeviceRealize realize;
140 void (*set_base)(APICCommonState *s, uint64_t val);
141 void (*set_tpr)(APICCommonState *s, uint8_t val);
142 uint8_t (*get_tpr)(APICCommonState *s);
143 void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
144 void (*vapic_base_update)(APICCommonState *s);
145 void (*external_nmi)(APICCommonState *s);
146 void (*pre_save)(APICCommonState *s);
147 void (*post_load)(APICCommonState *s);
148 void (*reset)(APICCommonState *s);
149} APICCommonClass;
150
151struct APICCommonState {
152
153 DeviceState parent_obj;
154
155
156 MemoryRegion io_memory;
157 X86CPU *cpu;
158 uint32_t apicbase;
159 uint8_t id;
160 uint8_t version;
161 uint8_t arb_id;
162 uint8_t tpr;
163 uint32_t spurious_vec;
164 uint8_t log_dest;
165 uint8_t dest_mode;
166 uint32_t isr[8];
167 uint32_t tmr[8];
168 uint32_t irr[8];
169 uint32_t lvt[APIC_LVT_NB];
170 uint32_t esr;
171 uint32_t icr[2];
172
173 uint32_t divide_conf;
174 int count_shift;
175 uint32_t initial_count;
176 int64_t initial_count_load_time;
177 int64_t next_time;
178 int idx;
179 QEMUTimer *timer;
180 int64_t timer_expiry;
181 int sipi_vector;
182 int wait_for_sipi;
183
184 uint32_t vapic_control;
185 DeviceState *vapic;
186 hwaddr vapic_paddr;
187};
188
189typedef struct VAPICState {
190 uint8_t tpr;
191 uint8_t isr;
192 uint8_t zero;
193 uint8_t irr;
194 uint8_t enabled;
195} QEMU_PACKED VAPICState;
196
197extern bool apic_report_tpr_access;
198
199void apic_report_irq_delivered(int delivered);
200bool apic_next_timer(APICCommonState *s, int64_t current_time);
201void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
202void apic_enable_vapic(DeviceState *d, hwaddr paddr);
203
204void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
205 TPRAccess access);
206
207int apic_get_ppr(APICCommonState *s);
208
209static inline void apic_set_bit(uint32_t *tab, int index)
210{
211 int i, mask;
212 i = index >> 5;
213 mask = 1 << (index & 0x1f);
214 tab[i] |= mask;
215}
216
217static inline int apic_get_bit(uint32_t *tab, int index)
218{
219 int i, mask;
220 i = index >> 5;
221 mask = 1 << (index & 0x1f);
222 return !!(tab[i] & mask);
223}
224
225#endif
226
