LXR qemu/include/hw/mdio/eth

   1/*
   2 * QEMU Ethernet MDIO bus & PHY models
   3 *
   4 * Copyright (c) 2008 Edgar E. Iglesias (edgari@xilinx.com),
   5 *                          Grant Likely (grant.likely@secretlab.ca),
   6 * Copyright (c) 2016 Xilinx Inc.
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 *
  26 */
  27
  28#ifndef ETH_PHY_H
  29#define ETH_PHY_H
  30
  31#include "qemu-common.h"
  32
  33/* PHY MII Register/Bit Definitions */
  34/* PHY Registers defined by IEEE */
  35#define PHY_CTRL         0x00 /* Control Register */
  36#define PHY_STATUS       0x01 /* Status Regiser */
  37#define PHY_ID1          0x02 /* Phy Id Reg (word 1) */
  38#define PHY_ID2          0x03 /* Phy Id Reg (word 2) */
  39#define PHY_AUTONEG_ADV  0x04 /* Autoneg Advertisement */
  40#define PHY_LP_ABILITY   0x05 /* Link Partner Ability (Base Page) */
  41#define PHY_AUTONEG_EXP  0x06 /* Autoneg Expansion Reg */
  42#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
  43#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
  44#define PHY_1000T_CTRL   0x09 /* 1000Base-T Control Reg */
  45#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
  46#define PHY_EXT_STATUS   0x0F /* Extended Status Reg */
  47#define PHY_SPEC_CTRL    0x10 /* PHY Specific control reg */
  48#define PHY_SPEC_STATUS  0x11 /* PHY Specific status reg */
  49#define NUM_PHY_REGS     0x1F  /* 5 bit address bus (0-0x1F) */
  50
  51/*Control Register bitfeild offsets*/
  52#define PHY_CTRL_REG_UNIDIR_EN      5
  53#define PHY_CTRLREG_SPEED_SEL_MSB   6
  54#define PHY_CTRLREG_COLLISION_TEST  7
  55#define PHY_CTRLREG_DUPLEX_MODE     8
  56#define PHY_CTRLREG_RST_AUTONEG     9
  57#define PHY_CTRLREG_ISOLATE         10
  58#define PHY_CTRLREG_POWER_DWN       11
  59#define PHY_CTRLREG_AUTONEG_EN      12
  60#define PHY_CTRLREG_SPEED_SEL_LSB   13
  61#define PHY_CTRLREG_LOOPBACK        14
  62#define PHY_CTRLREG_RESET           15
  63
  64/*Status Register bitfeild offsets */
  65#define PHY_STAT_EXT_CAP        0
  66#define PHY_STAT_JAB_DETECT     1
  67#define PHY_STAT_LINK_STAT      2
  68#define PHY_STAT_AUTONEG_CAP    3
  69#define PHY_STAT_REMOTE_FAL     4
  70#define PHY_STAT_AUTONEG_COMP   5
  71#define PHY_STAT_PREM_SUPPRESS  6
  72#define PHY_STAT_UNIDIR_CAP     7
  73#define PHY_STAT_EXT_STAT_CAP   8
  74#define PHY_STAT_100B_T2_HD     9
  75#define PHY_STAT_100B_T2_FD     10
  76#define PHY_STAT_10MBPS_HD      11
  77#define PHY_STAT_10MBPS_FD      12
  78#define PHY_STAT_100BX_HD       13
  79#define PHY_STAT_100BX_FD       14
  80#define PHY_STAT_T4             15
  81
  82/* EXT Status Register bitfeild offsets*/
  83#define PHY_EXT_STAT_1000BT_HD  12
  84#define PHY_EXT_STAT_1000BT_FD  13
  85#define PHY_EXT_STAT_1000BX_HD  14
  86#define PHY_EXT_STAT_1000BX_FD  15
  87
  88/* Prepare a bit mask */
  89#define M(X) (uint16_t) (1 << X)
  90
  91#define PHY_CTRL_RST            0x8000 /* PHY reset command */
  92#define PHY_CTRL_ANEG_RST       0x0200 /* Autonegotiation reset command */
  93
  94/* PHY Advertisement control and remote capability registers (same bitfields) */
  95#define PHY_ADVERTISE_10HALF    0x0020  /* Try for 10mbps half-duplex  */
  96#define PHY_ADVERTISE_10FULL    0x0040  /* Try for 10mbps full-duplex  */
  97#define PHY_ADVERTISE_100HALF   0x0080  /* Try for 100mbps half-duplex */
  98#define PHY_ADVERTISE_100FULL   0x0100  /* Try for 100mbps full-duplex */
  99
 100#define TYPE_ETH_PHY "eth-phy"
 101
 102#define ETHPHY(obj) OBJECT_CHECK(EthPhy, (obj), TYPE_ETH_PHY)
 103#define ETHPHY_CLASS(klass) OBJECT_CLASS_CHECK(EthPhyClass, (klass),\
 104                                               TYPE_ETH_PHY)
 105#define ETHPHY_GET_CLASS(obj) \
 106     OBJECT_GET_CLASS(EthPhyClass, (obj), TYPE_ETH_PHY)
 107
 108static const uint16_t default_readonly_mask[32] = {
 109    [PHY_CTRL] = PHY_CTRL_RST | PHY_CTRL_ANEG_RST,
 110    [PHY_ID1] = 0xffff,
 111    [PHY_ID2] = 0xffff,
 112    [PHY_LP_ABILITY] = 0xffff,
 113    [PHY_SPEC_STATUS] = 0xffff,
 114};
 115
 116typedef struct PhyPartInfo {
 117    const char *partname;
 118
 119    uint16_t phy_id1;
 120    uint16_t phy_id2;
 121
 122    bool autoneg;
 123    bool gmii;
 124} PhyPartInfo;
 125
 126#define PHYINFO(_part_name, _id1, _id2, _autoneg, _gmii) \
 127    .partname = (_part_name),\
 128    .phy_id1 = (_id1),\
 129    .phy_id2 = (_id2),\
 130    .autoneg = (_autoneg),\
 131    .gmii = (_gmii),\
 132
 133static const PhyPartInfo devices[] = {
 134    { PHYINFO("88e1116r", 0x0141, 0x0e50, 1, 1) },
 135    { PHYINFO("88e1116",  0x0141, 0x0e50, 1, 1) },
 136    { PHYINFO("dp83867",  0x2000, 0xa231, 1, 1) },
 137    { PHYINFO("88e1118r", 0x0141, 0x0e10, 1, 1) },
 138    { PHYINFO("88e1510",  0x0141, 0x0dd0, 1, 1) },
 139};
 140
 141
 142typedef struct EthPhy {
 143    MDIOSlave parent_object;
 144
 145    /* Only the basic registers, rest of them in Vendor */
 146    uint16_t regs[NUM_PHY_REGS];
 147    const uint16_t *regs_readonly_mask; /* 0=writable, 1=read-only */
 148
 149    bool link;
 150
 151    PhyPartInfo *part;
 152} EthPhy;
 153
 154typedef struct EthPhyClass {
 155    MDIOSlaveClass parent_class;
 156
 157    PhyPartInfo *part;
 158} EthPhyClass;
 159
 160#endif
 161