LXR qemu/include/hw/pci/pci

   1#ifndef QEMU_PCI_BUS_H
   2#define QEMU_PCI_BUS_H
   3
   4/*
   5 * PCI Bus and Bridge datastructures.
   6 *
   7 * Do not access the following members directly;
   8 * use accessor functions in pci.h, pci_bridge.h
   9 */
  10
  11typedef struct PCIBusClass {
  12    /*< private >*/
  13    BusClass parent_class;
  14    /*< public >*/
  15
  16    bool (*is_root)(PCIBus *bus);
  17    int (*bus_num)(PCIBus *bus);
  18    uint16_t (*numa_node)(PCIBus *bus);
  19} PCIBusClass;
  20
  21struct PCIBus {
  22    BusState qbus;
  23    PCIIOMMUFunc iommu_fn;
  24    void *iommu_opaque;
  25    uint8_t devfn_min;
  26    pci_set_irq_fn set_irq;
  27    pci_map_irq_fn map_irq;
  28    pci_route_irq_fn route_intx_to_irq;
  29    void *irq_opaque;
  30    PCIDevice *devices[PCI_SLOT_MAX * PCI_FUNC_MAX];
  31    PCIDevice *parent_dev;
  32    MemoryRegion *address_space_mem;
  33    MemoryRegion *address_space_io;
  34
  35    QLIST_HEAD(, PCIBus) child; /* this will be replaced by qdev later */
  36    QLIST_ENTRY(PCIBus) sibling;/* this will be replaced by qdev later */
  37
  38    /* The bus IRQ state is the logical OR of the connected devices.
  39       Keep a count of the number of devices with raised IRQs.  */
  40    int nirq;
  41    int *irq_count;
  42};
  43
  44typedef struct PCIBridgeWindows PCIBridgeWindows;
  45
  46/*
  47 * Aliases for each of the address space windows that the bridge
  48 * can forward. Mapped into the bridge's parent's address space,
  49 * as subregions.
  50 */
  51struct PCIBridgeWindows {
  52    MemoryRegion alias_pref_mem;
  53    MemoryRegion alias_mem;
  54    MemoryRegion alias_io;
  55    /*
  56     * When bridge control VGA forwarding is enabled, bridges will
  57     * provide positive decode on the PCI VGA defined I/O port and
  58     * MMIO ranges.  When enabled forwarding is only qualified on the
  59     * I/O and memory enable bits in the bridge command register.
  60     */
  61    MemoryRegion alias_vga[QEMU_PCI_VGA_NUM_REGIONS];
  62};
  63
  64#define TYPE_PCI_BRIDGE "base-pci-bridge"
  65#define PCI_BRIDGE(obj) OBJECT_CHECK(PCIBridge, (obj), TYPE_PCI_BRIDGE)
  66
  67struct PCIBridge {
  68    /*< private >*/
  69    PCIDevice parent_obj;
  70    /*< public >*/
  71
  72    /* private member */
  73    PCIBus sec_bus;
  74    /*
  75     * Memory regions for the bridge's address spaces.  These regions are not
  76     * directly added to system_memory/system_io or its descendants.
  77     * Bridge's secondary bus points to these, so that devices
  78     * under the bridge see these regions as its address spaces.
  79     * The regions are as large as the entire address space -
  80     * they don't take into account any windows.
  81     */
  82    MemoryRegion address_space_mem;
  83    MemoryRegion address_space_io;
  84
  85    PCIBridgeWindows *windows;
  86
  87    pci_map_irq_fn map_irq;
  88    const char *bus_name;
  89};
  90
  91#endif /* QEMU_PCI_BUS_H */
  92