LXR qemu/include/hw/ssi/xilinx

   1/*
   2 * Header file for the Xilinx Zynq SPI controller
   3 *
   4 * Copyright (C) 2015 Xilinx Inc
   5 *
   6 * Permission is hereby granted, free of charge, to any person obtaining a copy
   7 * of this software and associated documentation files (the "Software"), to deal
   8 * in the Software without restriction, including without limitation the rights
   9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10 * copies of the Software, and to permit persons to whom the Software is
  11 * furnished to do so, subject to the following conditions:
  12 *
  13 * The above copyright notice and this permission notice shall be included in
  14 * all copies or substantial portions of the Software.
  15 *
  16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22 * THE SOFTWARE.
  23 */
  24
  25#ifndef XLNX_SPIPS_H
  26#define XLNX_SPIPS_H
  27
  28#include "hw/ssi/ssi.h"
  29#include "qemu/fifo.h"
  30#include "hw/stream.h"
  31
  32typedef struct XilinxSPIPS XilinxSPIPS;
  33
  34#define XLNX_SPIPS_R_MAX        0x200
  35
  36/* Bite off 4k chunks at a time */
  37#define LQSPI_CACHE_SIZE 1024
  38
  39typedef enum {
  40    READ = 0x3,         READ_4 = 0x13,
  41    FAST_READ = 0xb,    FAST_READ_4 = 0x0c,
  42    DOR = 0x3b,         DOR_4 = 0x3c,
  43    QOR = 0x6b,         QOR_4 = 0x6c,
  44    DIOR = 0xbb,        DIOR_4 = 0xbc,
  45    QIOR = 0xeb,        QIOR_4 = 0xec,
  46
  47    PP = 0x2,           PP_4 = 0x12,
  48    DPP = 0xa2,
  49    QPP = 0x32,         QPP_4 = 0x34,
  50} FlashCMD;
  51
  52struct XilinxSPIPS {
  53    SysBusDevice parent_obj;
  54
  55    MemoryRegion iomem;
  56    MemoryRegion mmlqspi;
  57
  58    qemu_irq irq;
  59    int irqline;
  60
  61    uint8_t num_cs;
  62    uint8_t num_busses;
  63
  64    uint8_t snoop_state;
  65    uint8_t link_state;
  66    uint8_t link_state_next;
  67    uint8_t link_state_next_when;
  68    qemu_irq *cs_lines;
  69    bool *cs_lines_state;
  70    SSIBus **spi;
  71
  72    Fifo rx_fifo;
  73    Fifo tx_fifo;
  74    /* GQSPI has seperate tx/rx fifos */
  75    Fifo rx_fifo_g;
  76    Fifo tx_fifo_g;
  77    /*
  78     * at the end of each generic command, misaligned extra bytes are discard
  79     * or padded to tx and rx respectively to round it out (and avoid need for
  80     * individual byte access. Since we use byte fifos, keep track of the
  81     * alignment WRT to word access.
  82     */
  83    uint8_t rx_fifo_g_align;
  84    uint8_t tx_fifo_g_align;
  85
  86    Fifo fifo_g;
  87
  88    uint8_t num_txrx_bytes;
  89    uint32_t rx_discard;
  90
  91    uint32_t regs[XLNX_SPIPS_R_MAX];
  92
  93    bool man_start_com;
  94    bool man_start_com_g;
  95};
  96
  97typedef struct {
  98    XilinxSPIPS parent_obj;
  99
 100    uint32_t lqspi_size;
 101    uint32_t lqspi_src;
 102    uint32_t lqspi_dst;
 103
 104    MemoryRegion *hack_dma;
 105    AddressSpace *hack_as;
 106
 107    uint8_t spi_mode;
 108    uint8_t lqspi_buf[LQSPI_CACHE_SIZE];
 109    hwaddr lqspi_cached_addr;
 110} XilinxQSPIPS;
 111
 112typedef struct {
 113    XilinxQSPIPS parent_obj;
 114
 115    StreamSlave *dma;
 116    uint8_t dma_buf[4];
 117} ZynqMPQSPIPS;
 118
 119typedef struct XilinxSPIPSClass {
 120    SysBusDeviceClass parent_class;
 121
 122    const MemoryRegionOps *reg_ops;
 123
 124    uint32_t rx_fifo_size;
 125    uint32_t tx_fifo_size;
 126} XilinxSPIPSClass;
 127
 128#define TYPE_XILINX_SPIPS "xlnx.ps7-spi"
 129#define TYPE_XILINX_QSPIPS "xlnx.ps7-qspi"
 130#define TYPE_ZYNQMP_QSPIPS "xlnx.usmp-gqspi"
 131
 132#define XILINX_SPIPS(obj) \
 133     OBJECT_CHECK(XilinxSPIPS, (obj), TYPE_XILINX_SPIPS)
 134#define XILINX_SPIPS_CLASS(klass) \
 135     OBJECT_CLASS_CHECK(XilinxSPIPSClass, (klass), TYPE_XILINX_SPIPS)
 136#define XILINX_SPIPS_GET_CLASS(obj) \
 137     OBJECT_GET_CLASS(XilinxSPIPSClass, (obj), TYPE_XILINX_SPIPS)
 138
 139#define XILINX_QSPIPS(obj) \
 140     OBJECT_CHECK(XilinxQSPIPS, (obj), TYPE_XILINX_QSPIPS)
 141
 142#define ZYNQMP_QSPIPS(obj) \
 143     OBJECT_CHECK(ZynqMPQSPIPS, (obj), TYPE_ZYNQMP_QSPIPS)
 144
 145#endif /* XLNX_SPIPS_H */
 146