1/* 2 * This program is free software; you can redistribute it and/or modify 3 * it under the terms of the GNU General Public License, version 2, as 4 * published by the Free Software Foundation. 5 * 6 * This program is distributed in the hope that it will be useful, 7 * but WITHOUT ANY WARRANTY; without even the implied warranty of 8 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 9 * GNU General Public License for more details. 10 * 11 * You should have received a copy of the GNU General Public License 12 * along with this program; if not, write to the Free Software 13 * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. 14 * 15 * Copyright IBM Corp. 2007 16 * 17 * Authors: Hollis Blanchard <hollisb@us.ibm.com> 18 */ 19 20#ifndef __LINUX_KVM_POWERPC_H 21#define __LINUX_KVM_POWERPC_H 22 23#include <linux/types.h> 24 25/* Select powerpc specific features in <linux/kvm.h> */ 26#define __KVM_HAVE_SPAPR_TCE 27#define __KVM_HAVE_PPC_SMT 28#define __KVM_HAVE_IRQCHIP 29#define __KVM_HAVE_IRQ_LINE 30#define __KVM_HAVE_GUEST_DEBUG 31 32struct kvm_regs { 33 __u64 pc; 34 __u64 cr; 35 __u64 ctr; 36 __u64 lr; 37 __u64 xer; 38 __u64 msr; 39 __u64 srr0; 40 __u64 srr1; 41 __u64 pid; 42 43 __u64 sprg0; 44 __u64 sprg1; 45 __u64 sprg2; 46 __u64 sprg3; 47 __u64 sprg4; 48 __u64 sprg5; 49 __u64 sprg6; 50 __u64 sprg7; 51 52 __u64 gpr[32]; 53}; 54 55#define KVM_SREGS_E_IMPL_NONE 0 56#define KVM_SREGS_E_IMPL_FSL 1 57 58#define KVM_SREGS_E_FSL_PIDn (1 << 0) /* PID1/PID2 */ 59 60/* 61 * Feature bits indicate which sections of the sregs struct are valid, 62 * both in KVM_GET_SREGS and KVM_SET_SREGS. On KVM_SET_SREGS, registers 63 * corresponding to unset feature bits will not be modified. This allows 64 * restoring a checkpoint made without that feature, while keeping the 65 * default values of the new registers. 66 * 67 * KVM_SREGS_E_BASE contains: 68 * CSRR0/1 (refers to SRR2/3 on 40x) 69 * ESR 70 * DEAR 71 * MCSR 72 * TSR 73 * TCR 74 * DEC 75 * TB 76 * VRSAVE (USPRG0) 77 */ 78#define KVM_SREGS_E_BASE (1 << 0) 79 80/* 81 * KVM_SREGS_E_ARCH206 contains: 82 * 83 * PIR 84 * MCSRR0/1 85 * DECAR 86 * IVPR 87 */ 88#define KVM_SREGS_E_ARCH206 (1 << 1) 89 90/* 91 * Contains EPCR, plus the upper half of 64-bit registers 92 * that are 32-bit on 32-bit implementations. 93 */ 94#define KVM_SREGS_E_64 (1 << 2) 95 96#define KVM_SREGS_E_SPRG8 (1 << 3) 97#define KVM_SREGS_E_MCIVPR (1 << 4) 98 99/* 100 * IVORs are used -- contains IVOR0-15, plus additional IVORs 101 * in combination with an appropriate feature bit. 102 */ 103#define KVM_SREGS_E_IVOR (1 << 5) 104 105/* 106 * Contains MAS0-4, MAS6-7, TLBnCFG, MMUCFG. 107 * Also TLBnPS if MMUCFG[MAVN] = 1. 108 */ 109#define KVM_SREGS_E_ARCH206_MMU (1 << 6) 110 111/* DBSR, DBCR, IAC, DAC, DVC */ 112#define KVM_SREGS_E_DEBUG (1 << 7) 113 114/* Enhanced debug -- DSRR0/1, SPRG9 */ 115#define KVM_SREGS_E_ED (1 << 8) 116 117/* Embedded Floating Point (SPE) -- IVOR32-34 if KVM_SREGS_E_IVOR */ 118#define KVM_SREGS_E_SPE (1 << 9) 119 120/* 121 * DEPRECATED! USE ONE_REG FOR THIS ONE! 122 * External Proxy (EXP) -- EPR 123 */ 124#define KVM_SREGS_EXP (1 << 10) 125 126/* External PID (E.PD) -- EPSC/EPLC */ 127#define KVM_SREGS_E_PD (1 << 11) 128 129/* Processor Control (E.PC) -- IVOR36-37 if KVM_SREGS_E_IVOR */ 130#define KVM_SREGS_E_PC (1 << 12) 131 132/* Page table (E.PT) -- EPTCFG */ 133#define KVM_SREGS_E_PT (1 << 13) 134 135/* Embedded Performance Monitor (E.PM) -- IVOR35 if KVM_SREGS_E_IVOR */ 136#define KVM_SREGS_E_PM (1 << 14) 137 138/* 139 * Special updates: 140 * 141 * Some registers may change even while a vcpu is not running. 142 * To avoid losing these changes, by default these registers are 143 * not updated by KVM_SET_SREGS. To force an update, set the bit 144 * in u.e.update_special corresponding to the register to be updated. 145 * 146 * The update_special field is zero on return from KVM_GET_SREGS. 147 * 148 * When restoring a checkpoint, the caller can set update_special 149 * to 0xffffffff to ensure that everything is restored, even new features 150 * that the caller doesn't know about. 151 */ 152#define KVM_SREGS_E_UPDATE_MCSR (1 << 0) 153#define KVM_SREGS_E_UPDATE_TSR (1 << 1) 154#define KVM_SREGS_E_UPDATE_DEC (1 << 2) 155#define KVM_SREGS_E_UPDATE_DBSR (1 << 3) 156 157/* 158 * In KVM_SET_SREGS, reserved/pad fields must be left untouched from a 159 * previous KVM_GET_REGS. 160 * 161 * Unless otherwise indicated, setting any register with KVM_SET_SREGS 162 * directly sets its value. It does not trigger any special semantics such 163 * as write-one-to-clear. Calling KVM_SET_SREGS on an unmodified struct 164 * just received from KVM_GET_SREGS is always a no-op. 165 */ 166struct kvm_sregs { 167 __u32 pvr; 168 union { 169 struct { 170 __u64 sdr1; 171 struct { 172 struct { 173 __u64 slbe; 174 __u64 slbv; 175 } slb[64]; 176 } ppc64; 177 struct { 178 __u32 sr[16]; 179 __u64 ibat[8]; 180 __u64 dbat[8]; 181 } ppc32; 182 } s; 183 struct { 184 union { 185 struct { /* KVM_SREGS_E_IMPL_FSL */ 186 __u32 features; /* KVM_SREGS_E_FSL_ */ 187 __u32 svr; 188 __u64 mcar; 189 __u32 hid0; 190 191 /* KVM_SREGS_E_FSL_PIDn */ 192 __u32 pid1, pid2; 193 } fsl; 194 __u8 pad[256]; 195 } impl; 196 197 __u32 features; /* KVM_SREGS_E_ */ 198 __u32 impl_id; /* KVM_SREGS_E_IMPL_ */ 199 __u32 update_special; /* KVM_SREGS_E_UPDATE_ */ 200 __u32 pir; /* read-only */ 201 __u64 sprg8; 202 __u64 sprg9; /* E.ED */ 203 __u64 csrr0; 204 __u64 dsrr0; /* E.ED */ 205 __u64 mcsrr0; 206 __u32 csrr1; 207 __u32 dsrr1; /* E.ED */ 208 __u32 mcsrr1; 209 __u32 esr; 210 __u64 dear; 211 __u64 ivpr; 212 __u64 mcivpr; 213 __u64 mcsr; /* KVM_SREGS_E_UPDATE_MCSR */ 214 215 __u32 tsr; /* KVM_SREGS_E_UPDATE_TSR */ 216 __u32 tcr; 217 __u32 decar; 218 __u32 dec; /* KVM_SREGS_E_UPDATE_DEC */ 219 220 /* 221 * Userspace can read TB directly, but the 222 * value reported here is consistent with "dec". 223 * 224 * Read-only. 225 */ 226 __u64 tb; 227 228 __u32 dbsr; /* KVM_SREGS_E_UPDATE_DBSR */ 229 __u32 dbcr[3]; 230 /* 231 * iac/dac registers are 64bit wide, while this API 232 * interface provides only lower 32 bits on 64 bit 233 * processors. ONE_REG interface is added for 64bit 234 * iac/dac registers. 235 */ 236 __u32 iac[4]; 237 __u32 dac[2]; 238 __u32 dvc[2]; 239 __u8 num_iac; /* read-only */ 240 __u8 num_dac; /* read-only */ 241 __u8 num_dvc; /* read-only */ 242 __u8 pad; 243 244 __u32 epr; /* EXP */ 245 __u32 vrsave; /* a.k.a. USPRG0 */ 246 __u32 epcr; /* KVM_SREGS_E_64 */ 247 248 __u32 mas0; 249 __u32 mas1; 250 __u64 mas2; 251 __u64 mas7_3; 252 __u32 mas4; 253 __u32 mas6; 254 255 __u32 ivor_low[16]; /* IVOR0-15 */ 256 __u32 ivor_high[18]; /* IVOR32+, plus room to expand */ 257 258 __u32 mmucfg; /* read-only */ 259 __u32 eptcfg; /* E.PT, read-only */ 260 __u32 tlbcfg[4];/* read-only */ 261 __u32 tlbps[4]; /* read-only */ 262 263 __u32 eplc, epsc; /* E.PD */ 264 } e; 265 __u8 pad[1020]; 266 } u; 267}; 268 269struct kvm_fpu { 270 __u64 fpr[32]; 271}; 272 273/* 274 * Defines for h/w breakpoint, watchpoint (read, write or both) and 275 * software breakpoint. 276 * These are used as "type" in KVM_SET_GUEST_DEBUG ioctl and "status" 277 * for KVM_DEBUG_EXIT. 278 */ 279#define KVMPPC_DEBUG_NONE 0x0 280#define KVMPPC_DEBUG_BREAKPOINT (1UL << 1) 281#define KVMPPC_DEBUG_WATCH_WRITE (1UL << 2) 282#define KVMPPC_DEBUG_WATCH_READ (1UL << 3) 283struct kvm_debug_exit_arch { 284 __u64 address; 285 /* 286 * exiting to userspace because of h/w breakpoint, watchpoint 287 * (read, write or both) and software breakpoint. 288 */ 289 __u32 status; 290 __u32 reserved; 291}; 292 293/* for KVM_SET_GUEST_DEBUG */ 294struct kvm_guest_debug_arch { 295 struct { 296 /* H/W breakpoint/watchpoint address */ 297 __u64 addr; 298 /* 299 * Type denotes h/w breakpoint, read watchpoint, write 300 * watchpoint or watchpoint (both read and write). 301 */ 302 __u32 type; 303 __u32 reserved; 304 } bp[16]; 305}; 306 307/* Debug related defines */ 308/* 309 * kvm_guest_debug->control is a 32 bit field. The lower 16 bits are generic 310 * and upper 16 bits are architecture specific. Architecture specific defines 311 * that ioctl is for setting hardware breakpoint or software breakpoint. 312 */ 313#define KVM_GUESTDBG_USE_SW_BP 0x00010000 314#define KVM_GUESTDBG_USE_HW_BP 0x00020000 315 316/* definition of registers in kvm_run */ 317struct kvm_sync_regs { 318}; 319 320#define KVM_INTERRUPT_SET -1U 321#define KVM_INTERRUPT_UNSET -2U 322#define KVM_INTERRUPT_SET_LEVEL -3U 323 324#define KVM_CPU_440 1 325#define KVM_CPU_E500V2 2 326#define KVM_CPU_3S_32 3 327#define KVM_CPU_3S_64 4 328#define KVM_CPU_E500MC 5 329 330/* for KVM_CAP_SPAPR_TCE */ 331struct kvm_create_spapr_tce { 332 __u64 liobn; 333 __u32 window_size; 334}; 335 336/* for KVM_CAP_SPAPR_TCE_64 */ 337struct kvm_create_spapr_tce_64 { 338 __u64 liobn; 339 __u32 page_shift; 340 __u32 flags; 341 __u64 offset; /* in pages */ 342 __u64 size; /* in pages */ 343}; 344 345/* for KVM_ALLOCATE_RMA */ 346struct kvm_allocate_rma { 347 __u64 rma_size; 348}; 349 350/* for KVM_CAP_PPC_RTAS */ 351struct kvm_rtas_token_args { 352 char name[120]; 353 __u64 token; /* Use a token of 0 to undefine a mapping */ 354}; 355 356struct kvm_book3e_206_tlb_entry { 357 __u32 mas8; 358 __u32 mas1; 359 __u64 mas2; 360 __u64 mas7_3; 361}; 362 363struct kvm_book3e_206_tlb_params { 364 /* 365 * For mmu types KVM_MMU_FSL_BOOKE_NOHV and KVM_MMU_FSL_BOOKE_HV: 366 * 367 * - The number of ways of TLB0 must be a power of two between 2 and 368 * 16. 369 * - TLB1 must be fully associative. 370 * - The size of TLB0 must be a multiple of the number of ways, and 371 * the number of sets must be a power of two. 372 * - The size of TLB1 may not exceed 64 entries. 373 * - TLB0 supports 4 KiB pages. 374 * - The page sizes supported by TLB1 are as indicated by 375 * TLB1CFG (if MMUCFG[MAVN] = 0) or TLB1PS (if MMUCFG[MAVN] = 1) 376 * as returned by KVM_GET_SREGS. 377 * - TLB2 and TLB3 are reserved, and their entries in tlb_sizes[] 378 * and tlb_ways[] must be zero. 379 * 380 * tlb_ways[n] = tlb_sizes[n] means the array is fully associative. 381 * 382 * KVM will adjust TLBnCFG based on the sizes configured here, 383 * though arrays greater than 2048 entries will have TLBnCFG[NENTRY] 384 * set to zero. 385 */ 386 __u32 tlb_sizes[4]; 387 __u32 tlb_ways[4]; 388 __u32 reserved[8]; 389}; 390 391/* For KVM_PPC_GET_HTAB_FD */ 392struct kvm_get_htab_fd { 393 __u64 flags; 394 __u64 start_index; 395 __u64 reserved[2]; 396}; 397 398/* Values for kvm_get_htab_fd.flags */ 399#define KVM_GET_HTAB_BOLTED_ONLY ((__u64)0x1) 400#define KVM_GET_HTAB_WRITE ((__u64)0x2) 401 402/* 403 * Data read on the file descriptor is formatted as a series of 404 * records, each consisting of a header followed by a series of 405 * `n_valid' HPTEs (16 bytes each), which are all valid. Following 406 * those valid HPTEs there are `n_invalid' invalid HPTEs, which 407 * are not represented explicitly in the stream. The same format 408 * is used for writing. 409 */ 410struct kvm_get_htab_header { 411 __u32 index; 412 __u16 n_valid; 413 __u16 n_invalid; 414}; 415 416/* Per-vcpu XICS interrupt controller state */ 417#define KVM_REG_PPC_ICP_STATE (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8c) 418 419#define KVM_REG_PPC_ICP_CPPR_SHIFT 56 /* current proc priority */ 420#define KVM_REG_PPC_ICP_CPPR_MASK 0xff 421#define KVM_REG_PPC_ICP_XISR_SHIFT 32 /* interrupt status field */ 422#define KVM_REG_PPC_ICP_XISR_MASK 0xffffff 423#define KVM_REG_PPC_ICP_MFRR_SHIFT 24 /* pending IPI priority */ 424#define KVM_REG_PPC_ICP_MFRR_MASK 0xff 425#define KVM_REG_PPC_ICP_PPRI_SHIFT 16 /* pending irq priority */ 426#define KVM_REG_PPC_ICP_PPRI_MASK 0xff 427 428/* Device control API: PPC-specific devices */ 429#define KVM_DEV_MPIC_GRP_MISC 1 430#define KVM_DEV_MPIC_BASE_ADDR 0 /* 64-bit */ 431 432#define KVM_DEV_MPIC_GRP_REGISTER 2 /* 32-bit */ 433#define KVM_DEV_MPIC_GRP_IRQ_ACTIVE 3 /* 32-bit */ 434 435/* One-Reg API: PPC-specific registers */ 436#define KVM_REG_PPC_HIOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x1) 437#define KVM_REG_PPC_IAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x2) 438#define KVM_REG_PPC_IAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3) 439#define KVM_REG_PPC_IAC3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x4) 440#define KVM_REG_PPC_IAC4 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x5) 441#define KVM_REG_PPC_DAC1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x6) 442#define KVM_REG_PPC_DAC2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x7) 443#define KVM_REG_PPC_DABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8) 444#define KVM_REG_PPC_DSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9) 445#define KVM_REG_PPC_PURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa) 446#define KVM_REG_PPC_SPURR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb) 447#define KVM_REG_PPC_DAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc) 448#define KVM_REG_PPC_DSISR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xd) 449#define KVM_REG_PPC_AMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xe) 450#define KVM_REG_PPC_UAMOR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xf) 451 452#define KVM_REG_PPC_MMCR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x10) 453#define KVM_REG_PPC_MMCR1 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x11) 454#define KVM_REG_PPC_MMCRA (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x12) 455#define KVM_REG_PPC_MMCR2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x13) 456#define KVM_REG_PPC_MMCRS (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x14) 457#define KVM_REG_PPC_SIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x15) 458#define KVM_REG_PPC_SDAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x16) 459#define KVM_REG_PPC_SIER (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x17) 460 461#define KVM_REG_PPC_PMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x18) 462#define KVM_REG_PPC_PMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x19) 463#define KVM_REG_PPC_PMC3 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1a) 464#define KVM_REG_PPC_PMC4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1b) 465#define KVM_REG_PPC_PMC5 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1c) 466#define KVM_REG_PPC_PMC6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1d) 467#define KVM_REG_PPC_PMC7 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1e) 468#define KVM_REG_PPC_PMC8 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x1f) 469 470/* 32 floating-point registers */ 471#define KVM_REG_PPC_FPR0 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x20) 472#define KVM_REG_PPC_FPR(n) (KVM_REG_PPC_FPR0 + (n)) 473#define KVM_REG_PPC_FPR31 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x3f) 474 475/* 32 VMX/Altivec vector registers */ 476#define KVM_REG_PPC_VR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x40) 477#define KVM_REG_PPC_VR(n) (KVM_REG_PPC_VR0 + (n)) 478#define KVM_REG_PPC_VR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x5f) 479 480/* 32 double-width FP registers for VSX */ 481/* High-order halves overlap with FP regs */ 482#define KVM_REG_PPC_VSR0 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x60) 483#define KVM_REG_PPC_VSR(n) (KVM_REG_PPC_VSR0 + (n)) 484#define KVM_REG_PPC_VSR31 (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x7f) 485 486/* FP and vector status/control registers */ 487#define KVM_REG_PPC_FPSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x80) 488/* 489 * VSCR register is documented as a 32-bit register in the ISA, but it can 490 * only be accesses via a vector register. Expose VSCR as a 32-bit register 491 * even though the kernel represents it as a 128-bit vector. 492 */ 493#define KVM_REG_PPC_VSCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x81) 494 495/* Virtual processor areas */ 496/* For SLB & DTL, address in high (first) half, length in low half */ 497#define KVM_REG_PPC_VPA_ADDR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x82) 498#define KVM_REG_PPC_VPA_SLB (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x83) 499#define KVM_REG_PPC_VPA_DTL (KVM_REG_PPC | KVM_REG_SIZE_U128 | 0x84) 500 501#define KVM_REG_PPC_EPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x85) 502#define KVM_REG_PPC_EPR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x86) 503 504/* Timer Status Register OR/CLEAR interface */ 505#define KVM_REG_PPC_OR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x87) 506#define KVM_REG_PPC_CLEAR_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x88) 507#define KVM_REG_PPC_TCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x89) 508#define KVM_REG_PPC_TSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8a) 509 510/* Debugging: Special instruction for software breakpoint */ 511#define KVM_REG_PPC_DEBUG_INST (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8b) 512 513/* MMU registers */ 514#define KVM_REG_PPC_MAS0 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8c) 515#define KVM_REG_PPC_MAS1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x8d) 516#define KVM_REG_PPC_MAS2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8e) 517#define KVM_REG_PPC_MAS7_3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x8f) 518#define KVM_REG_PPC_MAS4 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x90) 519#define KVM_REG_PPC_MAS6 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x91) 520#define KVM_REG_PPC_MMUCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x92) 521/* 522 * TLBnCFG fields TLBnCFG_N_ENTRY and TLBnCFG_ASSOC can be changed only using 523 * KVM_CAP_SW_TLB ioctl 524 */ 525#define KVM_REG_PPC_TLB0CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x93) 526#define KVM_REG_PPC_TLB1CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x94) 527#define KVM_REG_PPC_TLB2CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x95) 528#define KVM_REG_PPC_TLB3CFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x96) 529#define KVM_REG_PPC_TLB0PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x97) 530#define KVM_REG_PPC_TLB1PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x98) 531#define KVM_REG_PPC_TLB2PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x99) 532#define KVM_REG_PPC_TLB3PS (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9a) 533#define KVM_REG_PPC_EPTCFG (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9b) 534 535/* Timebase offset */ 536#define KVM_REG_PPC_TB_OFFSET (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9c) 537 538/* POWER8 registers */ 539#define KVM_REG_PPC_SPMC1 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9d) 540#define KVM_REG_PPC_SPMC2 (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0x9e) 541#define KVM_REG_PPC_IAMR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0x9f) 542#define KVM_REG_PPC_TFHAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa0) 543#define KVM_REG_PPC_TFIAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa1) 544#define KVM_REG_PPC_TEXASR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa2) 545#define KVM_REG_PPC_FSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa3) 546#define KVM_REG_PPC_PSPB (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xa4) 547#define KVM_REG_PPC_EBBHR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa5) 548#define KVM_REG_PPC_EBBRR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa6) 549#define KVM_REG_PPC_BESCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa7) 550#define KVM_REG_PPC_TAR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa8) 551#define KVM_REG_PPC_DPDES (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xa9) 552#define KVM_REG_PPC_DAWR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaa) 553#define KVM_REG_PPC_DAWRX (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xab) 554#define KVM_REG_PPC_CIABR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xac) 555#define KVM_REG_PPC_IC (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xad) 556#define KVM_REG_PPC_VTB (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xae) 557#define KVM_REG_PPC_CSIGR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xaf) 558#define KVM_REG_PPC_TACR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb0) 559#define KVM_REG_PPC_TCSCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb1) 560#define KVM_REG_PPC_PID (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb2) 561#define KVM_REG_PPC_ACOP (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb3) 562 563#define KVM_REG_PPC_VRSAVE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb4) 564#define KVM_REG_PPC_LPCR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb5) 565#define KVM_REG_PPC_LPCR_64 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb5) 566#define KVM_REG_PPC_PPR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb6) 567 568/* Architecture compatibility level */ 569#define KVM_REG_PPC_ARCH_COMPAT (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb7) 570 571#define KVM_REG_PPC_DABRX (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xb8) 572#define KVM_REG_PPC_WORT (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xb9) 573#define KVM_REG_PPC_SPRG9 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xba) 574#define KVM_REG_PPC_DBSR (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbb) 575 576/* Transactional Memory checkpointed state: 577 * This is all GPRs, all VSX regs and a subset of SPRs 578 */ 579#define KVM_REG_PPC_TM (KVM_REG_PPC | 0x80000000) 580/* TM GPRs */ 581#define KVM_REG_PPC_TM_GPR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0) 582#define KVM_REG_PPC_TM_GPR(n) (KVM_REG_PPC_TM_GPR0 + (n)) 583#define KVM_REG_PPC_TM_GPR31 (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x1f) 584/* TM VSX */ 585#define KVM_REG_PPC_TM_VSR0 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x20) 586#define KVM_REG_PPC_TM_VSR(n) (KVM_REG_PPC_TM_VSR0 + (n)) 587#define KVM_REG_PPC_TM_VSR63 (KVM_REG_PPC_TM | KVM_REG_SIZE_U128 | 0x5f) 588/* TM SPRS */ 589#define KVM_REG_PPC_TM_CR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x60) 590#define KVM_REG_PPC_TM_LR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x61) 591#define KVM_REG_PPC_TM_CTR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x62) 592#define KVM_REG_PPC_TM_FPSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x63) 593#define KVM_REG_PPC_TM_AMR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x64) 594#define KVM_REG_PPC_TM_PPR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x65) 595#define KVM_REG_PPC_TM_VRSAVE (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x66) 596#define KVM_REG_PPC_TM_VSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U32 | 0x67) 597#define KVM_REG_PPC_TM_DSCR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x68) 598#define KVM_REG_PPC_TM_TAR (KVM_REG_PPC_TM | KVM_REG_SIZE_U64 | 0x69) 599 600/* PPC64 eXternal Interrupt Controller Specification */ 601#define KVM_DEV_XICS_GRP_SOURCES 1 /* 64-bit source attributes */ 602 603/* Layout of 64-bit source attribute values */ 604#define KVM_XICS_DESTINATION_SHIFT 0 605#define KVM_XICS_DESTINATION_MASK 0xffffffffULL 606#define KVM_XICS_PRIORITY_SHIFT 32 607#define KVM_XICS_PRIORITY_MASK 0xff 608#define KVM_XICS_LEVEL_SENSITIVE (1ULL << 40) 609#define KVM_XICS_MASKED (1ULL << 41) 610#define KVM_XICS_PENDING (1ULL << 42) 611 612#endif /* __LINUX_KVM_POWERPC_H */ 613