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20#ifndef QEMU_ARM_CPU_QOM_H
21#define QEMU_ARM_CPU_QOM_H
22
23#include "qom/cpu.h"
24
25struct arm_boot_info;
26
27#define TYPE_ARM_CPU "arm-cpu"
28
29#define ARM_CPU_CLASS(klass) \
30 OBJECT_CLASS_CHECK(ARMCPUClass, (klass), TYPE_ARM_CPU)
31#define ARM_CPU(obj) \
32 OBJECT_CHECK(ARMCPU, (obj), TYPE_ARM_CPU)
33#define ARM_CPU_GET_CLASS(obj) \
34 OBJECT_GET_CLASS(ARMCPUClass, (obj), TYPE_ARM_CPU)
35#define ARM_CPU_PARENT_CLASS \
36 object_class_get_parent(object_class_by_name(TYPE_ARM_CPU))
37
38
39
40
41
42
43
44
45typedef struct ARMCPUClass {
46
47 CPUClass parent_class;
48
49
50 DeviceRealize parent_realize;
51 void (*parent_reset)(CPUState *cpu);
52} ARMCPUClass;
53
54
55
56
57
58
59
60typedef struct ARMCPU {
61
62 CPUState parent_obj;
63
64
65 CPUARMState env;
66
67 bool is_in_wfi;
68
69
70 GHashTable *cp_regs;
71
72
73
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75
76
77
78 uint64_t *cpreg_indexes;
79
80 uint64_t *cpreg_values;
81
82 int32_t cpreg_array_len;
83
84
85
86
87 uint64_t *cpreg_vmstate_indexes;
88 uint64_t *cpreg_vmstate_values;
89 int32_t cpreg_vmstate_array_len;
90
91
92 QEMUTimer *gt_timer[NUM_GTIMERS];
93
94 qemu_irq gt_timer_outputs[NUM_GTIMERS];
95
96
97 qemu_irq wfi;
98
99
100 MemoryRegion *secure_memory;
101
102
103 const char *dtb_compatible;
104
105
106
107
108
109 uint32_t psci_version;
110
111
112 bool start_powered_off;
113
114 bool powered_off;
115
116 bool has_el3;
117
118
119 bool has_mpu;
120
121 uint32_t pmsav7_dregion;
122
123
124
125
126 uint32_t psci_conduit;
127
128
129
130
131 uint32_t kvm_target;
132
133
134 uint32_t kvm_init_features[7];
135
136
137 bool mp_is_up;
138
139
140
141
142
143
144
145
146
147
148
149 uint32_t midr;
150 uint32_t revidr;
151 uint32_t reset_fpsid;
152 uint32_t mvfr0;
153 uint32_t mvfr1;
154 uint32_t mvfr2;
155 uint32_t ctr;
156 uint32_t reset_sctlr;
157 uint32_t id_pfr0;
158 uint32_t id_pfr1;
159 uint32_t id_dfr0;
160 uint32_t pmceid0;
161 uint32_t pmceid1;
162 uint32_t id_afr0;
163 uint32_t id_mmfr0;
164 uint32_t id_mmfr1;
165 uint32_t id_mmfr2;
166 uint32_t id_mmfr3;
167 uint32_t id_mmfr4;
168 uint32_t id_isar0;
169 uint32_t id_isar1;
170 uint32_t id_isar2;
171 uint32_t id_isar3;
172 uint32_t id_isar4;
173 uint32_t id_isar5;
174 uint64_t id_aa64pfr0;
175 uint64_t id_aa64pfr1;
176 uint64_t id_aa64dfr0;
177 uint64_t id_aa64dfr1;
178 uint64_t id_aa64afr0;
179 uint64_t id_aa64afr1;
180 uint64_t id_aa64isar0;
181 uint64_t id_aa64isar1;
182 uint64_t id_aa64mmfr0;
183 uint64_t id_aa64mmfr1;
184 uint32_t dbgdidr;
185 uint32_t clidr;
186 uint64_t mp_affinity;
187
188
189
190 uint32_t ccsidr[16];
191 uint64_t reset_cbar;
192 uint32_t reset_auxcr;
193 bool reset_hivecs;
194
195 uint32_t dcz_blocksize;
196 uint64_t rvbar;
197 int pe;
198
199 MemoryRegion *mr_secure;
200 AddressSpace *as_secure;
201 AddressSpace *as_ns;
202} ARMCPU;
203
204#define TYPE_AARCH64_CPU "aarch64-cpu"
205#define AARCH64_CPU_CLASS(klass) \
206 OBJECT_CLASS_CHECK(AArch64CPUClass, (klass), TYPE_AARCH64_CPU)
207#define AARCH64_CPU_GET_CLASS(obj) \
208 OBJECT_GET_CLASS(AArch64CPUClass, (obj), TYPE_AArch64_CPU)
209
210typedef struct AArch64CPUClass {
211
212 ARMCPUClass parent_class;
213
214} AArch64CPUClass;
215
216void register_cp_regs_for_features(ARMCPU *cpu);
217void init_cpreg_list(ARMCPU *cpu);
218
219void arm_cpu_do_interrupt(CPUState *cpu);
220void arm_v7m_cpu_do_interrupt(CPUState *cpu);
221bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req);
222
223void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
224 int flags);
225
226hwaddr arm_cpu_get_phys_page_attrs_debug(CPUState *cpu, vaddr addr,
227 MemTxAttrs *attrs);
228
229int arm_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
230int arm_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
231
232int arm_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
233 int cpuid, void *opaque);
234int arm_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cs,
235 int cpuid, void *opaque);
236
237
238void arm_gt_ptimer_cb(void *opaque);
239void arm_gt_vtimer_cb(void *opaque);
240void arm_gt_htimer_cb(void *opaque);
241void arm_gt_stimer_cb(void *opaque);
242
243#define ARM_AFF0_SHIFT 0
244#define ARM_AFF0_MASK (0xFFULL << ARM_AFF0_SHIFT)
245#define ARM_AFF1_SHIFT 8
246#define ARM_AFF1_MASK (0xFFULL << ARM_AFF1_SHIFT)
247#define ARM_AFF2_SHIFT 16
248#define ARM_AFF2_MASK (0xFFULL << ARM_AFF2_SHIFT)
249#define ARM_AFF3_SHIFT 32
250#define ARM_AFF3_MASK (0xFFULL << ARM_AFF3_SHIFT)
251
252#define ARM32_AFFINITY_MASK (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK)
253#define ARM64_AFFINITY_MASK \
254 (ARM_AFF0_MASK|ARM_AFF1_MASK|ARM_AFF2_MASK|ARM_AFF3_MASK)
255
256#ifdef TARGET_AARCH64
257int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
258int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
259#endif
260
261#endif
262