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21#include "qemu/osdep.h"
22#include "qapi/error.h"
23#include "cpu.h"
24#include "internals.h"
25#include "qemu-common.h"
26#include "hw/qdev-properties.h"
27#if !defined(CONFIG_USER_ONLY)
28#include "hw/loader.h"
29#endif
30#include "hw/arm/arm.h"
31#include "sysemu/sysemu.h"
32#include "sysemu/kvm.h"
33#include "kvm_arm.h"
34
35#include "hw/fdt_generic_util.h"
36
37static void arm_cpu_set_pc(CPUState *cs, vaddr value)
38{
39 ARMCPU *cpu = ARM_CPU(cs);
40
41 cpu->env.regs[15] = value;
42}
43
44static vaddr arm_cpu_get_pc(CPUState *cs)
45{
46 ARMCPU *cpu = ARM_CPU(cs);
47
48 return cpu->env.regs[15];
49}
50
51enum {
52 ARM_DEBUG_CURRENT_EL,
53 ARM_DEBUG_PHYS
54};
55
56static const char *arm_debug_ctx[] = {
57 [ARM_DEBUG_CURRENT_EL] = "current-el",
58 [ARM_DEBUG_PHYS] = "phys",
59 NULL
60};
61
62static bool arm_cpu_has_work(CPUState *cs)
63{
64 ARMCPU *cpu = ARM_CPU(cs);
65
66 return !cpu->powered_off
67 && cs->interrupt_request &
68 (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
69 | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
70 | CPU_INTERRUPT_EXITTB);
71}
72
73static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
74{
75
76 ARMCPRegInfo *ri = value;
77 ARMCPU *cpu = opaque;
78
79 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
80 return;
81 }
82
83 if (ri->resetfn) {
84 ri->resetfn(&cpu->env, ri);
85 return;
86 }
87
88
89
90
91
92
93 if (!ri->fieldoffset) {
94 return;
95 }
96
97 if (cpreg_field_is_64bit(ri)) {
98 CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
99 } else {
100 CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
101 }
102}
103
104static void cp_reg_check_reset(gpointer key, gpointer value, gpointer opaque)
105{
106
107
108
109
110
111 ARMCPRegInfo *ri = value;
112 ARMCPU *cpu = opaque;
113 uint64_t oldvalue, newvalue;
114
115 if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) {
116 return;
117 }
118
119 oldvalue = read_raw_cp_reg(&cpu->env, ri);
120 cp_reg_reset(key, value, opaque);
121 newvalue = read_raw_cp_reg(&cpu->env, ri);
122 assert(oldvalue == newvalue);
123}
124
125
126static void arm_cpu_reset(CPUState *s)
127{
128 ARMCPU *cpu = ARM_CPU(s);
129 ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
130 CPUARMState *env = &cpu->env;
131#ifndef CONFIG_USER_ONLY
132 CPUClass *cc = CPU_GET_CLASS(s);
133 vaddr old_pc = cc->get_pc(s);
134#endif
135
136 acc->parent_reset(s);
137
138 memset(env, 0, offsetof(CPUARMState, features));
139 g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
140 g_hash_table_foreach(cpu->cp_regs, cp_reg_check_reset, cpu);
141
142 env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
143 env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
144 env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
145 env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
146
147 cpu->powered_off = cpu->start_powered_off || s->arch_halt_pin;
148 s->halted = cpu->start_powered_off || s->halt_pin || s->arch_halt_pin;
149
150
151 env->cp15.sctlr_ns &= ~SCTLR_V;
152 env->cp15.sctlr_s &= ~SCTLR_V;
153 env->cp15.sctlr_ns |= env->vinithi ? SCTLR_V : 0;
154 env->cp15.sctlr_s |= env->vinithi ? SCTLR_V : 0;
155
156 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
157 env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
158 }
159
160 if (arm_feature(env, ARM_FEATURE_AARCH64)) {
161
162 env->aarch64 = 1;
163#if defined(CONFIG_USER_ONLY)
164 env->pstate = PSTATE_MODE_EL0t;
165
166 env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
167
168 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
169#else
170
171 if (arm_feature(env, ARM_FEATURE_EL3)) {
172 env->pstate = PSTATE_MODE_EL3h;
173 } else if (arm_feature(env, ARM_FEATURE_EL2)) {
174 env->pstate = PSTATE_MODE_EL2h;
175 } else {
176 env->pstate = PSTATE_MODE_EL1h;
177 }
178 env->pc = cpu->rvbar;
179#endif
180 } else {
181#if defined(CONFIG_USER_ONLY)
182
183 env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
184#endif
185 }
186
187#if defined(CONFIG_USER_ONLY)
188 env->uncached_cpsr = ARM_CPU_MODE_USR;
189
190 env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
191 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
192 env->cp15.c15_cpar = 3;
193 } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
194 env->cp15.c15_cpar = 1;
195 }
196#else
197
198 env->uncached_cpsr = ARM_CPU_MODE_SVC;
199 if (arm_feature(env, ARM_FEATURE_EL2)) {
200 env->uncached_cpsr = ARM_CPU_MODE_HYP;
201 }
202 if (arm_feature(env, ARM_FEATURE_EL3)) {
203 env->uncached_cpsr = ARM_CPU_MODE_MON;
204 }
205 env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
206
207
208
209 if (IS_M(env)) {
210 uint32_t initial_msp;
211 uint32_t initial_pc;
212 uint8_t *rom;
213
214 env->daif &= ~PSTATE_I;
215 rom = rom_ptr(0);
216 if (rom) {
217
218
219
220 initial_msp = ldl_p(rom);
221 initial_pc = ldl_p(rom + 4);
222 } else {
223
224
225
226
227
228 initial_msp = ldl_phys(s->as, 0);
229 initial_pc = ldl_phys(s->as, 4);
230 }
231
232 env->regs[13] = initial_msp & 0xFFFFFFFC;
233 env->regs[15] = initial_pc & ~1;
234 env->thumb = initial_pc & 1;
235 }
236
237
238
239
240
241 if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
242 env->regs[15] = 0xFFFF0000;
243 }
244
245 env->vfp.xregs[ARM_VFP_FPEXC] = 0;
246#endif
247 set_flush_to_zero(1, &env->vfp.standard_fp_status);
248 set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
249 set_default_nan_mode(1, &env->vfp.standard_fp_status);
250 set_float_detect_tininess(float_tininess_before_rounding,
251 &env->vfp.fp_status);
252 set_float_detect_tininess(float_tininess_before_rounding,
253 &env->vfp.standard_fp_status);
254 tlb_flush(s, 1);
255
256#ifndef CONFIG_USER_ONLY
257 if (kvm_enabled()) {
258 kvm_arm_reset_vcpu(cpu);
259 }
260
261 if (!runstate_is_running()) {
262 cc->set_pc(s, old_pc);
263 }
264#endif
265
266 cpu->is_in_wfi = true;
267 qemu_set_irq(cpu->wfi, 1);
268
269 hw_breakpoint_update_all(cpu);
270 hw_watchpoint_update_all(cpu);
271
272#ifndef CONFIG_USER_ONLY
273 if (cpu->env.memattr_ns) {
274 env->memattr[MEM_ATTR_NS].attrs = *cpu->env.memattr_ns;
275 }
276
277 if (cpu->env.memattr_s) {
278 env->memattr[MEM_ATTR_SEC].attrs = *cpu->env.memattr_s;
279 } else if (arm_feature(env, ARM_FEATURE_EL3)) {
280
281 env->memattr[MEM_ATTR_SEC].attrs.secure = true;
282 }
283#endif
284}
285
286bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
287{
288 CPUClass *cc = CPU_GET_CLASS(cs);
289 ARMCPU *cpu = ARM_CPU(cs);
290 CPUARMState *env = cs->env_ptr;
291 uint32_t cur_el = arm_current_el(env);
292 bool secure = arm_is_secure(env);
293 uint32_t target_el;
294 uint32_t excp_idx;
295 bool ret = false;
296
297
298
299
300 if (cpu->is_in_wfi) {
301 cpu->is_in_wfi = false;
302 qemu_set_irq(cpu->wfi, 0);
303 }
304
305 if (interrupt_request & CPU_INTERRUPT_FIQ) {
306 excp_idx = EXCP_FIQ;
307 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
308 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
309 cs->exception_index = excp_idx;
310 env->exception.target_el = target_el;
311 cc->do_interrupt(cs);
312 ret = true;
313 }
314 }
315 if (interrupt_request & CPU_INTERRUPT_HARD) {
316 excp_idx = EXCP_IRQ;
317 target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
318 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
319 cs->exception_index = excp_idx;
320 env->exception.target_el = target_el;
321 cc->do_interrupt(cs);
322 ret = true;
323 }
324 }
325 if (interrupt_request & CPU_INTERRUPT_VIRQ) {
326 excp_idx = EXCP_VIRQ;
327 target_el = 1;
328 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
329 cs->exception_index = excp_idx;
330 env->exception.target_el = target_el;
331 cc->do_interrupt(cs);
332 ret = true;
333 }
334 }
335 if (interrupt_request & CPU_INTERRUPT_VFIQ) {
336 excp_idx = EXCP_VFIQ;
337 target_el = 1;
338 if (arm_excp_unmasked(cs, excp_idx, target_el)) {
339 cs->exception_index = excp_idx;
340 env->exception.target_el = target_el;
341 cc->do_interrupt(cs);
342 ret = true;
343 }
344 }
345
346 return ret;
347}
348
349#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
350static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
351{
352 CPUClass *cc = CPU_GET_CLASS(cs);
353 ARMCPU *cpu = ARM_CPU(cs);
354 CPUARMState *env = &cpu->env;
355 bool ret = false;
356
357
358 if (interrupt_request & CPU_INTERRUPT_FIQ
359 && !(env->daif & PSTATE_F)) {
360 cs->exception_index = EXCP_FIQ;
361 cc->do_interrupt(cs);
362 ret = true;
363 }
364
365
366
367
368
369
370
371
372
373
374 if (interrupt_request & CPU_INTERRUPT_HARD
375 && !(env->daif & PSTATE_I)
376 && (env->regs[15] < 0xfffffff0)) {
377 cs->exception_index = EXCP_IRQ;
378 cc->do_interrupt(cs);
379 ret = true;
380 }
381 return ret;
382}
383#endif
384
385#ifndef CONFIG_USER_ONLY
386static void arm_cpu_set_irq(void *opaque, int irq, int level)
387{
388 ARMCPU *cpu = opaque;
389 CPUARMState *env = &cpu->env;
390 CPUState *cs = CPU(cpu);
391 static const int mask[] = {
392 [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
393 [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
394 [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
395 [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
396 };
397
398 switch (irq) {
399 case ARM_CPU_VIRQ:
400 case ARM_CPU_VFIQ:
401 assert(arm_feature(env, ARM_FEATURE_EL2));
402
403 case ARM_CPU_IRQ:
404 case ARM_CPU_FIQ:
405 if (level) {
406 cpu_interrupt(cs, mask[irq]);
407 } else {
408 cpu_reset_interrupt(cs, mask[irq]);
409 }
410 break;
411 default:
412 g_assert_not_reached();
413 }
414}
415
416static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
417{
418#ifdef CONFIG_KVM
419 ARMCPU *cpu = opaque;
420 CPUState *cs = CPU(cpu);
421 int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
422
423 switch (irq) {
424 case ARM_CPU_IRQ:
425 kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
426 break;
427 case ARM_CPU_FIQ:
428 kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
429 break;
430 default:
431 g_assert_not_reached();
432 }
433 kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
434 kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
435#endif
436}
437
438static bool arm_cpu_virtio_is_big_endian(CPUState *cs)
439{
440 ARMCPU *cpu = ARM_CPU(cs);
441 CPUARMState *env = &cpu->env;
442
443 cpu_synchronize_state(cs);
444 return arm_cpu_data_is_big_endian(env);
445}
446
447#endif
448
449static inline void set_feature(CPUARMState *env, int feature)
450{
451 env->features |= 1ULL << feature;
452}
453
454#ifndef CONFIG_USER_ONLY
455static void arm_cpu_set_ncpuhalt(void *opaque, int irq, int level)
456{
457 CPUState *cs = opaque;
458
459
460
461
462
463
464
465#if 0
466 if (!cs->reset_pin) {
467 return;
468 }
469#endif
470 cpu_halt_reset_common(cs, &cs->arch_halt_pin, level, false);
471}
472
473static void arm_cpu_set_vinithi(void *opaque, int irq, int level)
474{
475 CPUState *cs = opaque;
476 ARMCPU *cpu = ARM_CPU(cs);
477
478 cpu->env.vinithi = level;
479}
480#endif
481
482static inline void unset_feature(CPUARMState *env, int feature)
483{
484 env->features &= ~(1ULL << feature);
485}
486
487#ifndef CONFIG_USER_ONLY
488static void arm_cpu_set_mr_secure(Object *obj, Visitor *v, const char *name,
489 void *opaque, Error **errp)
490{
491 ARMCPU *ac = ARM_CPU(obj);
492 Error *local_err = NULL;
493 char *path = NULL;
494
495 qemu_log("set mr_secure\n");
496 visit_type_str(v, name, &path, &local_err);
497
498 if (!local_err && strcmp(path, "") != 0) {
499 ac->mr_secure = MEMORY_REGION(object_resolve_link(obj, name, path,
500 &local_err));
501 }
502
503 if (local_err) {
504 error_propagate(errp, local_err);
505 return;
506 }
507
508 object_ref(OBJECT(ac->mr_secure));
509 ac->as_secure = address_space_init_shareable(ac->mr_secure, NULL);
510}
511#endif
512
513static int
514print_insn_thumb1(bfd_vma pc, disassemble_info *info)
515{
516 return print_insn_arm(pc | 1, info);
517}
518
519static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
520{
521 ARMCPU *ac = ARM_CPU(cpu);
522 CPUARMState *env = &ac->env;
523
524 if (is_a64(env)) {
525
526
527
528
529#if defined(CONFIG_ARM_A64_DIS)
530 info->print_insn = print_insn_arm_a64;
531#endif
532 } else if (env->thumb) {
533 info->print_insn = print_insn_thumb1;
534 } else {
535 info->print_insn = print_insn_arm;
536 }
537 if (bswap_code(arm_sctlr_b(env))) {
538#ifdef TARGET_WORDS_BIGENDIAN
539 info->endian = BFD_ENDIAN_LITTLE;
540#else
541 info->endian = BFD_ENDIAN_BIG;
542#endif
543 }
544}
545
546#define ARM_CPUS_PER_CLUSTER 4
547
548static void arm_cpu_initfn(Object *obj)
549{
550 CPUState *cs = CPU(obj);
551 ARMCPU *cpu = ARM_CPU(obj);
552 static bool inited;
553 uint32_t Aff1, Aff0;
554
555 cs->env_ptr = &cpu->env;
556 cpu_exec_init(cs, &error_abort);
557 cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
558 g_free, g_free);
559
560
561
562
563
564
565 Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
566 Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
567 cpu->mp_affinity = (Aff1 << ARM_AFF1_SHIFT) | Aff0;
568
569#ifndef CONFIG_USER_ONLY
570
571 if (kvm_enabled()) {
572
573
574
575 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
576 } else {
577 qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
578 }
579
580 qdev_init_gpio_in_named(DEVICE(cpu), arm_cpu_set_ncpuhalt, "ncpuhalt", 1);
581 qdev_init_gpio_in_named(DEVICE(cpu), arm_cpu_set_vinithi, "vinithi", 1);
582
583 cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
584 arm_gt_ptimer_cb, cpu);
585 cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
586 arm_gt_vtimer_cb, cpu);
587 cpu->gt_timer[GTIMER_HYP] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
588 arm_gt_htimer_cb, cpu);
589 cpu->gt_timer[GTIMER_SEC] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
590 arm_gt_stimer_cb, cpu);
591 qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
592 ARRAY_SIZE(cpu->gt_timer_outputs));
593
594 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->wfi, "wfi", 1);
595#endif
596
597
598
599
600
601 cpu->dtb_compatible = "qemu,unknown";
602 cpu->psci_version = 1;
603 cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
604
605 if (tcg_enabled()) {
606 cpu->psci_version = 2;
607 if (!inited) {
608 inited = true;
609 arm_translate_init();
610 }
611 }
612
613#ifndef CONFIG_USER_ONLY
614 object_property_add(obj, "mr-secure", "link<" TYPE_MEMORY_REGION ">",
615 NULL,
616 arm_cpu_set_mr_secure,
617 NULL,
618 NULL, &error_abort);
619
620 object_property_add_link(obj, "memattr_ns", TYPE_MEMORY_TRANSACTION_ATTR,
621 (Object **)&cpu->env.memattr_ns,
622 qdev_prop_allow_set_link_before_realize,
623 OBJ_PROP_LINK_UNREF_ON_RELEASE,
624 &error_abort);
625
626 object_property_add_link(obj, "memattr_s", TYPE_MEMORY_TRANSACTION_ATTR,
627 (Object **)&cpu->env.memattr_s,
628 qdev_prop_allow_set_link_before_realize,
629 OBJ_PROP_LINK_UNREF_ON_RELEASE,
630 &error_abort);
631#endif
632}
633
634static Property arm_cpu_reset_cbar_property =
635 DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
636
637static Property arm_cpu_reset_hivecs_property =
638 DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
639
640static Property arm_cpu_has_el3_property =
641 DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
642
643static Property arm_cpu_has_mpu_property =
644 DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
645
646static Property arm_cpu_pmsav7_dregion_property =
647 DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
648
649static void arm_cpu_get_rvbar(Object *obj, Visitor *v,
650 const char *name, void *opaque,
651 Error **errp)
652{
653 ARMCPU *cpu = ARM_CPU(obj);
654 Error *local_err = NULL;
655
656 visit_type_uint64(v, name, &cpu->rvbar, &local_err);
657 if (local_err) {
658 error_propagate(errp, local_err);
659 }
660}
661
662static void arm_cpu_set_rvbar(Object *obj, Visitor *v,
663 const char *name, void *opaque,
664 Error **errp)
665{
666 ARMCPU *cpu = ARM_CPU(obj);
667 Error *local_err = NULL;
668
669 visit_type_uint64(v, name, &cpu->rvbar, &local_err);
670 if (local_err) {
671 error_propagate(errp, local_err);
672 }
673}
674
675static void arm_cpu_post_init(Object *obj)
676{
677 ARMCPU *cpu = ARM_CPU(obj);
678
679 if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
680 arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
681 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
682 &error_abort);
683 }
684
685 if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
686 qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
687 &error_abort);
688 }
689
690 if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
691 object_property_add(obj, "rvbar", "uint64",
692 arm_cpu_get_rvbar,
693 arm_cpu_set_rvbar,
694 NULL, NULL, &error_abort);
695 }
696
697 if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
698
699
700
701 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
702 &error_abort);
703
704#ifndef CONFIG_USER_ONLY
705 object_property_add_link(obj, "secure-memory",
706 TYPE_MEMORY_REGION,
707 (Object **)&cpu->secure_memory,
708 qdev_prop_allow_set_link_before_realize,
709 OBJ_PROP_LINK_UNREF_ON_RELEASE,
710 &error_abort);
711#endif
712 }
713
714 if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
715 qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
716 &error_abort);
717 if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
718 qdev_property_add_static(DEVICE(obj),
719 &arm_cpu_pmsav7_dregion_property,
720 &error_abort);
721 }
722 }
723
724}
725
726static void arm_cpu_finalizefn(Object *obj)
727{
728 ARMCPU *cpu = ARM_CPU(obj);
729 g_hash_table_destroy(cpu->cp_regs);
730}
731
732static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
733{
734 CPUState *cs = CPU(dev);
735 ARMCPU *cpu = ARM_CPU(dev);
736 ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
737 CPUARMState *env = &cpu->env;
738
739
740 cpu->as_ns = cs->as;
741 if (!cpu->as_secure) {
742 cpu->as_secure = cs->as;
743 }
744
745
746 if (arm_feature(env, ARM_FEATURE_V8)) {
747 set_feature(env, ARM_FEATURE_V7);
748 set_feature(env, ARM_FEATURE_ARM_DIV);
749 set_feature(env, ARM_FEATURE_LPAE);
750 }
751 if (arm_feature(env, ARM_FEATURE_V7)) {
752 set_feature(env, ARM_FEATURE_VAPA);
753 set_feature(env, ARM_FEATURE_THUMB2);
754 set_feature(env, ARM_FEATURE_MPIDR);
755 if (!arm_feature(env, ARM_FEATURE_M)) {
756 set_feature(env, ARM_FEATURE_V6K);
757 } else {
758 set_feature(env, ARM_FEATURE_V6);
759 }
760 }
761 if (arm_feature(env, ARM_FEATURE_V6K)) {
762 set_feature(env, ARM_FEATURE_V6);
763 set_feature(env, ARM_FEATURE_MVFR);
764 }
765 if (arm_feature(env, ARM_FEATURE_V6)) {
766 set_feature(env, ARM_FEATURE_V5);
767 if (!arm_feature(env, ARM_FEATURE_M)) {
768 set_feature(env, ARM_FEATURE_AUXCR);
769 }
770 }
771 if (arm_feature(env, ARM_FEATURE_V5)) {
772 set_feature(env, ARM_FEATURE_V4T);
773 }
774 if (arm_feature(env, ARM_FEATURE_M)) {
775 set_feature(env, ARM_FEATURE_THUMB_DIV);
776 }
777 if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
778 set_feature(env, ARM_FEATURE_THUMB_DIV);
779 }
780 if (arm_feature(env, ARM_FEATURE_VFP4)) {
781 set_feature(env, ARM_FEATURE_VFP3);
782 set_feature(env, ARM_FEATURE_VFP_FP16);
783 }
784 if (arm_feature(env, ARM_FEATURE_VFP3)) {
785 set_feature(env, ARM_FEATURE_VFP);
786 }
787 if (arm_feature(env, ARM_FEATURE_LPAE)) {
788 set_feature(env, ARM_FEATURE_V7MP);
789 set_feature(env, ARM_FEATURE_PXN);
790 }
791 if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
792 set_feature(env, ARM_FEATURE_CBAR);
793 }
794 if (arm_feature(env, ARM_FEATURE_THUMB2) &&
795 !arm_feature(env, ARM_FEATURE_M)) {
796 set_feature(env, ARM_FEATURE_THUMB_DSP);
797 }
798
799 if (cpu->reset_hivecs) {
800 cpu->reset_sctlr |= (1 << 13);
801 }
802
803 if (!cpu->has_el3) {
804
805
806
807 unset_feature(env, ARM_FEATURE_EL3);
808
809
810
811
812 cpu->id_pfr1 &= ~0xf0;
813 cpu->id_aa64pfr0 &= ~0xf000;
814 }
815
816 if (!arm_feature(env, ARM_FEATURE_EL2)) {
817
818
819
820
821 cpu->id_aa64pfr0 &= ~0xf00;
822 cpu->id_pfr1 &= ~0xf000;
823 }
824
825 if (!cpu->has_mpu) {
826 unset_feature(env, ARM_FEATURE_MPU);
827 }
828
829 if (arm_feature(env, ARM_FEATURE_MPU) &&
830 arm_feature(env, ARM_FEATURE_V7)) {
831 uint32_t nr = cpu->pmsav7_dregion;
832
833 if (nr > 0xff) {
834 error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32, nr);
835 return;
836 }
837
838 if (nr) {
839 env->pmsav7.drbar = g_new0(uint32_t, nr);
840 env->pmsav7.drsr = g_new0(uint32_t, nr);
841 env->pmsav7.dracr = g_new0(uint32_t, nr);
842 }
843 }
844
845 register_cp_regs_for_features(cpu);
846 arm_cpu_register_gdb_regs_for_features(cpu);
847
848 init_cpreg_list(cpu);
849
850#ifndef CONFIG_USER_ONLY
851
852
853
854
855#define CPU_NO_EL3_SEC_ENABLE 1
856 if (cpu->has_el3 || CPU_NO_EL3_SEC_ENABLE) {
857 cs->num_ases = 2;
858 } else {
859 cs->num_ases = 1;
860 }
861
862 if (cpu->has_el3 || CPU_NO_EL3_SEC_ENABLE) {
863 AddressSpace *as;
864
865 if (!cpu->secure_memory) {
866 cpu->secure_memory = cs->memory;
867 }
868 as = address_space_init_shareable(cpu->secure_memory,
869 "cpu-secure-memory");
870 cpu_address_space_init(cs, as, ARMASIdx_S);
871 }
872 cpu_address_space_init(cs,
873 address_space_init_shareable(cs->memory,
874 "cpu-memory"),
875 ARMASIdx_NS);
876#endif
877
878 qemu_init_vcpu(cs);
879 cpu_reset(cs);
880
881 acc->parent_realize(dev, errp);
882}
883
884static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
885{
886 ObjectClass *oc;
887 char *typename;
888 char **cpuname;
889
890 if (!cpu_model) {
891 return NULL;
892 }
893
894 cpuname = g_strsplit(cpu_model, ",", 1);
895 typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
896 oc = object_class_by_name(typename);
897 g_strfreev(cpuname);
898 g_free(typename);
899 if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
900 object_class_is_abstract(oc)) {
901 return NULL;
902 }
903 return oc;
904}
905
906
907#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
908
909static void arm926_initfn(Object *obj)
910{
911 ARMCPU *cpu = ARM_CPU(obj);
912
913 cpu->dtb_compatible = "arm,arm926";
914 set_feature(&cpu->env, ARM_FEATURE_V5);
915 set_feature(&cpu->env, ARM_FEATURE_VFP);
916 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
917 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
918 cpu->midr = 0x41069265;
919 cpu->reset_fpsid = 0x41011090;
920 cpu->ctr = 0x1dd20d2;
921 cpu->reset_sctlr = 0x00090078;
922}
923
924static void arm946_initfn(Object *obj)
925{
926 ARMCPU *cpu = ARM_CPU(obj);
927
928 cpu->dtb_compatible = "arm,arm946";
929 set_feature(&cpu->env, ARM_FEATURE_V5);
930 set_feature(&cpu->env, ARM_FEATURE_MPU);
931 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
932 cpu->midr = 0x41059461;
933 cpu->ctr = 0x0f004006;
934 cpu->reset_sctlr = 0x00000078;
935}
936
937static void arm1026_initfn(Object *obj)
938{
939 ARMCPU *cpu = ARM_CPU(obj);
940
941 cpu->dtb_compatible = "arm,arm1026";
942 set_feature(&cpu->env, ARM_FEATURE_V5);
943 set_feature(&cpu->env, ARM_FEATURE_VFP);
944 set_feature(&cpu->env, ARM_FEATURE_AUXCR);
945 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
946 set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
947 cpu->midr = 0x4106a262;
948 cpu->reset_fpsid = 0x410110a0;
949 cpu->ctr = 0x1dd20d2;
950 cpu->reset_sctlr = 0x00090078;
951 cpu->reset_auxcr = 1;
952 {
953
954 ARMCPRegInfo ifar = {
955 .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
956 .access = PL1_RW,
957 .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
958 .resetvalue = 0
959 };
960 define_one_arm_cp_reg(cpu, &ifar);
961 }
962}
963
964static void arm1136_r2_initfn(Object *obj)
965{
966 ARMCPU *cpu = ARM_CPU(obj);
967
968
969
970
971
972
973
974
975 cpu->dtb_compatible = "arm,arm1136";
976 set_feature(&cpu->env, ARM_FEATURE_V6);
977 set_feature(&cpu->env, ARM_FEATURE_VFP);
978 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
979 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
980 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
981 cpu->midr = 0x4107b362;
982 cpu->reset_fpsid = 0x410120b4;
983 cpu->mvfr0 = 0x11111111;
984 cpu->mvfr1 = 0x00000000;
985 cpu->ctr = 0x1dd20d2;
986 cpu->reset_sctlr = 0x00050078;
987 cpu->id_pfr0 = 0x111;
988 cpu->id_pfr1 = 0x1;
989 cpu->id_dfr0 = 0x2;
990 cpu->id_afr0 = 0x3;
991 cpu->id_mmfr0 = 0x01130003;
992 cpu->id_mmfr1 = 0x10030302;
993 cpu->id_mmfr2 = 0x01222110;
994 cpu->id_isar0 = 0x00140011;
995 cpu->id_isar1 = 0x12002111;
996 cpu->id_isar2 = 0x11231111;
997 cpu->id_isar3 = 0x01102131;
998 cpu->id_isar4 = 0x141;
999 cpu->reset_auxcr = 7;
1000}
1001
1002static void arm1136_initfn(Object *obj)
1003{
1004 ARMCPU *cpu = ARM_CPU(obj);
1005
1006 cpu->dtb_compatible = "arm,arm1136";
1007 set_feature(&cpu->env, ARM_FEATURE_V6K);
1008 set_feature(&cpu->env, ARM_FEATURE_V6);
1009 set_feature(&cpu->env, ARM_FEATURE_VFP);
1010 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1011 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1012 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1013 cpu->midr = 0x4117b363;
1014 cpu->reset_fpsid = 0x410120b4;
1015 cpu->mvfr0 = 0x11111111;
1016 cpu->mvfr1 = 0x00000000;
1017 cpu->ctr = 0x1dd20d2;
1018 cpu->reset_sctlr = 0x00050078;
1019 cpu->id_pfr0 = 0x111;
1020 cpu->id_pfr1 = 0x1;
1021 cpu->id_dfr0 = 0x2;
1022 cpu->id_afr0 = 0x3;
1023 cpu->id_mmfr0 = 0x01130003;
1024 cpu->id_mmfr1 = 0x10030302;
1025 cpu->id_mmfr2 = 0x01222110;
1026 cpu->id_isar0 = 0x00140011;
1027 cpu->id_isar1 = 0x12002111;
1028 cpu->id_isar2 = 0x11231111;
1029 cpu->id_isar3 = 0x01102131;
1030 cpu->id_isar4 = 0x141;
1031 cpu->reset_auxcr = 7;
1032}
1033
1034static void arm1176_initfn(Object *obj)
1035{
1036 ARMCPU *cpu = ARM_CPU(obj);
1037
1038 cpu->dtb_compatible = "arm,arm1176";
1039 set_feature(&cpu->env, ARM_FEATURE_V6K);
1040 set_feature(&cpu->env, ARM_FEATURE_VFP);
1041 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1042 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1043 set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
1044 set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
1045 set_feature(&cpu->env, ARM_FEATURE_EL3);
1046 cpu->midr = 0x410fb767;
1047 cpu->reset_fpsid = 0x410120b5;
1048 cpu->mvfr0 = 0x11111111;
1049 cpu->mvfr1 = 0x00000000;
1050 cpu->ctr = 0x1dd20d2;
1051 cpu->reset_sctlr = 0x00050078;
1052 cpu->id_pfr0 = 0x111;
1053 cpu->id_pfr1 = 0x11;
1054 cpu->id_dfr0 = 0x33;
1055 cpu->id_afr0 = 0;
1056 cpu->id_mmfr0 = 0x01130003;
1057 cpu->id_mmfr1 = 0x10030302;
1058 cpu->id_mmfr2 = 0x01222100;
1059 cpu->id_isar0 = 0x0140011;
1060 cpu->id_isar1 = 0x12002111;
1061 cpu->id_isar2 = 0x11231121;
1062 cpu->id_isar3 = 0x01102131;
1063 cpu->id_isar4 = 0x01141;
1064 cpu->reset_auxcr = 7;
1065}
1066
1067static void arm11mpcore_initfn(Object *obj)
1068{
1069 ARMCPU *cpu = ARM_CPU(obj);
1070
1071 cpu->dtb_compatible = "arm,arm11mpcore";
1072 set_feature(&cpu->env, ARM_FEATURE_V6K);
1073 set_feature(&cpu->env, ARM_FEATURE_VFP);
1074 set_feature(&cpu->env, ARM_FEATURE_VAPA);
1075 set_feature(&cpu->env, ARM_FEATURE_MPIDR);
1076 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1077 cpu->midr = 0x410fb022;
1078 cpu->reset_fpsid = 0x410120b4;
1079 cpu->mvfr0 = 0x11111111;
1080 cpu->mvfr1 = 0x00000000;
1081 cpu->ctr = 0x1d192992;
1082 cpu->id_pfr0 = 0x111;
1083 cpu->id_pfr1 = 0x1;
1084 cpu->id_dfr0 = 0;
1085 cpu->id_afr0 = 0x2;
1086 cpu->id_mmfr0 = 0x01100103;
1087 cpu->id_mmfr1 = 0x10020302;
1088 cpu->id_mmfr2 = 0x01222000;
1089 cpu->id_isar0 = 0x00100011;
1090 cpu->id_isar1 = 0x12002111;
1091 cpu->id_isar2 = 0x11221011;
1092 cpu->id_isar3 = 0x01102131;
1093 cpu->id_isar4 = 0x141;
1094 cpu->reset_auxcr = 1;
1095}
1096
1097static void cortex_m3_initfn(Object *obj)
1098{
1099 ARMCPU *cpu = ARM_CPU(obj);
1100 set_feature(&cpu->env, ARM_FEATURE_V7);
1101 set_feature(&cpu->env, ARM_FEATURE_M);
1102 cpu->midr = 0x410fc231;
1103}
1104
1105static void cortex_m4_initfn(Object *obj)
1106{
1107 ARMCPU *cpu = ARM_CPU(obj);
1108
1109 set_feature(&cpu->env, ARM_FEATURE_V7);
1110 set_feature(&cpu->env, ARM_FEATURE_M);
1111 set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
1112 cpu->midr = 0x410fc240;
1113}
1114static void arm_v7m_class_init(ObjectClass *oc, void *data)
1115{
1116 CPUClass *cc = CPU_CLASS(oc);
1117
1118#ifndef CONFIG_USER_ONLY
1119 cc->do_interrupt = arm_v7m_cpu_do_interrupt;
1120#endif
1121
1122 cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
1123}
1124
1125static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
1126
1127 { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1128 .access = PL1_RW, .type = ARM_CP_CONST },
1129 { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1130 .access = PL1_RW, .type = ARM_CP_CONST },
1131 { .name = "DCIALLU", .cp = 15, .crn = 15, .crm = 5, .opc1 = 0, .opc2 = 0,
1132 .access = PL1_RW, .type = ARM_CP_NOP },
1133 REGINFO_SENTINEL
1134};
1135
1136static void cortex_r4_initfn(Object *obj)
1137{
1138 ARMCPU *cpu = ARM_CPU(obj);
1139 set_feature(&cpu->env, ARM_FEATURE_V7);
1140 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1141 set_feature(&cpu->env, ARM_FEATURE_MPU);
1142 cpu->midr = 0x411FC144;
1143 cpu->id_pfr0 = 0x0131;
1144 cpu->id_pfr1 = 0x001;
1145 cpu->id_dfr0 = 0x010400;
1146 cpu->id_afr0 = 0x0;
1147 cpu->id_mmfr0 = 0x0210030;
1148 cpu->id_mmfr1 = 0x00000000;
1149 cpu->id_mmfr2 = 0x01200000;
1150 cpu->id_mmfr3 = 0x0211;
1151 cpu->id_isar0 = 0x1101111;
1152 cpu->id_isar1 = 0x13112111;
1153 cpu->id_isar2 = 0x21232131;
1154 cpu->id_isar3 = 0x01112131;
1155 cpu->id_isar4 = 0x0010142;
1156 cpu->id_isar5 = 0x0;
1157 cpu->mp_is_up = true;
1158}
1159
1160static void cortex_r5_initfn(Object *obj)
1161{
1162 ARMCPU *cpu = ARM_CPU(obj);
1163
1164 cpu->dtb_compatible = "arm,cortex-r5";
1165 set_feature(&cpu->env, ARM_FEATURE_V7);
1166 set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
1167 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1168 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1169 set_feature(&cpu->env, ARM_FEATURE_MPU);
1170 cpu->midr = 0x411fc153;
1171 cpu->id_pfr0 = 0x0131;
1172 cpu->id_pfr1 = 0x001;
1173 cpu->id_dfr0 = 0x010400;
1174 cpu->id_afr0 = 0x0;
1175 cpu->id_mmfr0 = 0x0210030;
1176 cpu->id_mmfr1 = 0x00000000;
1177 cpu->id_mmfr2 = 0x01200000;
1178 cpu->id_mmfr3 = 0x0211;
1179 cpu->id_isar0 = 0x2101111;
1180 cpu->id_isar1 = 0x13112111;
1181 cpu->id_isar2 = 0x21232141;
1182 cpu->id_isar3 = 0x01112131;
1183 cpu->id_isar4 = 0x0010142;
1184 cpu->id_isar5 = 0x0;
1185 cpu->mp_is_up = true;
1186 define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
1187}
1188
1189static void cortex_r5f_initfn(Object *obj)
1190{
1191 ARMCPU *cpu = ARM_CPU(obj);
1192
1193 cortex_r5_initfn(obj);
1194 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1195}
1196
1197static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
1198 { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
1199 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1200 { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1201 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1202 REGINFO_SENTINEL
1203};
1204
1205static void cortex_a8_initfn(Object *obj)
1206{
1207 ARMCPU *cpu = ARM_CPU(obj);
1208
1209 cpu->dtb_compatible = "arm,cortex-a8";
1210 set_feature(&cpu->env, ARM_FEATURE_V7);
1211 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1212 set_feature(&cpu->env, ARM_FEATURE_NEON);
1213 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1214 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1215 set_feature(&cpu->env, ARM_FEATURE_EL3);
1216 cpu->midr = 0x410fc080;
1217 cpu->reset_fpsid = 0x410330c0;
1218 cpu->mvfr0 = 0x11110222;
1219 cpu->mvfr1 = 0x00011100;
1220 cpu->ctr = 0x82048004;
1221 cpu->reset_sctlr = 0x00c50078;
1222 cpu->id_pfr0 = 0x1031;
1223 cpu->id_pfr1 = 0x11;
1224 cpu->id_dfr0 = 0x400;
1225 cpu->id_afr0 = 0;
1226 cpu->id_mmfr0 = 0x31100003;
1227 cpu->id_mmfr1 = 0x20000000;
1228 cpu->id_mmfr2 = 0x01202000;
1229 cpu->id_mmfr3 = 0x11;
1230 cpu->id_isar0 = 0x00101111;
1231 cpu->id_isar1 = 0x12112111;
1232 cpu->id_isar2 = 0x21232031;
1233 cpu->id_isar3 = 0x11112131;
1234 cpu->id_isar4 = 0x00111142;
1235 cpu->dbgdidr = 0x15141000;
1236 cpu->clidr = (1 << 27) | (2 << 24) | 3;
1237 cpu->ccsidr[0] = 0xe007e01a;
1238 cpu->ccsidr[1] = 0x2007e01a;
1239 cpu->ccsidr[2] = 0xf0000000;
1240 cpu->reset_auxcr = 2;
1241 define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
1242}
1243
1244static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
1245
1246
1247
1248 { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1249 .access = PL1_RW, .resetvalue = 0,
1250 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
1251 { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
1252 .access = PL1_RW, .resetvalue = 0,
1253 .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
1254 { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
1255 .access = PL1_RW, .resetvalue = 0,
1256 .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
1257 { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1258 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1259
1260 { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
1261 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1262 { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
1263 .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
1264 { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
1265 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1266 { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
1267 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1268 { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1269 .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1270 REGINFO_SENTINEL
1271};
1272
1273static void cortex_a9_initfn(Object *obj)
1274{
1275 ARMCPU *cpu = ARM_CPU(obj);
1276
1277 cpu->dtb_compatible = "arm,cortex-a9";
1278 set_feature(&cpu->env, ARM_FEATURE_V7);
1279 set_feature(&cpu->env, ARM_FEATURE_VFP3);
1280 set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1281 set_feature(&cpu->env, ARM_FEATURE_NEON);
1282 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1283 set_feature(&cpu->env, ARM_FEATURE_EL3);
1284
1285
1286
1287
1288 set_feature(&cpu->env, ARM_FEATURE_V7MP);
1289 set_feature(&cpu->env, ARM_FEATURE_CBAR);
1290 cpu->midr = 0x410fc090;
1291 cpu->reset_fpsid = 0x41033090;
1292 cpu->mvfr0 = 0x11110222;
1293 cpu->mvfr1 = 0x01111111;
1294 cpu->ctr = 0x80038003;
1295 cpu->reset_sctlr = 0x00c50078;
1296 cpu->id_pfr0 = 0x1031;
1297 cpu->id_pfr1 = 0x11;
1298 cpu->id_dfr0 = 0x000;
1299 cpu->id_afr0 = 0;
1300 cpu->id_mmfr0 = 0x00100103;
1301 cpu->id_mmfr1 = 0x20000000;
1302 cpu->id_mmfr2 = 0x01230000;
1303 cpu->id_mmfr3 = 0x00002111;
1304 cpu->id_isar0 = 0x00101111;
1305 cpu->id_isar1 = 0x13112111;
1306 cpu->id_isar2 = 0x21232041;
1307 cpu->id_isar3 = 0x11112131;
1308 cpu->id_isar4 = 0x00111142;
1309 cpu->dbgdidr = 0x35141000;
1310 cpu->clidr = (1 << 27) | (1 << 24) | 3;
1311 cpu->ccsidr[0] = 0xe00fe019;
1312 cpu->ccsidr[1] = 0x200fe019;
1313 define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1314}
1315
1316#ifndef CONFIG_USER_ONLY
1317static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1318{
1319
1320
1321
1322 return ((smp_cpus - 1) << 24) | (1 << 23);
1323}
1324#endif
1325
1326static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1327#ifndef CONFIG_USER_ONLY
1328 { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1329 .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1330 .writefn = arm_cp_write_ignore, },
1331#endif
1332 { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1333 .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1334 REGINFO_SENTINEL
1335};
1336
1337static void cortex_a15_initfn(Object *obj)
1338{
1339 ARMCPU *cpu = ARM_CPU(obj);
1340
1341 cpu->dtb_compatible = "arm,cortex-a15";
1342 set_feature(&cpu->env, ARM_FEATURE_V7);
1343 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1344 set_feature(&cpu->env, ARM_FEATURE_NEON);
1345 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1346 set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1347 set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1348 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1349 set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1350 set_feature(&cpu->env, ARM_FEATURE_LPAE);
1351 set_feature(&cpu->env, ARM_FEATURE_EL3);
1352 cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1353 cpu->midr = 0x412fc0f1;
1354 cpu->reset_fpsid = 0x410430f0;
1355 cpu->mvfr0 = 0x10110222;
1356 cpu->mvfr1 = 0x11111111;
1357 cpu->ctr = 0x8444c004;
1358 cpu->reset_sctlr = 0x00c50078;
1359 cpu->id_pfr0 = 0x00001131;
1360 cpu->id_pfr1 = 0x00011011;
1361 cpu->id_dfr0 = 0x02010555;
1362 cpu->pmceid0 = 0x0000000;
1363 cpu->pmceid1 = 0x00000000;
1364 cpu->id_afr0 = 0x00000000;
1365 cpu->id_mmfr0 = 0x10201105;
1366 cpu->id_mmfr1 = 0x20000000;
1367 cpu->id_mmfr2 = 0x01240000;
1368 cpu->id_mmfr3 = 0x02102211;
1369 cpu->id_isar0 = 0x02101110;
1370 cpu->id_isar1 = 0x13112111;
1371 cpu->id_isar2 = 0x21232041;
1372 cpu->id_isar3 = 0x11112131;
1373 cpu->id_isar4 = 0x10011142;
1374 cpu->dbgdidr = 0x3515f021;
1375 cpu->clidr = 0x0a200023;
1376 cpu->ccsidr[0] = 0x701fe00a;
1377 cpu->ccsidr[1] = 0x201fe00a;
1378 cpu->ccsidr[2] = 0x711fe07a;
1379 define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1380}
1381
1382static void ti925t_initfn(Object *obj)
1383{
1384 ARMCPU *cpu = ARM_CPU(obj);
1385 set_feature(&cpu->env, ARM_FEATURE_V4T);
1386 set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1387 cpu->midr = ARM_CPUID_TI925T;
1388 cpu->ctr = 0x5109149;
1389 cpu->reset_sctlr = 0x00000070;
1390}
1391
1392static void sa1100_initfn(Object *obj)
1393{
1394 ARMCPU *cpu = ARM_CPU(obj);
1395
1396 cpu->dtb_compatible = "intel,sa1100";
1397 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1398 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1399 cpu->midr = 0x4401A11B;
1400 cpu->reset_sctlr = 0x00000070;
1401}
1402
1403static void sa1110_initfn(Object *obj)
1404{
1405 ARMCPU *cpu = ARM_CPU(obj);
1406 set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1407 set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1408 cpu->midr = 0x6901B119;
1409 cpu->reset_sctlr = 0x00000070;
1410}
1411
1412static void pxa250_initfn(Object *obj)
1413{
1414 ARMCPU *cpu = ARM_CPU(obj);
1415
1416 cpu->dtb_compatible = "marvell,xscale";
1417 set_feature(&cpu->env, ARM_FEATURE_V5);
1418 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1419 cpu->midr = 0x69052100;
1420 cpu->ctr = 0xd172172;
1421 cpu->reset_sctlr = 0x00000078;
1422}
1423
1424static void pxa255_initfn(Object *obj)
1425{
1426 ARMCPU *cpu = ARM_CPU(obj);
1427
1428 cpu->dtb_compatible = "marvell,xscale";
1429 set_feature(&cpu->env, ARM_FEATURE_V5);
1430 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1431 cpu->midr = 0x69052d00;
1432 cpu->ctr = 0xd172172;
1433 cpu->reset_sctlr = 0x00000078;
1434}
1435
1436static void pxa260_initfn(Object *obj)
1437{
1438 ARMCPU *cpu = ARM_CPU(obj);
1439
1440 cpu->dtb_compatible = "marvell,xscale";
1441 set_feature(&cpu->env, ARM_FEATURE_V5);
1442 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1443 cpu->midr = 0x69052903;
1444 cpu->ctr = 0xd172172;
1445 cpu->reset_sctlr = 0x00000078;
1446}
1447
1448static void pxa261_initfn(Object *obj)
1449{
1450 ARMCPU *cpu = ARM_CPU(obj);
1451
1452 cpu->dtb_compatible = "marvell,xscale";
1453 set_feature(&cpu->env, ARM_FEATURE_V5);
1454 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1455 cpu->midr = 0x69052d05;
1456 cpu->ctr = 0xd172172;
1457 cpu->reset_sctlr = 0x00000078;
1458}
1459
1460static void pxa262_initfn(Object *obj)
1461{
1462 ARMCPU *cpu = ARM_CPU(obj);
1463
1464 cpu->dtb_compatible = "marvell,xscale";
1465 set_feature(&cpu->env, ARM_FEATURE_V5);
1466 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1467 cpu->midr = 0x69052d06;
1468 cpu->ctr = 0xd172172;
1469 cpu->reset_sctlr = 0x00000078;
1470}
1471
1472static void pxa270a0_initfn(Object *obj)
1473{
1474 ARMCPU *cpu = ARM_CPU(obj);
1475
1476 cpu->dtb_compatible = "marvell,xscale";
1477 set_feature(&cpu->env, ARM_FEATURE_V5);
1478 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1479 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1480 cpu->midr = 0x69054110;
1481 cpu->ctr = 0xd172172;
1482 cpu->reset_sctlr = 0x00000078;
1483}
1484
1485static void pxa270a1_initfn(Object *obj)
1486{
1487 ARMCPU *cpu = ARM_CPU(obj);
1488
1489 cpu->dtb_compatible = "marvell,xscale";
1490 set_feature(&cpu->env, ARM_FEATURE_V5);
1491 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1492 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1493 cpu->midr = 0x69054111;
1494 cpu->ctr = 0xd172172;
1495 cpu->reset_sctlr = 0x00000078;
1496}
1497
1498static void pxa270b0_initfn(Object *obj)
1499{
1500 ARMCPU *cpu = ARM_CPU(obj);
1501
1502 cpu->dtb_compatible = "marvell,xscale";
1503 set_feature(&cpu->env, ARM_FEATURE_V5);
1504 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1505 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1506 cpu->midr = 0x69054112;
1507 cpu->ctr = 0xd172172;
1508 cpu->reset_sctlr = 0x00000078;
1509}
1510
1511static void pxa270b1_initfn(Object *obj)
1512{
1513 ARMCPU *cpu = ARM_CPU(obj);
1514
1515 cpu->dtb_compatible = "marvell,xscale";
1516 set_feature(&cpu->env, ARM_FEATURE_V5);
1517 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1518 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1519 cpu->midr = 0x69054113;
1520 cpu->ctr = 0xd172172;
1521 cpu->reset_sctlr = 0x00000078;
1522}
1523
1524static void pxa270c0_initfn(Object *obj)
1525{
1526 ARMCPU *cpu = ARM_CPU(obj);
1527
1528 cpu->dtb_compatible = "marvell,xscale";
1529 set_feature(&cpu->env, ARM_FEATURE_V5);
1530 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1531 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1532 cpu->midr = 0x69054114;
1533 cpu->ctr = 0xd172172;
1534 cpu->reset_sctlr = 0x00000078;
1535}
1536
1537static void pxa270c5_initfn(Object *obj)
1538{
1539 ARMCPU *cpu = ARM_CPU(obj);
1540
1541 cpu->dtb_compatible = "marvell,xscale";
1542 set_feature(&cpu->env, ARM_FEATURE_V5);
1543 set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1544 set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1545 cpu->midr = 0x69054117;
1546 cpu->ctr = 0xd172172;
1547 cpu->reset_sctlr = 0x00000078;
1548}
1549
1550#ifdef CONFIG_USER_ONLY
1551static void arm_any_initfn(Object *obj)
1552{
1553 ARMCPU *cpu = ARM_CPU(obj);
1554 set_feature(&cpu->env, ARM_FEATURE_V8);
1555 set_feature(&cpu->env, ARM_FEATURE_VFP4);
1556 set_feature(&cpu->env, ARM_FEATURE_NEON);
1557 set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1558 set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1559 set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1560 set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1561 set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1562 set_feature(&cpu->env, ARM_FEATURE_CRC);
1563 cpu->midr = 0xffffffff;
1564}
1565#endif
1566
1567#endif
1568
1569typedef struct ARMCPUInfo {
1570 const char *name;
1571 void (*initfn)(Object *obj);
1572 void (*class_init)(ObjectClass *oc, void *data);
1573} ARMCPUInfo;
1574
1575static const ARMCPUInfo arm_cpus[] = {
1576#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1577 { .name = "arm926", .initfn = arm926_initfn },
1578 { .name = "arm946", .initfn = arm946_initfn },
1579 { .name = "arm1026", .initfn = arm1026_initfn },
1580
1581
1582
1583
1584 { .name = "arm1136-r2", .initfn = arm1136_r2_initfn },
1585 { .name = "arm1136", .initfn = arm1136_initfn },
1586 { .name = "arm1176", .initfn = arm1176_initfn },
1587 { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1588 { .name = "cortex-m3", .initfn = cortex_m3_initfn,
1589 .class_init = arm_v7m_class_init },
1590 { .name = "cortex-m4", .initfn = cortex_m4_initfn,
1591 .class_init = arm_v7m_class_init },
1592 { .name = "cortex-r4", .initfn = cortex_r4_initfn },
1593 { .name = "cortex-r5", .initfn = cortex_r5_initfn },
1594 { .name = "cortex-r5f", .initfn = cortex_r5f_initfn },
1595 { .name = "cortex-a8", .initfn = cortex_a8_initfn },
1596 { .name = "cortex-a9", .initfn = cortex_a9_initfn },
1597 { .name = "cortex-a15", .initfn = cortex_a15_initfn },
1598 { .name = "ti925t", .initfn = ti925t_initfn },
1599 { .name = "sa1100", .initfn = sa1100_initfn },
1600 { .name = "sa1110", .initfn = sa1110_initfn },
1601 { .name = "pxa250", .initfn = pxa250_initfn },
1602 { .name = "pxa255", .initfn = pxa255_initfn },
1603 { .name = "pxa260", .initfn = pxa260_initfn },
1604 { .name = "pxa261", .initfn = pxa261_initfn },
1605 { .name = "pxa262", .initfn = pxa262_initfn },
1606
1607 { .name = "pxa270", .initfn = pxa270a0_initfn },
1608 { .name = "pxa270-a0", .initfn = pxa270a0_initfn },
1609 { .name = "pxa270-a1", .initfn = pxa270a1_initfn },
1610 { .name = "pxa270-b0", .initfn = pxa270b0_initfn },
1611 { .name = "pxa270-b1", .initfn = pxa270b1_initfn },
1612 { .name = "pxa270-c0", .initfn = pxa270c0_initfn },
1613 { .name = "pxa270-c5", .initfn = pxa270c5_initfn },
1614#ifdef CONFIG_USER_ONLY
1615 { .name = "any", .initfn = arm_any_initfn },
1616#endif
1617#endif
1618 { .name = NULL }
1619};
1620
1621static Property arm_cpu_properties[] = {
1622 DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1623 DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1624 DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1625
1626 DEFINE_PROP_UINT32("ctr", ARMCPU, ctr, 0),
1627 DEFINE_PROP_UINT32("clidr", ARMCPU, clidr, 0),
1628 DEFINE_PROP_UINT32("id_pfr0", ARMCPU, id_pfr0, 0),
1629 DEFINE_PROP_UINT32("id_pfr1", ARMCPU, id_pfr1, 0),
1630 DEFINE_PROP_UINT32("ccsidr0", ARMCPU, ccsidr[0], 0),
1631 DEFINE_PROP_UINT32("ccsidr1", ARMCPU, ccsidr[1], 0),
1632 DEFINE_PROP_END_OF_LIST()
1633};
1634
1635
1636static void update_wfi_out(void *opaque, int level)
1637{
1638 ARMCPU *cpu = ARM_CPU(opaque);
1639
1640 cpu->is_in_wfi = level;
1641 qemu_set_irq(cpu->wfi, level);
1642}
1643
1644static void set_debug_context(CPUState *cs, unsigned int ctx)
1645{
1646 ARMCPU *cpu = ARM_CPU(cs);
1647 switch (ctx) {
1648 case ARM_DEBUG_CURRENT_EL:
1649 cpu->env.debug_ctx = DEBUG_CURRENT_EL;
1650 break;
1651
1652 case ARM_DEBUG_PHYS:
1653 cpu->env.debug_ctx = DEBUG_PHYS;
1654 break;
1655 }
1656}
1657
1658static void arm_cpu_pwr_cntrl(void *opaque, int n, int level)
1659{
1660 DeviceClass *dc_parent = DEVICE_CLASS(ARM_CPU_PARENT_CLASS);
1661
1662 dc_parent->pwr_cntrl(opaque, n, level);
1663 update_wfi_out(opaque, level);
1664}
1665
1666#ifdef CONFIG_USER_ONLY
1667static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1668 int mmu_idx)
1669{
1670 ARMCPU *cpu = ARM_CPU(cs);
1671 CPUARMState *env = &cpu->env;
1672
1673 env->exception.vaddress = address;
1674 if (rw == 2) {
1675 cs->exception_index = EXCP_PREFETCH_ABORT;
1676 } else {
1677 cs->exception_index = EXCP_DATA_ABORT;
1678 }
1679 return 1;
1680}
1681#endif
1682
1683static gchar *arm_gdb_arch_name(CPUState *cs)
1684{
1685 ARMCPU *cpu = ARM_CPU(cs);
1686 CPUARMState *env = &cpu->env;
1687
1688 if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
1689 return g_strdup("iwmmxt");
1690 }
1691 return g_strdup("arm");
1692}
1693
1694static void arm_cpu_class_init(ObjectClass *oc, void *data)
1695{
1696 ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1697 CPUClass *cc = CPU_CLASS(acc);
1698 DeviceClass *dc = DEVICE_CLASS(oc);
1699
1700 acc->parent_realize = dc->realize;
1701 dc->realize = arm_cpu_realizefn;
1702 dc->props = arm_cpu_properties;
1703 dc->pwr_cntrl = arm_cpu_pwr_cntrl;
1704 dc->rst_cntrl = cpu_reset_gpio;
1705
1706 acc->parent_reset = cc->reset;
1707 cc->reset = arm_cpu_reset;
1708
1709 cc->class_by_name = arm_cpu_class_by_name;
1710 cc->has_work = arm_cpu_has_work;
1711 cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1712 cc->dump_state = arm_cpu_dump_state;
1713 cc->set_pc = arm_cpu_set_pc;
1714 cc->get_pc = arm_cpu_get_pc;
1715 cc->debug_contexts = arm_debug_ctx;
1716 cc->set_debug_context = set_debug_context;
1717 cc->gdb_read_register = arm_cpu_gdb_read_register;
1718 cc->gdb_write_register = arm_cpu_gdb_write_register;
1719#ifdef CONFIG_USER_ONLY
1720 cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1721#else
1722 cc->do_interrupt = arm_cpu_do_interrupt;
1723 cc->do_unaligned_access = arm_cpu_do_unaligned_access;
1724 cc->get_phys_page_attrs_debug = arm_cpu_get_phys_page_attrs_debug;
1725 cc->asidx_from_attrs = arm_asidx_from_attrs;
1726 cc->vmsd = &vmstate_arm_cpu;
1727 cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian;
1728 cc->write_elf64_note = arm_cpu_write_elf64_note;
1729 cc->write_elf32_note = arm_cpu_write_elf32_note;
1730#endif
1731 cc->gdb_num_core_regs = 32;
1732 cc->gdb_core_xml_file = "arm-core.xml";
1733 cc->gdb_arch_name = arm_gdb_arch_name;
1734 cc->gdb_stop_before_watchpoint = true;
1735 cc->debug_excp_handler = arm_debug_excp_handler;
1736 cc->debug_check_watchpoint = arm_debug_check_watchpoint;
1737
1738 cc->disas_set_info = arm_disas_set_info;
1739
1740
1741
1742
1743
1744
1745
1746
1747
1748
1749 dc->cannot_destroy_with_object_finalize_yet = true;
1750}
1751
1752static void cpu_register(const ARMCPUInfo *info)
1753{
1754 TypeInfo type_info = {
1755 .parent = TYPE_ARM_CPU,
1756 .instance_size = sizeof(ARMCPU),
1757 .instance_init = info->initfn,
1758 .class_size = sizeof(ARMCPUClass),
1759 .class_init = info->class_init,
1760 };
1761
1762 type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1763 type_register(&type_info);
1764 g_free((void *)type_info.name);
1765}
1766
1767static const TypeInfo arm_cpu_type_info = {
1768 .name = TYPE_ARM_CPU,
1769 .parent = TYPE_CPU,
1770 .instance_size = sizeof(ARMCPU),
1771 .instance_init = arm_cpu_initfn,
1772 .instance_post_init = arm_cpu_post_init,
1773 .instance_finalize = arm_cpu_finalizefn,
1774 .abstract = true,
1775 .class_size = sizeof(ARMCPUClass),
1776 .class_init = arm_cpu_class_init,
1777};
1778
1779static void arm_cpu_register_types(void)
1780{
1781 const ARMCPUInfo *info = arm_cpus;
1782
1783 type_register_static(&arm_cpu_type_info);
1784
1785 while (info->name) {
1786 cpu_register(info);
1787 info++;
1788 }
1789}
1790
1791type_init(arm_cpu_register_types)
1792
1793#ifndef CONFIG_USER_ONLY
1794
1795static int armv8_timer_fdt_init(char *node_path, FDTMachineInfo *fdti,
1796 void *priv)
1797{
1798 CPUState *cpu;
1799 bool map_mode = false;
1800 qemu_irq *sec_irqs = fdt_get_irq(fdti, node_path, 0, &map_mode);
1801 qemu_irq *ns_irqs = fdt_get_irq(fdti, node_path, 1, &map_mode);
1802 qemu_irq *v_irqs = fdt_get_irq(fdti, node_path, 2, &map_mode);
1803 qemu_irq *h_irqs = fdt_get_irq(fdti, node_path, 3, &map_mode);
1804
1805 assert(!map_mode);
1806
1807 for (cpu = first_cpu; cpu; cpu = CPU_NEXT(cpu)) {
1808 ARMCPU *acpu = ARM_CPU(cpu);
1809
1810 if (!arm_feature(&acpu->env, ARM_FEATURE_GENERIC_TIMER)) {
1811 continue;
1812 }
1813 assert(*sec_irqs);
1814 assert(*ns_irqs);
1815 assert(*v_irqs);
1816 assert(*h_irqs);
1817 qdev_connect_gpio_out(DEVICE(acpu), 0, *ns_irqs++);
1818 qdev_connect_gpio_out(DEVICE(acpu), 1, *v_irqs++);
1819 qdev_connect_gpio_out(DEVICE(acpu), 2, *h_irqs++);
1820 qdev_connect_gpio_out(DEVICE(acpu), 3, *sec_irqs++);
1821 }
1822
1823 return 0;
1824}
1825
1826fdt_register_compatibility_n(armv8_timer_fdt_init,
1827 "compatible:arm,armv8-timer", 13);
1828
1829#endif
1830
1831static const TypeInfo fdt_qom_aliases [] = {
1832#if defined(TARGET_AARCH64)
1833 { .name = "arm.armv8", .parent = "cortex-a57-arm-cpu" },
1834#endif
1835 { .name = "arm.cortex-r5", .parent = "cortex-r5-arm-cpu" },
1836 { .name = "arm.cortex-r5f", .parent = "cortex-r5f-arm-cpu" },
1837 { .name = "arm.cortex-a9", .parent = "cortex-a9-arm-cpu" },
1838};
1839
1840static void fdt_generic_register_types(void)
1841{
1842 int i;
1843
1844 for (i = 0; i < ARRAY_SIZE(fdt_qom_aliases); ++i) {
1845 type_register_static(&fdt_qom_aliases[i]);
1846 }
1847}
1848
1849type_init(fdt_generic_register_types)
1850