LXR qemu/target-cris/machine.c

   1/*
   2 *  CRIS virtual CPU state save/load support
   3 *
   4 *  Copyright (c) 2012 Red Hat, Inc.
   5 *  Written by Juan Quintela <quintela@redhat.com>
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/hw.h"
  23
  24static const VMStateDescription vmstate_tlbset = {
  25    .name = "cpu/tlbset",
  26    .version_id = 1,
  27    .minimum_version_id = 1,
  28    .fields = (VMStateField[]) {
  29        VMSTATE_UINT32(lo, TLBSet),
  30        VMSTATE_UINT32(hi, TLBSet),
  31        VMSTATE_END_OF_LIST()
  32    }
  33};
  34
  35static const VMStateDescription vmstate_cris_env = {
  36    .name = "env",
  37    .version_id = 2,
  38    .minimum_version_id = 2,
  39    .fields = (VMStateField[]) {
  40        VMSTATE_UINT32_ARRAY(regs, CPUCRISState, 16),
  41        VMSTATE_UINT32_ARRAY(pregs, CPUCRISState, 16),
  42        VMSTATE_UINT32(pc, CPUCRISState),
  43        VMSTATE_UINT32(ksp, CPUCRISState),
  44        VMSTATE_INT32(dslot, CPUCRISState),
  45        VMSTATE_INT32(btaken, CPUCRISState),
  46        VMSTATE_UINT32(btarget, CPUCRISState),
  47        VMSTATE_UINT32(cc_op, CPUCRISState),
  48        VMSTATE_UINT32(cc_mask, CPUCRISState),
  49        VMSTATE_UINT32(cc_dest, CPUCRISState),
  50        VMSTATE_UINT32(cc_src, CPUCRISState),
  51        VMSTATE_UINT32(cc_result, CPUCRISState),
  52        VMSTATE_INT32(cc_size, CPUCRISState),
  53        VMSTATE_INT32(cc_x, CPUCRISState),
  54        VMSTATE_INT32(locked_irq, CPUCRISState),
  55        VMSTATE_INT32(interrupt_vector, CPUCRISState),
  56        VMSTATE_INT32(fault_vector, CPUCRISState),
  57        VMSTATE_INT32(trap_vector, CPUCRISState),
  58        VMSTATE_UINT32_ARRAY(sregs[0], CPUCRISState, 16),
  59        VMSTATE_UINT32_ARRAY(sregs[1], CPUCRISState, 16),
  60        VMSTATE_UINT32_ARRAY(sregs[2], CPUCRISState, 16),
  61        VMSTATE_UINT32_ARRAY(sregs[3], CPUCRISState, 16),
  62        VMSTATE_UINT32(mmu_rand_lfsr, CPUCRISState),
  63        VMSTATE_STRUCT_ARRAY(tlbsets[0][0], CPUCRISState, 16, 0,
  64                             vmstate_tlbset, TLBSet),
  65        VMSTATE_STRUCT_ARRAY(tlbsets[0][1], CPUCRISState, 16, 0,
  66                             vmstate_tlbset, TLBSet),
  67        VMSTATE_STRUCT_ARRAY(tlbsets[0][2], CPUCRISState, 16, 0,
  68                             vmstate_tlbset, TLBSet),
  69        VMSTATE_STRUCT_ARRAY(tlbsets[0][3], CPUCRISState, 16, 0,
  70                             vmstate_tlbset, TLBSet),
  71        VMSTATE_STRUCT_ARRAY(tlbsets[1][0], CPUCRISState, 16, 0,
  72                             vmstate_tlbset, TLBSet),
  73        VMSTATE_STRUCT_ARRAY(tlbsets[1][1], CPUCRISState, 16, 0,
  74                             vmstate_tlbset, TLBSet),
  75        VMSTATE_STRUCT_ARRAY(tlbsets[1][2], CPUCRISState, 16, 0,
  76                             vmstate_tlbset, TLBSet),
  77        VMSTATE_STRUCT_ARRAY(tlbsets[1][3], CPUCRISState, 16, 0,
  78                             vmstate_tlbset, TLBSet),
  79        VMSTATE_END_OF_LIST()
  80    }
  81};
  82
  83const VMStateDescription vmstate_cris_cpu = {
  84    .name = "cpu",
  85    .version_id = 1,
  86    .minimum_version_id = 1,
  87    .fields = (VMStateField[]) {
  88        VMSTATE_CPU(),
  89        VMSTATE_STRUCT(env, CRISCPU, 1, vmstate_cris_env, CPUCRISState),
  90        VMSTATE_END_OF_LIST()
  91    }
  92};
  93