LXR qemu/target-i386/gdbstub.c

   1/*
   2 * x86 gdb server stub
   3 *
   4 * Copyright (c) 2003-2005 Fabrice Bellard
   5 * Copyright (c) 2013 SUSE LINUX Products GmbH
   6 *
   7 * This library is free software; you can redistribute it and/or
   8 * modify it under the terms of the GNU Lesser General Public
   9 * License as published by the Free Software Foundation; either
  10 * version 2 of the License, or (at your option) any later version.
  11 *
  12 * This library is distributed in the hope that it will be useful,
  13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15 * Lesser General Public License for more details.
  16 *
  17 * You should have received a copy of the GNU Lesser General Public
  18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19 */
  20#include "qemu/osdep.h"
  21#include "qemu-common.h"
  22#include "exec/gdbstub.h"
  23
  24#ifdef TARGET_X86_64
  25static const int gpr_map[16] = {
  26    R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
  27    8, 9, 10, 11, 12, 13, 14, 15
  28};
  29#else
  30#define gpr_map gpr_map32
  31#endif
  32static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
  33
  34#define IDX_IP_REG      CPU_NB_REGS
  35#define IDX_FLAGS_REG   (IDX_IP_REG + 1)
  36#define IDX_SEG_REGS    (IDX_FLAGS_REG + 1)
  37#define IDX_FP_REGS     (IDX_SEG_REGS + 6)
  38#define IDX_XMM_REGS    (IDX_FP_REGS + 16)
  39#define IDX_MXCSR_REG   (IDX_XMM_REGS + CPU_NB_REGS)
  40
  41int x86_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
  42{
  43    X86CPU *cpu = X86_CPU(cs);
  44    CPUX86State *env = &cpu->env;
  45
  46    if (n < CPU_NB_REGS) {
  47        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
  48            return gdb_get_reg64(mem_buf, env->regs[gpr_map[n]]);
  49        } else if (n < CPU_NB_REGS32) {
  50            return gdb_get_reg32(mem_buf, env->regs[gpr_map32[n]]);
  51        }
  52    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
  53#ifdef USE_X86LDOUBLE
  54        /* FIXME: byteswap float values - after fixing fpregs layout. */
  55        memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
  56#else
  57        memset(mem_buf, 0, 10);
  58#endif
  59        return 10;
  60    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
  61        n -= IDX_XMM_REGS;
  62        if (n < CPU_NB_REGS32 ||
  63            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
  64            stq_p(mem_buf, env->xmm_regs[n].ZMM_Q(0));
  65            stq_p(mem_buf + 8, env->xmm_regs[n].ZMM_Q(1));
  66            return 16;
  67        }
  68    } else {
  69        switch (n) {
  70        case IDX_IP_REG:
  71            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
  72                return gdb_get_reg64(mem_buf, env->eip);
  73            } else {
  74                return gdb_get_reg32(mem_buf, env->eip);
  75            }
  76        case IDX_FLAGS_REG:
  77            return gdb_get_reg32(mem_buf, env->eflags);
  78
  79        case IDX_SEG_REGS:
  80            return gdb_get_reg32(mem_buf, env->segs[R_CS].selector);
  81        case IDX_SEG_REGS + 1:
  82            return gdb_get_reg32(mem_buf, env->segs[R_SS].selector);
  83        case IDX_SEG_REGS + 2:
  84            return gdb_get_reg32(mem_buf, env->segs[R_DS].selector);
  85        case IDX_SEG_REGS + 3:
  86            return gdb_get_reg32(mem_buf, env->segs[R_ES].selector);
  87        case IDX_SEG_REGS + 4:
  88            return gdb_get_reg32(mem_buf, env->segs[R_FS].selector);
  89        case IDX_SEG_REGS + 5:
  90            return gdb_get_reg32(mem_buf, env->segs[R_GS].selector);
  91
  92        case IDX_FP_REGS + 8:
  93            return gdb_get_reg32(mem_buf, env->fpuc);
  94        case IDX_FP_REGS + 9:
  95            return gdb_get_reg32(mem_buf, (env->fpus & ~0x3800) |
  96                                          (env->fpstt & 0x7) << 11);
  97        case IDX_FP_REGS + 10:
  98            return gdb_get_reg32(mem_buf, 0); /* ftag */
  99        case IDX_FP_REGS + 11:
 100            return gdb_get_reg32(mem_buf, 0); /* fiseg */
 101        case IDX_FP_REGS + 12:
 102            return gdb_get_reg32(mem_buf, 0); /* fioff */
 103        case IDX_FP_REGS + 13:
 104            return gdb_get_reg32(mem_buf, 0); /* foseg */
 105        case IDX_FP_REGS + 14:
 106            return gdb_get_reg32(mem_buf, 0); /* fooff */
 107        case IDX_FP_REGS + 15:
 108            return gdb_get_reg32(mem_buf, 0); /* fop */
 109
 110        case IDX_MXCSR_REG:
 111            return gdb_get_reg32(mem_buf, env->mxcsr);
 112        }
 113    }
 114    return 0;
 115}
 116
 117static int x86_cpu_gdb_load_seg(X86CPU *cpu, int sreg, uint8_t *mem_buf)
 118{
 119    CPUX86State *env = &cpu->env;
 120    uint16_t selector = ldl_p(mem_buf);
 121
 122    if (selector != env->segs[sreg].selector) {
 123#if defined(CONFIG_USER_ONLY)
 124        cpu_x86_load_seg(env, sreg, selector);
 125#else
 126        unsigned int limit, flags;
 127        target_ulong base;
 128
 129        if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
 130            int dpl = (env->eflags & VM_MASK) ? 3 : 0;
 131            base = selector << 4;
 132            limit = 0xffff;
 133            flags = DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
 134                    DESC_A_MASK | (dpl << DESC_DPL_SHIFT);
 135        } else {
 136            if (!cpu_x86_get_descr_debug(env, selector, &base, &limit,
 137                                         &flags)) {
 138                return 4;
 139            }
 140        }
 141        cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
 142#endif
 143    }
 144    return 4;
 145}
 146
 147int x86_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
 148{
 149    X86CPU *cpu = X86_CPU(cs);
 150    CPUX86State *env = &cpu->env;
 151    uint32_t tmp;
 152
 153    if (n < CPU_NB_REGS) {
 154        if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 155            env->regs[gpr_map[n]] = ldtul_p(mem_buf);
 156            return sizeof(target_ulong);
 157        } else if (n < CPU_NB_REGS32) {
 158            n = gpr_map32[n];
 159            env->regs[n] &= ~0xffffffffUL;
 160            env->regs[n] |= (uint32_t)ldl_p(mem_buf);
 161            return 4;
 162        }
 163    } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
 164#ifdef USE_X86LDOUBLE
 165        /* FIXME: byteswap float values - after fixing fpregs layout. */
 166        memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
 167#endif
 168        return 10;
 169    } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
 170        n -= IDX_XMM_REGS;
 171        if (n < CPU_NB_REGS32 ||
 172            (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
 173            env->xmm_regs[n].ZMM_Q(0) = ldq_p(mem_buf);
 174            env->xmm_regs[n].ZMM_Q(1) = ldq_p(mem_buf + 8);
 175            return 16;
 176        }
 177    } else {
 178        switch (n) {
 179        case IDX_IP_REG:
 180            if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
 181                env->eip = ldq_p(mem_buf);
 182                return 8;
 183            } else {
 184                env->eip &= ~0xffffffffUL;
 185                env->eip |= (uint32_t)ldl_p(mem_buf);
 186                return 4;
 187            }
 188        case IDX_FLAGS_REG:
 189            env->eflags = ldl_p(mem_buf);
 190            return 4;
 191
 192        case IDX_SEG_REGS:
 193            return x86_cpu_gdb_load_seg(cpu, R_CS, mem_buf);
 194        case IDX_SEG_REGS + 1:
 195            return x86_cpu_gdb_load_seg(cpu, R_SS, mem_buf);
 196        case IDX_SEG_REGS + 2:
 197            return x86_cpu_gdb_load_seg(cpu, R_DS, mem_buf);
 198        case IDX_SEG_REGS + 3:
 199            return x86_cpu_gdb_load_seg(cpu, R_ES, mem_buf);
 200        case IDX_SEG_REGS + 4:
 201            return x86_cpu_gdb_load_seg(cpu, R_FS, mem_buf);
 202        case IDX_SEG_REGS + 5:
 203            return x86_cpu_gdb_load_seg(cpu, R_GS, mem_buf);
 204
 205        case IDX_FP_REGS + 8:
 206            cpu_set_fpuc(env, ldl_p(mem_buf));
 207            return 4;
 208        case IDX_FP_REGS + 9:
 209            tmp = ldl_p(mem_buf);
 210            env->fpstt = (tmp >> 11) & 7;
 211            env->fpus = tmp & ~0x3800;
 212            return 4;
 213        case IDX_FP_REGS + 10: /* ftag */
 214            return 4;
 215        case IDX_FP_REGS + 11: /* fiseg */
 216            return 4;
 217        case IDX_FP_REGS + 12: /* fioff */
 218            return 4;
 219        case IDX_FP_REGS + 13: /* foseg */
 220            return 4;
 221        case IDX_FP_REGS + 14: /* fooff */
 222            return 4;
 223        case IDX_FP_REGS + 15: /* fop */
 224            return 4;
 225
 226        case IDX_MXCSR_REG:
 227            cpu_set_mxcsr(env, ldl_p(mem_buf));
 228            return 4;
 229        }
 230    }
 231    /* Unrecognised register.  */
 232    return 0;
 233}
 234