LXR qemu/target-microblaze/cpu-qom.h

   1/*
   2 * QEMU MicroBlaze CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20#ifndef QEMU_MICROBLAZE_CPU_QOM_H
  21#define QEMU_MICROBLAZE_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24
  25#define TYPE_MICROBLAZE_CPU "microblaze-cpu"
  26
  27#define MICROBLAZE_CPU_CLASS(klass) \
  28    OBJECT_CLASS_CHECK(MicroBlazeCPUClass, (klass), TYPE_MICROBLAZE_CPU)
  29#define MICROBLAZE_CPU(obj) \
  30    OBJECT_CHECK(MicroBlazeCPU, (obj), TYPE_MICROBLAZE_CPU)
  31#define MICROBLAZE_CPU_GET_CLASS(obj) \
  32    OBJECT_GET_CLASS(MicroBlazeCPUClass, (obj), TYPE_MICROBLAZE_CPU)
  33
  34/**
  35 * MicroBlazeCPUClass:
  36 * @parent_realize: The parent class' realize handler.
  37 * @parent_reset: The parent class' reset handler.
  38 *
  39 * A MicroBlaze CPU model.
  40 */
  41typedef struct MicroBlazeCPUClass {
  42    /*< private >*/
  43    CPUClass parent_class;
  44    /*< public >*/
  45
  46    DeviceRealize parent_realize;
  47    void (*parent_reset)(CPUState *cpu);
  48} MicroBlazeCPUClass;
  49
  50/**
  51 * MicroBlazeCPU:
  52 * @env: #CPUMBState
  53 *
  54 * A MicroBlaze CPU.
  55 */
  56typedef struct MicroBlazeCPU {
  57    /*< private >*/
  58    CPUState parent_obj;
  59
  60    /*< public >*/
  61    qemu_irq mb_sleep;
  62
  63    /* Microblaze Configuration Settings */
  64    struct {
  65        bool stackprot;
  66        uint32_t base_vectors;
  67        uint8_t use_fpu;
  68        bool use_mmu;
  69        bool dcache_writeback;
  70        bool endi;
  71        char *version;
  72        uint8_t pvr;
  73    } cfg;
  74
  75    CPUMBState env;
  76} MicroBlazeCPU;
  77
  78static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env)
  79{
  80    return container_of(env, MicroBlazeCPU, env);
  81}
  82
  83#define ENV_GET_CPU(e) CPU(mb_env_get_cpu(e))
  84
  85#define ENV_OFFSET offsetof(MicroBlazeCPU, env)
  86
  87void mb_cpu_do_interrupt(CPUState *cs);
  88bool mb_cpu_exec_interrupt(CPUState *cs, int int_req);
  89void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
  90                       int flags);
  91hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  92int mb_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
  93int mb_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  94
  95#endif
  96