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24#include "qemu/osdep.h"
25#include "qapi/error.h"
26#include "cpu.h"
27#include "qemu-common.h"
28#include "hw/qdev-properties.h"
29#include "migration/vmstate.h"
30#include "exec/exec-all.h"
31
32#ifndef CONFIG_USER_ONLY
33#include "hw/fdt_generic_util.h"
34#endif
35
36static const struct {
37 const char *name;
38 uint8_t version_id;
39} mb_cpu_lookup[] = {
40
41 {"5.00.a", 0x01},
42 {"5.00.b", 0x02},
43 {"5.00.c", 0x03},
44 {"6.00.a", 0x04},
45 {"6.00.b", 0x06},
46 {"7.00.a", 0x05},
47 {"7.00.b", 0x07},
48 {"7.10.a", 0x08},
49 {"7.10.b", 0x09},
50 {"7.10.c", 0x0a},
51 {"7.10.d", 0x0b},
52 {"7.20.a", 0x0c},
53 {"7.20.b", 0x0d},
54 {"7.20.c", 0x0e},
55 {"7.20.d", 0x0f},
56 {"7.30.a", 0x10},
57 {"7.30.b", 0x11},
58 {"8.00.a", 0x12},
59 {"8.00.b", 0x13},
60 {"8.10.a", 0x14},
61 {"8.20.a", 0x15},
62 {"8.20.b", 0x16},
63 {"8.30.a", 0x17},
64 {"8.40.a", 0x18},
65 {"8.40.b", 0x19},
66 {"8.50.a", 0x1A},
67 {"9.0", 0x1B},
68 {"9.1", 0x1D},
69 {"9.2", 0x1F},
70 {"9.3", 0x20},
71 {"10.0", 0x24},
72 {NULL, 0},
73};
74
75static void mb_cpu_set_pc(CPUState *cs, vaddr value)
76{
77 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
78
79 cpu->env.sregs[SR_PC] = value;
80}
81
82static vaddr mb_cpu_get_pc(CPUState *cs)
83{
84 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
85
86 return cpu->env.sregs[SR_PC];
87}
88
89static bool mb_cpu_has_work(CPUState *cs)
90{
91 CPUMBState *env = cs->env_ptr;
92 bool r;
93
94 r = (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI))
95 || env->wakeup;
96
97 return r;
98}
99
100#ifndef CONFIG_USER_ONLY
101static void microblaze_cpu_set_irq(void *opaque, int irq, int level)
102{
103 MicroBlazeCPU *cpu = opaque;
104 CPUState *cs = CPU(cpu);
105 int type = irq ? CPU_INTERRUPT_NMI : CPU_INTERRUPT_HARD;
106
107 if (level) {
108 cpu_interrupt(cs, type);
109 } else {
110 cpu_reset_interrupt(cs, type);
111 }
112}
113
114static void microblaze_set_wakeup(void *opaque, int irq, int level)
115{
116 MicroBlazeCPU *cpu = opaque;
117 CPUState *cs = CPU(cpu);
118 CPUMBState *env = &cpu->env;
119
120 env->wakeup &= ~(1 << irq);
121 if (level) {
122 qemu_set_irq(cpu->mb_sleep, false);
123 env->wakeup |= 1 << irq;
124 cs->halted = 0;
125 qemu_cpu_kick(cs);
126 }
127}
128#endif
129
130
131static void mb_cpu_reset(CPUState *s)
132{
133 MicroBlazeCPU *cpu = MICROBLAZE_CPU(s);
134 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(cpu);
135 CPUMBState *env = &cpu->env;
136
137 mcc->parent_reset(s);
138
139 memset(env, 0, offsetof(CPUMBState, pvr));
140 env->res_addr = RES_ADDR_NONE;
141 tlb_flush(s, 1);
142
143
144 env->shr = ~0;
145
146 env->sregs[SR_PC] = cpu->cfg.base_vectors;
147
148#if defined(CONFIG_USER_ONLY)
149
150 env->sregs[SR_MSR] = MSR_EE | MSR_IE | MSR_VM | MSR_UM;
151#else
152 env->sregs[SR_MSR] = 0;
153 mmu_init(&env->mmu);
154 env->mmu.c_mmu = 3;
155 env->mmu.c_mmu_tlb_access = 3;
156 env->mmu.c_mmu_zones = 16;
157
158 if (cpu->env.memattr_p) {
159 env->memattr[0].attrs = *cpu->env.memattr_p;
160 }
161#endif
162}
163
164static void mb_disas_set_info(CPUState *cpu, disassemble_info *info)
165{
166 info->mach = bfd_arch_microblaze;
167 info->print_insn = print_insn_microblaze;
168}
169
170static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
171{
172 CPUState *cs = CPU(dev);
173 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_GET_CLASS(dev);
174 MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs);
175 CPUMBState *env = &cpu->env;
176 uint8_t version_code = 0;
177 int i = 0;
178
179 qemu_init_vcpu(cs);
180
181 env->pvr.regs[0] = PVR0_USE_BARREL_MASK \
182 | PVR0_USE_DIV_MASK \
183 | PVR0_USE_HW_MUL_MASK \
184 | PVR0_USE_EXC_MASK \
185 | PVR0_USE_ICACHE_MASK \
186 | PVR0_USE_DCACHE_MASK \
187 | (0xb << 8);
188 env->pvr.regs[2] = PVR2_D_OPB_MASK \
189 | PVR2_D_LMB_MASK \
190 | PVR2_I_OPB_MASK \
191 | PVR2_I_LMB_MASK \
192 | PVR2_USE_MSR_INSTR \
193 | PVR2_USE_PCMP_INSTR \
194 | PVR2_USE_BARREL_MASK \
195 | PVR2_USE_DIV_MASK \
196 | PVR2_USE_HW_MUL_MASK \
197 | PVR2_USE_MUL64_MASK \
198 | PVR2_FPU_EXC_MASK \
199 | 0;
200
201 for (i = 0; mb_cpu_lookup[i].name && cpu->cfg.version; i++) {
202 if (strcmp(mb_cpu_lookup[i].name, cpu->cfg.version) == 0) {
203 version_code = mb_cpu_lookup[i].version_id;
204 break;
205 }
206 }
207
208 if (!version_code) {
209 qemu_log("Invalid MicroBlaze version number: %s\n", cpu->cfg.version);
210 }
211
212 env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
213 (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
214 (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) |
215 (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) |
216 (version_code << 16) |
217 (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0);
218
219 env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
220 (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
221
222 env->pvr.regs[5] |= cpu->cfg.dcache_writeback ?
223 PVR5_DCACHE_WRITEBACK_MASK : 0;
224
225 env->pvr.regs[10] = 0x0c000000;
226 env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
227
228 mcc->parent_realize(dev, errp);
229}
230
231static void mb_cpu_initfn(Object *obj)
232{
233 CPUState *cs = CPU(obj);
234 MicroBlazeCPU *cpu = MICROBLAZE_CPU(obj);
235 CPUMBState *env = &cpu->env;
236 static bool tcg_initialized;
237
238 cs->env_ptr = env;
239 cpu_exec_init(cs, &error_abort);
240
241 set_float_rounding_mode(float_round_nearest_even, &env->fp_status);
242
243#ifndef CONFIG_USER_ONLY
244
245 qdev_init_gpio_in(DEVICE(cpu), microblaze_cpu_set_irq, 2);
246 qdev_init_gpio_in_named(DEVICE(cpu), microblaze_set_wakeup, "wakeup", 2);
247
248 qdev_init_gpio_out_named(DEVICE(cpu), &cpu->mb_sleep, "mb_sleep", 1);
249
250 object_property_add_link(obj, "memattr", TYPE_MEMORY_TRANSACTION_ATTR,
251 (Object **)&cpu->env.memattr_p,
252 qdev_prop_allow_set_link_before_realize,
253 OBJ_PROP_LINK_UNREF_ON_RELEASE,
254 &error_abort);
255#endif
256
257 if (tcg_enabled() && !tcg_initialized) {
258 tcg_initialized = true;
259 mb_tcg_init();
260 }
261}
262
263static const VMStateDescription vmstate_mb_cpu = {
264 .name = "cpu",
265 .unmigratable = 1,
266};
267
268static Property mb_properties[] = {
269 DEFINE_PROP_UINT32("base-vectors", MicroBlazeCPU, cfg.base_vectors, 0),
270 DEFINE_PROP_BOOL("use-stack-protection", MicroBlazeCPU, cfg.stackprot,
271 false),
272
273
274
275
276 DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
277 DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
278 DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
279 false),
280 DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
281 DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),
282 DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL),
283 DEFINE_PROP_END_OF_LIST(),
284};
285
286#ifndef CONFIG_USER_ONLY
287static const FDTGenericGPIOSet mb_ctrl_gpios[] = {
288 {
289 .names = &fdt_generic_gpio_name_set_gpio,
290 .gpios = (FDTGenericGPIOConnection[]) {
291 { .name = "wakeup", .fdt_index = 0, .range = 2 },
292 { .name = "mb_sleep", .fdt_index = 2 },
293 { },
294 },
295 },
296 { },
297};
298#endif
299
300static void mb_cpu_class_init(ObjectClass *oc, void *data)
301{
302#ifndef CONFIG_USER_ONLY
303 FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(oc);
304#endif
305 DeviceClass *dc = DEVICE_CLASS(oc);
306 CPUClass *cc = CPU_CLASS(oc);
307 MicroBlazeCPUClass *mcc = MICROBLAZE_CPU_CLASS(oc);
308
309 mcc->parent_realize = dc->realize;
310 dc->realize = mb_cpu_realizefn;
311
312 mcc->parent_reset = cc->reset;
313 cc->reset = mb_cpu_reset;
314
315 cc->has_work = mb_cpu_has_work;
316 cc->do_interrupt = mb_cpu_do_interrupt;
317 cc->cpu_exec_interrupt = mb_cpu_exec_interrupt;
318 cc->dump_state = mb_cpu_dump_state;
319 cc->set_pc = mb_cpu_set_pc;
320 cc->get_pc = mb_cpu_get_pc;
321 cc->gdb_read_register = mb_cpu_gdb_read_register;
322 cc->gdb_write_register = mb_cpu_gdb_write_register;
323#ifdef CONFIG_USER_ONLY
324 cc->handle_mmu_fault = mb_cpu_handle_mmu_fault;
325#else
326 cc->do_unassigned_access = mb_cpu_unassigned_access;
327 cc->get_phys_page_debug = mb_cpu_get_phys_page_debug;
328#endif
329 dc->vmsd = &vmstate_mb_cpu;
330 dc->props = mb_properties;
331 cc->gdb_num_core_regs = 32 + 5;
332
333#ifndef CONFIG_USER_ONLY
334 fggc->controller_gpios = mb_ctrl_gpios;
335#endif
336 cc->disas_set_info = mb_disas_set_info;
337
338
339
340
341
342 dc->cannot_destroy_with_object_finalize_yet = true;
343}
344
345static const TypeInfo mb_cpu_type_info = {
346 .name = TYPE_MICROBLAZE_CPU,
347 .parent = TYPE_CPU,
348 .instance_size = sizeof(MicroBlazeCPU),
349 .instance_init = mb_cpu_initfn,
350 .class_size = sizeof(MicroBlazeCPUClass),
351 .class_init = mb_cpu_class_init,
352#ifndef CONFIG_USER_ONLY
353 .interfaces = (InterfaceInfo[]) {
354 { TYPE_FDT_GENERIC_GPIO },
355 { }
356 },
357#endif
358};
359
360static void mb_cpu_register_types(void)
361{
362 type_register_static(&mb_cpu_type_info);
363}
364
365type_init(mb_cpu_register_types)
366
