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19#ifndef CPU_MICROBLAZE_H
20#define CPU_MICROBLAZE_H
21
22#include "qemu-common.h"
23
24#define TARGET_LONG_BITS 32
25
26#define CPUArchState struct CPUMBState
27
28#include "exec/cpu-defs.h"
29#include "fpu/softfloat.h"
30struct CPUMBState;
31typedef struct CPUMBState CPUMBState;
32#if !defined(CONFIG_USER_ONLY)
33#include "mmu.h"
34#endif
35
36#define EXCP_MMU 1
37#define EXCP_IRQ 2
38#define EXCP_BREAK 3
39#define EXCP_HW_BREAK 4
40#define EXCP_HW_EXCP 5
41
42
43#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
44
45
46#define MB_CPU_IRQ 0
47#define MB_CPU_FIR 1
48
49
50#define R_SP 1
51#define SR_PC 0
52#define SR_MSR 1
53#define SR_EAR 3
54#define SR_ESR 5
55#define SR_FSR 7
56#define SR_BTR 0xb
57#define SR_EDR 0xd
58
59
60#define MSR_BE (1<<0)
61#define MSR_IE (1<<1)
62#define MSR_C (1<<2)
63#define MSR_BIP (1<<3)
64#define MSR_FSL (1<<4)
65#define MSR_ICE (1<<5)
66#define MSR_DZ (1<<6)
67#define MSR_DCE (1<<7)
68#define MSR_EE (1<<8)
69#define MSR_EIP (1<<9)
70#define MSR_PVR (1<<10)
71#define MSR_CC (1<<31)
72
73
74#define MSR_UM (1<<11)
75#define MSR_UMS (1<<12)
76#define MSR_VM (1<<13)
77#define MSR_VMS (1<<14)
78
79#define MSR_KERNEL MSR_EE|MSR_VM
80
81#define MSR_KERNEL_VMS MSR_EE|MSR_VMS
82
83
84
85#define ESR_DIZ (1<<11)
86#define ESR_S (1<<10)
87
88#define ESR_ESS_FSL_OFFSET 5
89
90#define ESR_EC_FSL 0
91#define ESR_EC_UNALIGNED_DATA 1
92#define ESR_EC_ILLEGAL_OP 2
93#define ESR_EC_INSN_BUS 3
94#define ESR_EC_DATA_BUS 4
95#define ESR_EC_DIVZERO 5
96#define ESR_EC_FPU 6
97#define ESR_EC_PRIVINSN 7
98#define ESR_EC_STACKPROT 7
99#define ESR_EC_DATA_STORAGE 8
100#define ESR_EC_INSN_STORAGE 9
101#define ESR_EC_DATA_TLB 10
102#define ESR_EC_INSN_TLB 11
103#define ESR_EC_MASK 31
104
105
106#define FSR_IO (1<<4)
107#define FSR_DZ (1<<3)
108#define FSR_OF (1<<2)
109#define FSR_UF (1<<1)
110#define FSR_DO (1<<0)
111
112
113
114#define PVR0_PVR_FULL_MASK 0x80000000
115#define PVR0_USE_BARREL_MASK 0x40000000
116#define PVR0_USE_DIV_MASK 0x20000000
117#define PVR0_USE_HW_MUL_MASK 0x10000000
118#define PVR0_USE_FPU_MASK 0x08000000
119#define PVR0_USE_EXC_MASK 0x04000000
120#define PVR0_USE_ICACHE_MASK 0x02000000
121#define PVR0_USE_DCACHE_MASK 0x01000000
122#define PVR0_USE_MMU_MASK 0x00800000
123#define PVR0_USE_BTC 0x00400000
124#define PVR0_ENDI_MASK 0x00200000
125#define PVR0_FAULT 0x00100000
126#define PVR0_VERSION_MASK 0x0000FF00
127#define PVR0_USER1_MASK 0x000000FF
128#define PVR0_SPROT_MASK 0x00000001
129
130
131#define PVR1_USER2_MASK 0xFFFFFFFF
132
133
134#define PVR2_D_OPB_MASK 0x80000000
135#define PVR2_D_LMB_MASK 0x40000000
136#define PVR2_I_OPB_MASK 0x20000000
137#define PVR2_I_LMB_MASK 0x10000000
138#define PVR2_INTERRUPT_IS_EDGE_MASK 0x08000000
139#define PVR2_EDGE_IS_POSITIVE_MASK 0x04000000
140#define PVR2_D_PLB_MASK 0x02000000
141#define PVR2_I_PLB_MASK 0x01000000
142#define PVR2_INTERCONNECT 0x00800000
143#define PVR2_USE_EXTEND_FSL 0x00080000
144#define PVR2_USE_FSL_EXC 0x00040000
145#define PVR2_USE_MSR_INSTR 0x00020000
146#define PVR2_USE_PCMP_INSTR 0x00010000
147#define PVR2_AREA_OPTIMISED 0x00008000
148#define PVR2_USE_BARREL_MASK 0x00004000
149#define PVR2_USE_DIV_MASK 0x00002000
150#define PVR2_USE_HW_MUL_MASK 0x00001000
151#define PVR2_USE_FPU_MASK 0x00000800
152#define PVR2_USE_MUL64_MASK 0x00000400
153#define PVR2_USE_FPU2_MASK 0x00000200
154#define PVR2_USE_IPLBEXC 0x00000100
155#define PVR2_USE_DPLBEXC 0x00000080
156#define PVR2_OPCODE_0x0_ILL_MASK 0x00000040
157#define PVR2_UNALIGNED_EXC_MASK 0x00000020
158#define PVR2_ILL_OPCODE_EXC_MASK 0x00000010
159#define PVR2_IOPB_BUS_EXC_MASK 0x00000008
160#define PVR2_DOPB_BUS_EXC_MASK 0x00000004
161#define PVR2_DIV_ZERO_EXC_MASK 0x00000002
162#define PVR2_FPU_EXC_MASK 0x00000001
163
164
165#define PVR3_DEBUG_ENABLED_MASK 0x80000000
166#define PVR3_NUMBER_OF_PC_BRK_MASK 0x1E000000
167#define PVR3_NUMBER_OF_RD_ADDR_BRK_MASK 0x00380000
168#define PVR3_NUMBER_OF_WR_ADDR_BRK_MASK 0x0000E000
169#define PVR3_FSL_LINKS_MASK 0x00000380
170
171
172#define PVR4_USE_ICACHE_MASK 0x80000000
173#define PVR4_ICACHE_ADDR_TAG_BITS_MASK 0x7C000000
174#define PVR4_ICACHE_USE_FSL_MASK 0x02000000
175#define PVR4_ICACHE_ALLOW_WR_MASK 0x01000000
176#define PVR4_ICACHE_LINE_LEN_MASK 0x00E00000
177#define PVR4_ICACHE_BYTE_SIZE_MASK 0x001F0000
178
179
180#define PVR5_USE_DCACHE_MASK 0x80000000
181#define PVR5_DCACHE_ADDR_TAG_BITS_MASK 0x7C000000
182#define PVR5_DCACHE_USE_FSL_MASK 0x02000000
183#define PVR5_DCACHE_ALLOW_WR_MASK 0x01000000
184#define PVR5_DCACHE_LINE_LEN_MASK 0x00E00000
185#define PVR5_DCACHE_BYTE_SIZE_MASK 0x001F0000
186#define PVR5_DCACHE_WRITEBACK_MASK 0x00004000
187
188
189#define PVR6_ICACHE_BASEADDR_MASK 0xFFFFFFFF
190
191
192#define PVR7_ICACHE_HIGHADDR_MASK 0xFFFFFFFF
193
194
195#define PVR8_DCACHE_BASEADDR_MASK 0xFFFFFFFF
196
197
198#define PVR9_DCACHE_HIGHADDR_MASK 0xFFFFFFFF
199
200
201#define PVR10_TARGET_FAMILY_MASK 0xFF000000
202
203
204#define PVR11_USE_MMU 0xC0000000
205#define PVR11_MMU_ITLB_SIZE 0x38000000
206#define PVR11_MMU_DTLB_SIZE 0x07000000
207#define PVR11_MMU_TLB_ACCESS 0x00C00000
208#define PVR11_MMU_ZONES 0x003E0000
209
210#define PVR11_MSR_RESET_VALUE_MASK 0x000007FF
211
212#define C_PVR_NONE 0
213#define C_PVR_BASIC 1
214#define C_PVR_FULL 2
215
216
217
218
219#define CC_GE 5
220#define CC_GT 4
221#define CC_LE 3
222#define CC_LT 2
223#define CC_NE 1
224#define CC_EQ 0
225
226#define NB_MMU_MODES 3
227#undef NB_MEM_ATTR
228#define NB_MEM_ATTR 1
229
230#define STREAM_EXCEPTION (1 << 0)
231#define STREAM_ATOMIC (1 << 1)
232#define STREAM_TEST (1 << 2)
233#define STREAM_CONTROL (1 << 3)
234#define STREAM_NONBLOCK (1 << 4)
235
236struct CPUMBState {
237 uint32_t debug;
238 uint32_t btaken;
239 uint32_t btarget;
240 uint32_t bimm;
241
242 uint32_t imm;
243 uint32_t regs[33];
244 uint32_t sregs[24];
245 float_status fp_status;
246
247 uint32_t slr, shr;
248
249
250#define RES_ADDR_NONE 0xffffffff
251 uint32_t res_addr;
252 uint32_t res_val;
253
254
255#define IMM_FLAG 4
256#define MSR_EE_FLAG (1 << 8)
257#define DRTI_FLAG (1 << 16)
258#define DRTE_FLAG (1 << 17)
259#define DRTB_FLAG (1 << 18)
260#define D_FLAG (1 << 19)
261
262#define IFLAGS_TB_MASK (D_FLAG | IMM_FLAG | DRTI_FLAG | DRTE_FLAG | DRTB_FLAG)
263 uint32_t iflags;
264 uint32_t wakeup;
265
266#if !defined(CONFIG_USER_ONLY)
267
268 struct microblaze_mmu mmu;
269#endif
270
271 CPU_COMMON
272
273
274
275 struct {
276 uint32_t regs[16];
277 } pvr;
278
279
280
281 MemTxAttrs *memattr_p;
282};
283
284#include "cpu-qom.h"
285
286void mb_tcg_init(void);
287MicroBlazeCPU *cpu_mb_init(const char *cpu_model);
288int cpu_mb_exec(CPUState *cpu);
289
290
291
292int cpu_mb_signal_handler(int host_signum, void *pinfo,
293 void *puc);
294
295
296#define TARGET_PAGE_BITS 12
297
298#define TARGET_PHYS_ADDR_SPACE_BITS 32
299#define TARGET_VIRT_ADDR_SPACE_BITS 32
300
301#define cpu_init(cpu_model) CPU(cpu_mb_init(cpu_model))
302
303#define cpu_exec cpu_mb_exec
304#define cpu_signal_handler cpu_mb_signal_handler
305
306
307#define MMU_MODE0_SUFFIX _nommu
308#define MMU_MODE1_SUFFIX _kernel
309#define MMU_MODE2_SUFFIX _user
310#define MMU_NOMMU_IDX 0
311#define MMU_KERNEL_IDX 1
312#define MMU_USER_IDX 2
313
314
315static inline int cpu_mmu_index (CPUMBState *env, bool ifetch)
316{
317
318 if (!(env->sregs[SR_MSR] & MSR_VM))
319 return MMU_NOMMU_IDX;
320
321 if (env->sregs[SR_MSR] & MSR_UM)
322 return MMU_USER_IDX;
323 return MMU_KERNEL_IDX;
324}
325
326int mb_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
327 int mmu_idx);
328
329#include "exec/cpu-all.h"
330
331static inline void cpu_get_tb_cpu_state(CPUMBState *env, target_ulong *pc,
332 target_ulong *cs_base, int *flags)
333{
334 *pc = env->sregs[SR_PC];
335 *cs_base = 0;
336 *flags = (env->iflags & IFLAGS_TB_MASK) |
337 (env->sregs[SR_MSR] & (MSR_UM | MSR_VM | MSR_EE));
338}
339
340#if !defined(CONFIG_USER_ONLY)
341void mb_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
342 bool is_write, bool is_exec, int is_asi,
343 unsigned size);
344#endif
345
346#include "exec/exec-all.h"
347
348#endif
349