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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "exec/helper-proto.h"
24#include "qemu/host-utils.h"
25#include "exec/exec-all.h"
26#include "exec/cpu_ldst.h"
27#include "hw/remote-port.h"
28
29#define D(x)
30
31#if !defined(CONFIG_USER_ONLY)
32
33
34
35
36
37void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
38 uintptr_t retaddr)
39{
40 int ret;
41
42 ret = mb_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
43 if (unlikely(ret)) {
44 if (retaddr) {
45
46 cpu_restore_state(cs, retaddr);
47 }
48 cpu_loop_exit(cs);
49 }
50}
51#endif
52
53void helper_put(uint32_t id, uint32_t ctrl, uint32_t data)
54{
55 int test = ctrl & STREAM_TEST;
56 int atomic = ctrl & STREAM_ATOMIC;
57 int control = ctrl & STREAM_CONTROL;
58 int nonblock = ctrl & STREAM_NONBLOCK;
59 int exception = ctrl & STREAM_EXCEPTION;
60
61 qemu_log_mask(LOG_UNIMP, "Unhandled stream put to stream-id=%d data=%x %s%s%s%s%s\n",
62 id, data,
63 test ? "t" : "",
64 nonblock ? "n" : "",
65 exception ? "e" : "",
66 control ? "c" : "",
67 atomic ? "a" : "");
68}
69
70uint32_t helper_get(uint32_t id, uint32_t ctrl)
71{
72 int test = ctrl & STREAM_TEST;
73 int atomic = ctrl & STREAM_ATOMIC;
74 int control = ctrl & STREAM_CONTROL;
75 int nonblock = ctrl & STREAM_NONBLOCK;
76 int exception = ctrl & STREAM_EXCEPTION;
77
78 qemu_log_mask(LOG_UNIMP, "Unhandled stream get from stream-id=%d %s%s%s%s%s\n",
79 id,
80 test ? "t" : "",
81 nonblock ? "n" : "",
82 exception ? "e" : "",
83 control ? "c" : "",
84 atomic ? "a" : "");
85 return 0xdead0000 | id;
86}
87
88void helper_raise_exception(CPUMBState *env, uint32_t index)
89{
90 CPUState *cs = CPU(mb_env_get_cpu(env));
91
92 cs->exception_index = index;
93 cpu_loop_exit(cs);
94}
95
96void helper_sleep(CPUMBState *env)
97{
98 MicroBlazeCPU *cpu = mb_env_get_cpu(env);
99 CPUState *cs = CPU(cpu);
100 CPUClass *cc = CPU_GET_CLASS(cs);
101
102 if (cc->has_work(cs)) {
103 cs->exception_index = EXCP_YIELD;
104 cpu_loop_exit(cs);
105 return;
106 }
107
108#if !defined(CONFIG_USER_ONLY)
109 qemu_set_irq(cpu->mb_sleep, true);
110#endif
111 cs->exception_index = EXCP_HLT;
112 cs->halted = 1;
113 cpu_loop_exit(cs);
114}
115
116void helper_debug(CPUMBState *env)
117{
118 int i;
119
120 qemu_log("PC=%8.8x\n", env->sregs[SR_PC]);
121 qemu_log("rmsr=%x resr=%x rear=%x debug[%x] imm=%x iflags=%x\n",
122 env->sregs[SR_MSR], env->sregs[SR_ESR], env->sregs[SR_EAR],
123 env->debug, env->imm, env->iflags);
124 qemu_log("btaken=%d btarget=%x mode=%s(saved=%s) eip=%d ie=%d\n",
125 env->btaken, env->btarget,
126 (env->sregs[SR_MSR] & MSR_UM) ? "user" : "kernel",
127 (env->sregs[SR_MSR] & MSR_UMS) ? "user" : "kernel",
128 (env->sregs[SR_MSR] & MSR_EIP),
129 (env->sregs[SR_MSR] & MSR_IE));
130 for (i = 0; i < 32; i++) {
131 qemu_log("r%2.2d=%8.8x ", i, env->regs[i]);
132 if ((i + 1) % 4 == 0)
133 qemu_log("\n");
134 }
135 qemu_log("\n\n");
136}
137
138static inline uint32_t compute_carry(uint32_t a, uint32_t b, uint32_t cin)
139{
140 uint32_t cout = 0;
141
142 if ((b == ~0) && cin)
143 cout = 1;
144 else if ((~0 - a) < (b + cin))
145 cout = 1;
146 return cout;
147}
148
149uint32_t helper_cmp(uint32_t a, uint32_t b)
150{
151 uint32_t t;
152
153 t = b + ~a + 1;
154 if ((b & 0x80000000) ^ (a & 0x80000000))
155 t = (t & 0x7fffffff) | (b & 0x80000000);
156 return t;
157}
158
159uint32_t helper_cmpu(uint32_t a, uint32_t b)
160{
161 uint32_t t;
162
163 t = b + ~a + 1;
164 if ((b & 0x80000000) ^ (a & 0x80000000))
165 t = (t & 0x7fffffff) | (a & 0x80000000);
166 return t;
167}
168
169uint32_t helper_clz(uint32_t t0)
170{
171 return clz32(t0);
172}
173
174uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf)
175{
176 return compute_carry(a, b, cf);
177}
178
179static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b)
180{
181 if (b == 0) {
182 env->sregs[SR_MSR] |= MSR_DZ;
183
184 if ((env->sregs[SR_MSR] & MSR_EE)
185 && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) {
186 env->sregs[SR_ESR] = ESR_EC_DIVZERO;
187 helper_raise_exception(env, EXCP_HW_EXCP);
188 }
189 return 0;
190 }
191 env->sregs[SR_MSR] &= ~MSR_DZ;
192 return 1;
193}
194
195uint32_t helper_divs(CPUMBState *env, uint32_t a, uint32_t b)
196{
197 if (!div_prepare(env, a, b)) {
198 return 0;
199 }
200 return (int32_t)a / (int32_t)b;
201}
202
203uint32_t helper_divu(CPUMBState *env, uint32_t a, uint32_t b)
204{
205 if (!div_prepare(env, a, b)) {
206 return 0;
207 }
208 return a / b;
209}
210
211
212static void raise_fpu_exception(CPUMBState *env)
213{
214 env->sregs[SR_ESR] = ESR_EC_FPU;
215 helper_raise_exception(env, EXCP_HW_EXCP);
216}
217
218static void update_fpu_flags(CPUMBState *env, int flags)
219{
220 int raise = 0;
221
222 if (flags & float_flag_invalid) {
223 env->sregs[SR_FSR] |= FSR_IO;
224 raise = 1;
225 }
226 if (flags & float_flag_divbyzero) {
227 env->sregs[SR_FSR] |= FSR_DZ;
228 raise = 1;
229 }
230 if (flags & float_flag_overflow) {
231 env->sregs[SR_FSR] |= FSR_OF;
232 raise = 1;
233 }
234 if (flags & float_flag_underflow) {
235 env->sregs[SR_FSR] |= FSR_UF;
236 raise = 1;
237 }
238 if (raise
239 && (env->pvr.regs[2] & PVR2_FPU_EXC_MASK)
240 && (env->sregs[SR_MSR] & MSR_EE)) {
241 raise_fpu_exception(env);
242 }
243}
244
245uint32_t helper_fadd(CPUMBState *env, uint32_t a, uint32_t b)
246{
247 CPU_FloatU fd, fa, fb;
248 int flags;
249
250 set_float_exception_flags(0, &env->fp_status);
251 fa.l = a;
252 fb.l = b;
253 fd.f = float32_add(fa.f, fb.f, &env->fp_status);
254
255 flags = get_float_exception_flags(&env->fp_status);
256 update_fpu_flags(env, flags);
257 return fd.l;
258}
259
260uint32_t helper_frsub(CPUMBState *env, uint32_t a, uint32_t b)
261{
262 CPU_FloatU fd, fa, fb;
263 int flags;
264
265 set_float_exception_flags(0, &env->fp_status);
266 fa.l = a;
267 fb.l = b;
268 fd.f = float32_sub(fb.f, fa.f, &env->fp_status);
269 flags = get_float_exception_flags(&env->fp_status);
270 update_fpu_flags(env, flags);
271 return fd.l;
272}
273
274uint32_t helper_fmul(CPUMBState *env, uint32_t a, uint32_t b)
275{
276 CPU_FloatU fd, fa, fb;
277 int flags;
278
279 set_float_exception_flags(0, &env->fp_status);
280 fa.l = a;
281 fb.l = b;
282 fd.f = float32_mul(fa.f, fb.f, &env->fp_status);
283 flags = get_float_exception_flags(&env->fp_status);
284 update_fpu_flags(env, flags);
285
286 return fd.l;
287}
288
289uint32_t helper_fdiv(CPUMBState *env, uint32_t a, uint32_t b)
290{
291 CPU_FloatU fd, fa, fb;
292 int flags;
293
294 set_float_exception_flags(0, &env->fp_status);
295 fa.l = a;
296 fb.l = b;
297 fd.f = float32_div(fb.f, fa.f, &env->fp_status);
298 flags = get_float_exception_flags(&env->fp_status);
299 update_fpu_flags(env, flags);
300
301 return fd.l;
302}
303
304uint32_t helper_fcmp_un(CPUMBState *env, uint32_t a, uint32_t b)
305{
306 CPU_FloatU fa, fb;
307 uint32_t r = 0;
308
309 fa.l = a;
310 fb.l = b;
311
312 if (float32_is_signaling_nan(fa.f) || float32_is_signaling_nan(fb.f)) {
313 update_fpu_flags(env, float_flag_invalid);
314 r = 1;
315 }
316
317 if (float32_is_quiet_nan(fa.f) || float32_is_quiet_nan(fb.f)) {
318 r = 1;
319 }
320
321 return r;
322}
323
324uint32_t helper_fcmp_lt(CPUMBState *env, uint32_t a, uint32_t b)
325{
326 CPU_FloatU fa, fb;
327 int r;
328 int flags;
329
330 set_float_exception_flags(0, &env->fp_status);
331 fa.l = a;
332 fb.l = b;
333 r = float32_lt(fb.f, fa.f, &env->fp_status);
334 flags = get_float_exception_flags(&env->fp_status);
335 update_fpu_flags(env, flags & float_flag_invalid);
336
337 return r;
338}
339
340uint32_t helper_fcmp_eq(CPUMBState *env, uint32_t a, uint32_t b)
341{
342 CPU_FloatU fa, fb;
343 int flags;
344 int r;
345
346 set_float_exception_flags(0, &env->fp_status);
347 fa.l = a;
348 fb.l = b;
349 r = float32_eq_quiet(fa.f, fb.f, &env->fp_status);
350 flags = get_float_exception_flags(&env->fp_status);
351 update_fpu_flags(env, flags & float_flag_invalid);
352
353 return r;
354}
355
356uint32_t helper_fcmp_le(CPUMBState *env, uint32_t a, uint32_t b)
357{
358 CPU_FloatU fa, fb;
359 int flags;
360 int r;
361
362 fa.l = a;
363 fb.l = b;
364 set_float_exception_flags(0, &env->fp_status);
365 r = float32_le(fa.f, fb.f, &env->fp_status);
366 flags = get_float_exception_flags(&env->fp_status);
367 update_fpu_flags(env, flags & float_flag_invalid);
368
369
370 return r;
371}
372
373uint32_t helper_fcmp_gt(CPUMBState *env, uint32_t a, uint32_t b)
374{
375 CPU_FloatU fa, fb;
376 int flags, r;
377
378 fa.l = a;
379 fb.l = b;
380 set_float_exception_flags(0, &env->fp_status);
381 r = float32_lt(fa.f, fb.f, &env->fp_status);
382 flags = get_float_exception_flags(&env->fp_status);
383 update_fpu_flags(env, flags & float_flag_invalid);
384 return r;
385}
386
387uint32_t helper_fcmp_ne(CPUMBState *env, uint32_t a, uint32_t b)
388{
389 CPU_FloatU fa, fb;
390 int flags, r;
391
392 fa.l = a;
393 fb.l = b;
394 set_float_exception_flags(0, &env->fp_status);
395 r = !float32_eq_quiet(fa.f, fb.f, &env->fp_status);
396 flags = get_float_exception_flags(&env->fp_status);
397 update_fpu_flags(env, flags & float_flag_invalid);
398
399 return r;
400}
401
402uint32_t helper_fcmp_ge(CPUMBState *env, uint32_t a, uint32_t b)
403{
404 CPU_FloatU fa, fb;
405 int flags, r;
406
407 fa.l = a;
408 fb.l = b;
409 set_float_exception_flags(0, &env->fp_status);
410 r = !float32_lt(fa.f, fb.f, &env->fp_status);
411 flags = get_float_exception_flags(&env->fp_status);
412 update_fpu_flags(env, flags & float_flag_invalid);
413
414 return r;
415}
416
417uint32_t helper_flt(CPUMBState *env, uint32_t a)
418{
419 CPU_FloatU fd, fa;
420
421 fa.l = a;
422 fd.f = int32_to_float32(fa.l, &env->fp_status);
423 return fd.l;
424}
425
426uint32_t helper_fint(CPUMBState *env, uint32_t a)
427{
428 CPU_FloatU fa;
429 uint32_t r;
430 int flags;
431
432 set_float_exception_flags(0, &env->fp_status);
433 fa.l = a;
434 r = float32_to_int32(fa.f, &env->fp_status);
435 flags = get_float_exception_flags(&env->fp_status);
436 update_fpu_flags(env, flags);
437
438 return r;
439}
440
441uint32_t helper_fsqrt(CPUMBState *env, uint32_t a)
442{
443 CPU_FloatU fd, fa;
444 int flags;
445
446 set_float_exception_flags(0, &env->fp_status);
447 fa.l = a;
448 fd.l = float32_sqrt(fa.f, &env->fp_status);
449 flags = get_float_exception_flags(&env->fp_status);
450 update_fpu_flags(env, flags);
451
452 return fd.l;
453}
454
455uint32_t helper_pcmpbf(uint32_t a, uint32_t b)
456{
457 unsigned int i;
458 uint32_t mask = 0xff000000;
459
460 for (i = 0; i < 4; i++) {
461 if ((a & mask) == (b & mask))
462 return i + 1;
463 mask >>= 8;
464 }
465 return 0;
466}
467
468void helper_memalign(CPUMBState *env, uint32_t addr, uint32_t dr, uint32_t wr,
469 uint32_t mask)
470{
471 if (addr & mask) {
472 qemu_log_mask(CPU_LOG_INT,
473 "unaligned access addr=%x mask=%x, wr=%d dr=r%d\n",
474 addr, mask, wr, dr);
475 env->sregs[SR_EAR] = addr;
476 env->sregs[SR_ESR] = ESR_EC_UNALIGNED_DATA | (wr << 10) \
477 | (dr & 31) << 5;
478 if (mask == 3) {
479 env->sregs[SR_ESR] |= 1 << 11;
480 }
481 if (!(env->sregs[SR_MSR] & MSR_EE)) {
482 return;
483 }
484 helper_raise_exception(env, EXCP_HW_EXCP);
485 }
486}
487
488void helper_stackprot(CPUMBState *env, uint32_t addr)
489{
490 if (addr < env->slr || addr > env->shr) {
491 qemu_log_mask(CPU_LOG_INT, "Stack protector violation at %x %x %x\n",
492 addr, env->slr, env->shr);
493 env->sregs[SR_EAR] = addr;
494 env->sregs[SR_ESR] = ESR_EC_STACKPROT;
495 helper_raise_exception(env, EXCP_HW_EXCP);
496 }
497}
498
499#if !defined(CONFIG_USER_ONLY)
500
501uint32_t helper_mmu_read(CPUMBState *env, uint32_t rn)
502{
503 return mmu_read(env, rn);
504}
505
506void helper_mmu_write(CPUMBState *env, uint32_t rn, uint32_t v)
507{
508 mmu_write(env, rn, v);
509}
510
511void mb_cpu_unassigned_access(CPUState *cs, hwaddr addr,
512 bool is_write, bool is_exec, int is_asi,
513 unsigned size)
514{
515 MicroBlazeCPU *cpu;
516 CPUMBState *env;
517
518 qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
519 addr, is_write ? 1 : 0, is_exec ? 1 : 0);
520 if (cs == NULL) {
521 return;
522 }
523 cpu = MICROBLAZE_CPU(cs);
524 env = &cpu->env;
525 if (!(env->sregs[SR_MSR] & MSR_EE)) {
526 return;
527 }
528
529 env->sregs[SR_EAR] = addr;
530 if (is_exec) {
531 if ((env->pvr.regs[2] & PVR2_IOPB_BUS_EXC_MASK)) {
532 env->sregs[SR_ESR] = ESR_EC_INSN_BUS;
533 helper_raise_exception(env, EXCP_HW_EXCP);
534 }
535 } else {
536 if ((env->pvr.regs[2] & PVR2_DOPB_BUS_EXC_MASK)) {
537 env->sregs[SR_ESR] = ESR_EC_DATA_BUS;
538 helper_raise_exception(env, EXCP_HW_EXCP);
539 }
540 }
541}
542#endif
543
