LXR qemu/target-mips/cpu-qom.h

   1/*
   2 * QEMU MIPS CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20#ifndef QEMU_MIPS_CPU_QOM_H
  21#define QEMU_MIPS_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24
  25#ifdef TARGET_MIPS64
  26#define TYPE_MIPS_CPU "mips64-cpu"
  27#else
  28#define TYPE_MIPS_CPU "mips-cpu"
  29#endif
  30
  31#define MIPS_CPU_CLASS(klass) \
  32    OBJECT_CLASS_CHECK(MIPSCPUClass, (klass), TYPE_MIPS_CPU)
  33#define MIPS_CPU(obj) \
  34    OBJECT_CHECK(MIPSCPU, (obj), TYPE_MIPS_CPU)
  35#define MIPS_CPU_GET_CLASS(obj) \
  36    OBJECT_GET_CLASS(MIPSCPUClass, (obj), TYPE_MIPS_CPU)
  37
  38/**
  39 * MIPSCPUClass:
  40 * @parent_realize: The parent class' realize handler.
  41 * @parent_reset: The parent class' reset handler.
  42 *
  43 * A MIPS CPU model.
  44 */
  45typedef struct MIPSCPUClass {
  46    /*< private >*/
  47    CPUClass parent_class;
  48    /*< public >*/
  49
  50    DeviceRealize parent_realize;
  51    void (*parent_reset)(CPUState *cpu);
  52} MIPSCPUClass;
  53
  54/**
  55 * MIPSCPU:
  56 * @env: #CPUMIPSState
  57 *
  58 * A MIPS CPU.
  59 */
  60typedef struct MIPSCPU {
  61    /*< private >*/
  62    CPUState parent_obj;
  63    /*< public >*/
  64
  65    CPUMIPSState env;
  66} MIPSCPU;
  67
  68static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env)
  69{
  70    return container_of(env, MIPSCPU, env);
  71}
  72
  73#define ENV_GET_CPU(e) CPU(mips_env_get_cpu(e))
  74
  75#define ENV_OFFSET offsetof(MIPSCPU, env)
  76
  77#ifndef CONFIG_USER_ONLY
  78extern const struct VMStateDescription vmstate_mips_cpu;
  79#endif
  80
  81void mips_cpu_do_interrupt(CPUState *cpu);
  82bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req);
  83void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
  84                         int flags);
  85hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
  86int mips_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
  87int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
  88void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr,
  89                                  int is_write, int is_user, uintptr_t retaddr);
  90
  91#endif
  92