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21#include "qemu/osdep.h"
22#include "cpu.h"
23#include "exec/helper-proto.h"
24
25#define TO_SPR(group, number) (((group) << 11) + (number))
26
27void HELPER(mtspr)(CPUOpenRISCState *env,
28 target_ulong ra, target_ulong rb, target_ulong offset)
29{
30#ifndef CONFIG_USER_ONLY
31 int spr = (ra | offset);
32 int idx;
33
34 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
35 CPUState *cs = CPU(cpu);
36
37 switch (spr) {
38 case TO_SPR(0, 0):
39 env->vr = rb;
40 break;
41
42 case TO_SPR(0, 16):
43 env->npc = rb;
44 break;
45
46 case TO_SPR(0, 17):
47 if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
48 (rb & (SR_IME | SR_DME | SR_SM))) {
49 tlb_flush(cs, 1);
50 }
51 env->sr = rb;
52 env->sr |= SR_FO;
53 if (env->sr & SR_DME) {
54 env->tlb->cpu_openrisc_map_address_data =
55 &cpu_openrisc_get_phys_data;
56 } else {
57 env->tlb->cpu_openrisc_map_address_data =
58 &cpu_openrisc_get_phys_nommu;
59 }
60
61 if (env->sr & SR_IME) {
62 env->tlb->cpu_openrisc_map_address_code =
63 &cpu_openrisc_get_phys_code;
64 } else {
65 env->tlb->cpu_openrisc_map_address_code =
66 &cpu_openrisc_get_phys_nommu;
67 }
68 break;
69
70 case TO_SPR(0, 18):
71 env->ppc = rb;
72 break;
73
74 case TO_SPR(0, 32):
75 env->epcr = rb;
76 break;
77
78 case TO_SPR(0, 48):
79 env->eear = rb;
80 break;
81
82 case TO_SPR(0, 64):
83 env->esr = rb;
84 break;
85 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1):
86 idx = spr - TO_SPR(1, 512);
87 if (!(rb & 1)) {
88 tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
89 }
90 env->tlb->dtlb[0][idx].mr = rb;
91 break;
92
93 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1):
94 idx = spr - TO_SPR(1, 640);
95 env->tlb->dtlb[0][idx].tr = rb;
96 break;
97 case TO_SPR(1, 768) ... TO_SPR(1, 895):
98 case TO_SPR(1, 896) ... TO_SPR(1, 1023):
99 case TO_SPR(1, 1024) ... TO_SPR(1, 1151):
100 case TO_SPR(1, 1152) ... TO_SPR(1, 1279):
101 case TO_SPR(1, 1280) ... TO_SPR(1, 1407):
102 case TO_SPR(1, 1408) ... TO_SPR(1, 1535):
103 break;
104 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):
105 idx = spr - TO_SPR(2, 512);
106 if (!(rb & 1)) {
107 tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
108 }
109 env->tlb->itlb[0][idx].mr = rb;
110 break;
111
112 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1):
113 idx = spr - TO_SPR(2, 640);
114 env->tlb->itlb[0][idx].tr = rb;
115 break;
116 case TO_SPR(2, 768) ... TO_SPR(2, 895):
117 case TO_SPR(2, 896) ... TO_SPR(2, 1023):
118 case TO_SPR(2, 1024) ... TO_SPR(2, 1151):
119 case TO_SPR(2, 1152) ... TO_SPR(2, 1279):
120 case TO_SPR(2, 1280) ... TO_SPR(2, 1407):
121 case TO_SPR(2, 1408) ... TO_SPR(2, 1535):
122 break;
123 case TO_SPR(9, 0):
124 env->picmr |= rb;
125 break;
126 case TO_SPR(9, 2):
127 env->picsr &= ~rb;
128 break;
129 case TO_SPR(10, 0):
130 {
131 if ((env->ttmr & TTMR_M) ^ (rb & TTMR_M)) {
132 switch (rb & TTMR_M) {
133 case TIMER_NONE:
134 cpu_openrisc_count_stop(cpu);
135 break;
136 case TIMER_INTR:
137 case TIMER_SHOT:
138 case TIMER_CONT:
139 cpu_openrisc_count_start(cpu);
140 break;
141 default:
142 break;
143 }
144 }
145
146 int ip = env->ttmr & TTMR_IP;
147
148 if (rb & TTMR_IP) {
149 env->ttmr = (rb & ~TTMR_IP) | ip;
150 } else {
151 env->ttmr = rb & ~TTMR_IP;
152 cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
153 }
154
155 cpu_openrisc_timer_update(cpu);
156 }
157 break;
158
159 case TO_SPR(10, 1):
160 env->ttcr = rb;
161 if (env->ttmr & TIMER_NONE) {
162 return;
163 }
164 cpu_openrisc_timer_update(cpu);
165 break;
166 default:
167
168 break;
169 }
170#endif
171}
172
173target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
174 target_ulong rd, target_ulong ra, uint32_t offset)
175{
176#ifndef CONFIG_USER_ONLY
177 int spr = (ra | offset);
178 int idx;
179
180 OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
181
182 switch (spr) {
183 case TO_SPR(0, 0):
184 return env->vr & SPR_VR;
185
186 case TO_SPR(0, 1):
187 return env->upr;
188
189 case TO_SPR(0, 2):
190 return env->cpucfgr;
191
192 case TO_SPR(0, 3):
193 return env->dmmucfgr;
194
195 case TO_SPR(0, 4):
196 return env->immucfgr;
197
198 case TO_SPR(0, 16):
199 return env->npc;
200
201 case TO_SPR(0, 17):
202 return env->sr;
203
204 case TO_SPR(0, 18):
205 return env->ppc;
206
207 case TO_SPR(0, 32):
208 return env->epcr;
209
210 case TO_SPR(0, 48):
211 return env->eear;
212
213 case TO_SPR(0, 64):
214 return env->esr;
215
216 case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1):
217 idx = spr - TO_SPR(1, 512);
218 return env->tlb->dtlb[0][idx].mr;
219
220 case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1):
221 idx = spr - TO_SPR(1, 640);
222 return env->tlb->dtlb[0][idx].tr;
223
224 case TO_SPR(1, 768) ... TO_SPR(1, 895):
225 case TO_SPR(1, 896) ... TO_SPR(1, 1023):
226 case TO_SPR(1, 1024) ... TO_SPR(1, 1151):
227 case TO_SPR(1, 1152) ... TO_SPR(1, 1279):
228 case TO_SPR(1, 1280) ... TO_SPR(1, 1407):
229 case TO_SPR(1, 1408) ... TO_SPR(1, 1535):
230 break;
231
232 case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1):
233 idx = spr - TO_SPR(2, 512);
234 return env->tlb->itlb[0][idx].mr;
235
236 case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1):
237 idx = spr - TO_SPR(2, 640);
238 return env->tlb->itlb[0][idx].tr;
239
240 case TO_SPR(2, 768) ... TO_SPR(2, 895):
241 case TO_SPR(2, 896) ... TO_SPR(2, 1023):
242 case TO_SPR(2, 1024) ... TO_SPR(2, 1151):
243 case TO_SPR(2, 1152) ... TO_SPR(2, 1279):
244 case TO_SPR(2, 1280) ... TO_SPR(2, 1407):
245 case TO_SPR(2, 1408) ... TO_SPR(2, 1535):
246 break;
247
248 case TO_SPR(9, 0):
249 return env->picmr;
250
251 case TO_SPR(9, 2):
252 return env->picsr;
253
254 case TO_SPR(10, 0):
255 return env->ttmr;
256
257 case TO_SPR(10, 1):
258 cpu_openrisc_count_update(cpu);
259 return env->ttcr;
260
261 default:
262 break;
263 }
264#endif
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286 return rd;
287}
288