LXR qemu/target-ppc/cpu-qom.h

   1/*
   2 * QEMU PowerPC CPU
   3 *
   4 * Copyright (c) 2012 SUSE LINUX Products GmbH
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2.1 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see
  18 * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19 */
  20#ifndef QEMU_PPC_CPU_QOM_H
  21#define QEMU_PPC_CPU_QOM_H
  22
  23#include "qom/cpu.h"
  24#include "cpu.h"
  25
  26#ifdef TARGET_PPC64
  27#define TYPE_POWERPC_CPU "powerpc64-cpu"
  28#elif defined(TARGET_PPCEMB)
  29#define TYPE_POWERPC_CPU "embedded-powerpc-cpu"
  30#else
  31#define TYPE_POWERPC_CPU "powerpc-cpu"
  32#endif
  33
  34#define POWERPC_CPU_CLASS(klass) \
  35    OBJECT_CLASS_CHECK(PowerPCCPUClass, (klass), TYPE_POWERPC_CPU)
  36#define POWERPC_CPU(obj) \
  37    OBJECT_CHECK(PowerPCCPU, (obj), TYPE_POWERPC_CPU)
  38#define POWERPC_CPU_GET_CLASS(obj) \
  39    OBJECT_GET_CLASS(PowerPCCPUClass, (obj), TYPE_POWERPC_CPU)
  40
  41typedef struct PowerPCCPU PowerPCCPU;
  42
  43/**
  44 * PowerPCCPUClass:
  45 * @parent_realize: The parent class' realize handler.
  46 * @parent_reset: The parent class' reset handler.
  47 *
  48 * A PowerPC CPU model.
  49 */
  50typedef struct PowerPCCPUClass {
  51    /*< private >*/
  52    CPUClass parent_class;
  53    /*< public >*/
  54
  55    DeviceRealize parent_realize;
  56    void (*parent_reset)(CPUState *cpu);
  57
  58    uint32_t pvr;
  59    bool (*pvr_match)(struct PowerPCCPUClass *pcc, uint32_t pvr);
  60    uint64_t pcr_mask;
  61    uint32_t svr;
  62    uint64_t insns_flags;
  63    uint64_t insns_flags2;
  64    uint64_t msr_mask;
  65    powerpc_mmu_t   mmu_model;
  66    powerpc_excp_t  excp_model;
  67    powerpc_input_t bus_model;
  68    uint32_t flags;
  69    int bfd_mach;
  70    uint32_t l1_dcache_size, l1_icache_size;
  71#if defined(TARGET_PPC64)
  72    const struct ppc_segment_page_sizes *sps;
  73#endif
  74    void (*init_proc)(CPUPPCState *env);
  75    int  (*check_pow)(CPUPPCState *env);
  76#if defined(CONFIG_SOFTMMU)
  77    int (*handle_mmu_fault)(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
  78                            int mmu_idx);
  79#endif
  80    bool (*interrupts_big_endian)(PowerPCCPU *cpu);
  81} PowerPCCPUClass;
  82
  83/**
  84 * PowerPCCPU:
  85 * @env: #CPUPPCState
  86 * @cpu_dt_id: CPU index used in the device tree. KVM uses this index too
  87 * @max_compat: Maximal supported logical PVR from the command line
  88 * @cpu_version: Current logical PVR, zero if in "raw" mode
  89 *
  90 * A PowerPC CPU.
  91 */
  92struct PowerPCCPU {
  93    /*< private >*/
  94    CPUState parent_obj;
  95    /*< public >*/
  96
  97    CPUPPCState env;
  98    int cpu_dt_id;
  99    uint32_t max_compat;
 100    uint32_t cpu_version;
 101};
 102
 103static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env)
 104{
 105    return container_of(env, PowerPCCPU, env);
 106}
 107
 108#define ENV_GET_CPU(e) CPU(ppc_env_get_cpu(e))
 109
 110#define ENV_OFFSET offsetof(PowerPCCPU, env)
 111
 112PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr);
 113PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr);
 114
 115void ppc_cpu_do_interrupt(CPUState *cpu);
 116bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req);
 117void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
 118                        int flags);
 119void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f,
 120                             fprintf_function cpu_fprintf, int flags);
 121int ppc_cpu_get_monitor_def(CPUState *cs, const char *name,
 122                            uint64_t *pval);
 123hwaddr ppc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
 124int ppc_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
 125int ppc_cpu_gdb_read_register_apple(CPUState *cpu, uint8_t *buf, int reg);
 126int ppc_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
 127int ppc_cpu_gdb_write_register_apple(CPUState *cpu, uint8_t *buf, int reg);
 128int ppc64_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs,
 129                               int cpuid, void *opaque);
 130#ifndef CONFIG_USER_ONLY
 131void ppc_cpu_do_system_reset(CPUState *cs);
 132extern const struct VMStateDescription vmstate_ppc_cpu;
 133
 134typedef struct PPCTimebase {
 135    uint64_t guest_timebase;
 136    int64_t time_of_the_day_ns;
 137} PPCTimebase;
 138
 139extern const struct VMStateDescription vmstate_ppc_timebase;
 140
 141#define VMSTATE_PPC_TIMEBASE_V(_field, _state, _version) {            \
 142    .name       = (stringify(_field)),                                \
 143    .version_id = (_version),                                         \
 144    .size       = sizeof(PPCTimebase),                                \
 145    .vmsd       = &vmstate_ppc_timebase,                              \
 146    .flags      = VMS_STRUCT,                                         \
 147    .offset     = vmstate_offset_value(_state, _field, PPCTimebase),  \
 148}
 149#endif
 150
 151#endif
 152