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22#ifndef CPU_S390X_H
23#define CPU_S390X_H
24
25#include "qemu-common.h"
26
27#define TARGET_LONG_BITS 64
28
29#define ELF_MACHINE_UNAME "S390X"
30
31#define CPUArchState struct CPUS390XState
32
33#include "exec/cpu-defs.h"
34#define TARGET_PAGE_BITS 12
35
36#define TARGET_PHYS_ADDR_SPACE_BITS 64
37#define TARGET_VIRT_ADDR_SPACE_BITS 64
38
39#include "exec/cpu-all.h"
40
41#include "fpu/softfloat.h"
42
43#define NB_MMU_MODES 3
44#define TARGET_INSN_START_EXTRA_WORDS 1
45
46#define MMU_MODE0_SUFFIX _primary
47#define MMU_MODE1_SUFFIX _secondary
48#define MMU_MODE2_SUFFIX _home
49
50#define MMU_USER_IDX 0
51
52#define MAX_EXT_QUEUE 16
53#define MAX_IO_QUEUE 16
54#define MAX_MCHK_QUEUE 16
55
56#define PSW_MCHK_MASK 0x0004000000000000
57#define PSW_IO_MASK 0x0200000000000000
58
59typedef struct PSW {
60 uint64_t mask;
61 uint64_t addr;
62} PSW;
63
64typedef struct ExtQueue {
65 uint32_t code;
66 uint32_t param;
67 uint32_t param64;
68} ExtQueue;
69
70typedef struct IOIntQueue {
71 uint16_t id;
72 uint16_t nr;
73 uint32_t parm;
74 uint32_t word;
75} IOIntQueue;
76
77typedef struct MchkQueue {
78 uint16_t type;
79} MchkQueue;
80
81typedef struct CPUS390XState {
82 uint64_t regs[16];
83
84
85
86
87 CPU_DoubleU vregs[32][2];
88 uint32_t aregs[16];
89
90 uint32_t fpc;
91 uint32_t cc_op;
92
93 float_status fpu_status;
94
95
96 uint64_t retxl;
97
98 PSW psw;
99
100 uint64_t cc_src;
101 uint64_t cc_dst;
102 uint64_t cc_vr;
103
104 uint64_t __excp_addr;
105 uint64_t psa;
106
107 uint32_t int_pgm_code;
108 uint32_t int_pgm_ilen;
109
110 uint32_t int_svc_code;
111 uint32_t int_svc_ilen;
112
113 uint64_t per_address;
114 uint16_t per_perc_atmid;
115
116 uint64_t cregs[16];
117
118 ExtQueue ext_queue[MAX_EXT_QUEUE];
119 IOIntQueue io_queue[MAX_IO_QUEUE][8];
120 MchkQueue mchk_queue[MAX_MCHK_QUEUE];
121
122 int pending_int;
123 int ext_index;
124 int io_index[8];
125 int mchk_index;
126
127 uint64_t ckc;
128 uint64_t cputm;
129 uint32_t todpr;
130
131 uint64_t pfault_token;
132 uint64_t pfault_compare;
133 uint64_t pfault_select;
134
135 uint64_t gbea;
136 uint64_t pp;
137
138 CPU_COMMON
139
140
141
142 uint32_t cpu_num;
143 uint32_t machine_type;
144
145 uint64_t tod_offset;
146 uint64_t tod_basetime;
147 QEMUTimer *tod_timer;
148
149 QEMUTimer *cpu_timer;
150
151
152
153
154
155
156
157#define CPU_STATE_UNINITIALIZED 0x00
158#define CPU_STATE_STOPPED 0x01
159#define CPU_STATE_CHECK_STOP 0x02
160#define CPU_STATE_OPERATING 0x03
161#define CPU_STATE_LOAD 0x04
162 uint8_t cpu_state;
163
164
165 uint8_t sigp_order;
166
167} CPUS390XState;
168
169static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
170{
171 return &cs->vregs[nr][0];
172}
173
174#include "cpu-qom.h"
175#include <sysemu/kvm.h>
176
177
178#define HIGH_ORDER_BIT 0x80000000
179
180
181
182#define PGM_OPERATION 0x0001
183#define PGM_PRIVILEGED 0x0002
184#define PGM_EXECUTE 0x0003
185#define PGM_PROTECTION 0x0004
186#define PGM_ADDRESSING 0x0005
187#define PGM_SPECIFICATION 0x0006
188#define PGM_DATA 0x0007
189#define PGM_FIXPT_OVERFLOW 0x0008
190#define PGM_FIXPT_DIVIDE 0x0009
191#define PGM_DEC_OVERFLOW 0x000a
192#define PGM_DEC_DIVIDE 0x000b
193#define PGM_HFP_EXP_OVERFLOW 0x000c
194#define PGM_HFP_EXP_UNDERFLOW 0x000d
195#define PGM_HFP_SIGNIFICANCE 0x000e
196#define PGM_HFP_DIVIDE 0x000f
197#define PGM_SEGMENT_TRANS 0x0010
198#define PGM_PAGE_TRANS 0x0011
199#define PGM_TRANS_SPEC 0x0012
200#define PGM_SPECIAL_OP 0x0013
201#define PGM_OPERAND 0x0015
202#define PGM_TRACE_TABLE 0x0016
203#define PGM_SPACE_SWITCH 0x001c
204#define PGM_HFP_SQRT 0x001d
205#define PGM_PC_TRANS_SPEC 0x001f
206#define PGM_AFX_TRANS 0x0020
207#define PGM_ASX_TRANS 0x0021
208#define PGM_LX_TRANS 0x0022
209#define PGM_EX_TRANS 0x0023
210#define PGM_PRIM_AUTH 0x0024
211#define PGM_SEC_AUTH 0x0025
212#define PGM_ALET_SPEC 0x0028
213#define PGM_ALEN_SPEC 0x0029
214#define PGM_ALE_SEQ 0x002a
215#define PGM_ASTE_VALID 0x002b
216#define PGM_ASTE_SEQ 0x002c
217#define PGM_EXT_AUTH 0x002d
218#define PGM_STACK_FULL 0x0030
219#define PGM_STACK_EMPTY 0x0031
220#define PGM_STACK_SPEC 0x0032
221#define PGM_STACK_TYPE 0x0033
222#define PGM_STACK_OP 0x0034
223#define PGM_ASCE_TYPE 0x0038
224#define PGM_REG_FIRST_TRANS 0x0039
225#define PGM_REG_SEC_TRANS 0x003a
226#define PGM_REG_THIRD_TRANS 0x003b
227#define PGM_MONITOR 0x0040
228#define PGM_PER 0x0080
229#define PGM_CRYPTO 0x0119
230
231
232#define EXT_INTERRUPT_KEY 0x0040
233#define EXT_CLOCK_COMP 0x1004
234#define EXT_CPU_TIMER 0x1005
235#define EXT_MALFUNCTION 0x1200
236#define EXT_EMERGENCY 0x1201
237#define EXT_EXTERNAL_CALL 0x1202
238#define EXT_ETR 0x1406
239#define EXT_SERVICE 0x2401
240#define EXT_VIRTIO 0x2603
241
242
243#undef PSW_MASK_PER
244#undef PSW_MASK_DAT
245#undef PSW_MASK_IO
246#undef PSW_MASK_EXT
247#undef PSW_MASK_KEY
248#undef PSW_SHIFT_KEY
249#undef PSW_MASK_MCHECK
250#undef PSW_MASK_WAIT
251#undef PSW_MASK_PSTATE
252#undef PSW_MASK_ASC
253#undef PSW_MASK_CC
254#undef PSW_MASK_PM
255#undef PSW_MASK_64
256#undef PSW_MASK_32
257#undef PSW_MASK_ESA_ADDR
258
259#define PSW_MASK_PER 0x4000000000000000ULL
260#define PSW_MASK_DAT 0x0400000000000000ULL
261#define PSW_MASK_IO 0x0200000000000000ULL
262#define PSW_MASK_EXT 0x0100000000000000ULL
263#define PSW_MASK_KEY 0x00F0000000000000ULL
264#define PSW_SHIFT_KEY 56
265#define PSW_MASK_MCHECK 0x0004000000000000ULL
266#define PSW_MASK_WAIT 0x0002000000000000ULL
267#define PSW_MASK_PSTATE 0x0001000000000000ULL
268#define PSW_MASK_ASC 0x0000C00000000000ULL
269#define PSW_MASK_CC 0x0000300000000000ULL
270#define PSW_MASK_PM 0x00000F0000000000ULL
271#define PSW_MASK_64 0x0000000100000000ULL
272#define PSW_MASK_32 0x0000000080000000ULL
273#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
274
275#undef PSW_ASC_PRIMARY
276#undef PSW_ASC_ACCREG
277#undef PSW_ASC_SECONDARY
278#undef PSW_ASC_HOME
279
280#define PSW_ASC_PRIMARY 0x0000000000000000ULL
281#define PSW_ASC_ACCREG 0x0000400000000000ULL
282#define PSW_ASC_SECONDARY 0x0000800000000000ULL
283#define PSW_ASC_HOME 0x0000C00000000000ULL
284
285
286
287#define FLAG_MASK_PER (PSW_MASK_PER >> 32)
288#define FLAG_MASK_DAT (PSW_MASK_DAT >> 32)
289#define FLAG_MASK_IO (PSW_MASK_IO >> 32)
290#define FLAG_MASK_EXT (PSW_MASK_EXT >> 32)
291#define FLAG_MASK_KEY (PSW_MASK_KEY >> 32)
292#define FLAG_MASK_MCHECK (PSW_MASK_MCHECK >> 32)
293#define FLAG_MASK_WAIT (PSW_MASK_WAIT >> 32)
294#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> 32)
295#define FLAG_MASK_ASC (PSW_MASK_ASC >> 32)
296#define FLAG_MASK_CC (PSW_MASK_CC >> 32)
297#define FLAG_MASK_PM (PSW_MASK_PM >> 32)
298#define FLAG_MASK_64 (PSW_MASK_64 >> 32)
299#define FLAG_MASK_32 0x00001000
300
301
302#define CR0_LOWPROT 0x0000000010000000ULL
303#define CR0_EDAT 0x0000000000800000ULL
304
305
306#define MMU_PRIMARY_IDX 0
307#define MMU_SECONDARY_IDX 1
308#define MMU_HOME_IDX 2
309
310static inline int cpu_mmu_index (CPUS390XState *env, bool ifetch)
311{
312 switch (env->psw.mask & PSW_MASK_ASC) {
313 case PSW_ASC_PRIMARY:
314 return MMU_PRIMARY_IDX;
315 case PSW_ASC_SECONDARY:
316 return MMU_SECONDARY_IDX;
317 case PSW_ASC_HOME:
318 return MMU_HOME_IDX;
319 case PSW_ASC_ACCREG:
320
321 default:
322 abort();
323 }
324}
325
326static inline uint64_t cpu_mmu_idx_to_asc(int mmu_idx)
327{
328 switch (mmu_idx) {
329 case MMU_PRIMARY_IDX:
330 return PSW_ASC_PRIMARY;
331 case MMU_SECONDARY_IDX:
332 return PSW_ASC_SECONDARY;
333 case MMU_HOME_IDX:
334 return PSW_ASC_HOME;
335 default:
336 abort();
337 }
338}
339
340static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
341 target_ulong *cs_base, int *flags)
342{
343 *pc = env->psw.addr;
344 *cs_base = 0;
345 *flags = ((env->psw.mask >> 32) & ~FLAG_MASK_CC) |
346 ((env->psw.mask & PSW_MASK_32) ? FLAG_MASK_32 : 0);
347}
348
349
350
351
352
353
354static inline int get_ilen(uint8_t opc)
355{
356 switch (opc >> 6) {
357 case 0:
358 return 2;
359 case 1:
360 case 2:
361 return 4;
362 default:
363 return 6;
364 }
365}
366
367
368#define PER_CR9_EVENT_BRANCH 0x80000000
369#define PER_CR9_EVENT_IFETCH 0x40000000
370#define PER_CR9_EVENT_STORE 0x20000000
371#define PER_CR9_EVENT_STORE_REAL 0x08000000
372#define PER_CR9_EVENT_NULLIFICATION 0x01000000
373#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
374#define PER_CR9_CONTROL_ALTERATION 0x00200000
375
376
377#define PER_CODE_EVENT_BRANCH 0x8000
378#define PER_CODE_EVENT_IFETCH 0x4000
379#define PER_CODE_EVENT_STORE 0x2000
380#define PER_CODE_EVENT_STORE_REAL 0x0800
381#define PER_CODE_EVENT_NULLIFICATION 0x0100
382
383
384
385static inline uint8_t get_per_atmid(CPUS390XState *env)
386{
387 return ((env->psw.mask & PSW_MASK_64) ? (1 << 7) : 0) |
388 ( (1 << 6) ) |
389 ((env->psw.mask & PSW_MASK_32) ? (1 << 5) : 0) |
390 ((env->psw.mask & PSW_MASK_DAT)? (1 << 4) : 0) |
391 ((env->psw.mask & PSW_ASC_SECONDARY)? (1 << 3) : 0) |
392 ((env->psw.mask & PSW_ASC_ACCREG)? (1 << 2) : 0);
393}
394
395
396
397static inline bool get_per_in_range(CPUS390XState *env, uint64_t addr)
398{
399 if (env->cregs[10] <= env->cregs[11]) {
400 return env->cregs[10] <= addr && addr <= env->cregs[11];
401 } else {
402 return env->cregs[10] <= addr || addr <= env->cregs[11];
403 }
404}
405
406#ifndef CONFIG_USER_ONLY
407
408
409
410#define ILEN_LATER 0x20
411#define ILEN_LATER_INC 0x21
412void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilen);
413#endif
414
415S390CPU *cpu_s390x_init(const char *cpu_model);
416S390CPU *s390x_new_cpu(const char *cpu_model, int64_t id, Error **errp);
417S390CPU *cpu_s390x_create(const char *cpu_model, Error **errp);
418void s390x_translate_init(void);
419int cpu_s390x_exec(CPUState *cpu);
420
421
422
423
424int cpu_s390x_signal_handler(int host_signum, void *pinfo,
425 void *puc);
426int s390_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
427 int mmu_idx);
428
429#include "ioinst.h"
430
431
432#ifndef CONFIG_USER_ONLY
433void do_restart_interrupt(CPUS390XState *env);
434
435static inline hwaddr decode_basedisp_s(CPUS390XState *env, uint32_t ipb,
436 uint8_t *ar)
437{
438 hwaddr addr = 0;
439 uint8_t reg;
440
441 reg = ipb >> 28;
442 if (reg > 0) {
443 addr = env->regs[reg];
444 }
445 addr += (ipb >> 16) & 0xfff;
446 if (ar) {
447 *ar = reg;
448 }
449
450 return addr;
451}
452
453
454#define decode_basedisp_rs decode_basedisp_s
455
456
457static inline void s390_do_cpu_reset(void *arg)
458{
459 CPUState *cs = arg;
460 S390CPUClass *scc = S390_CPU_GET_CLASS(cs);
461
462 scc->cpu_reset(cs);
463}
464static inline void s390_do_cpu_full_reset(void *arg)
465{
466 CPUState *cs = arg;
467
468 cpu_reset(cs);
469}
470
471void s390x_tod_timer(void *opaque);
472void s390x_cpu_timer(void *opaque);
473
474int s390_virtio_hypercall(CPUS390XState *env);
475
476#ifdef CONFIG_KVM
477void kvm_s390_service_interrupt(uint32_t parm);
478void kvm_s390_vcpu_interrupt(S390CPU *cpu, struct kvm_s390_irq *irq);
479void kvm_s390_floating_interrupt(struct kvm_s390_irq *irq);
480int kvm_s390_inject_flic(struct kvm_s390_irq *irq);
481void kvm_s390_access_exception(S390CPU *cpu, uint16_t code, uint64_t te_code);
482int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar, void *hostbuf,
483 int len, bool is_write);
484int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_clock);
485int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_clock);
486#else
487static inline void kvm_s390_service_interrupt(uint32_t parm)
488{
489}
490static inline int kvm_s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
491{
492 return -ENOSYS;
493}
494static inline int kvm_s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
495{
496 return -ENOSYS;
497}
498static inline int kvm_s390_mem_op(S390CPU *cpu, vaddr addr, uint8_t ar,
499 void *hostbuf, int len, bool is_write)
500{
501 return -ENOSYS;
502}
503static inline void kvm_s390_access_exception(S390CPU *cpu, uint16_t code,
504 uint64_t te_code)
505{
506}
507#endif
508
509static inline int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low)
510{
511 if (kvm_enabled()) {
512 return kvm_s390_get_clock(tod_high, tod_low);
513 }
514
515 *tod_high = 0;
516 *tod_low = 0;
517 return 0;
518}
519
520static inline int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low)
521{
522 if (kvm_enabled()) {
523 return kvm_s390_set_clock(tod_high, tod_low);
524 }
525
526 return 0;
527}
528
529S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
530unsigned int s390_cpu_halt(S390CPU *cpu);
531void s390_cpu_unhalt(S390CPU *cpu);
532unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
533static inline uint8_t s390_cpu_get_state(S390CPU *cpu)
534{
535 return cpu->env.cpu_state;
536}
537
538void gtod_save(QEMUFile *f, void *opaque);
539int gtod_load(QEMUFile *f, void *opaque, int version_id);
540
541
542void s390_sclp_extint(uint32_t parm);
543
544#else
545static inline unsigned int s390_cpu_halt(S390CPU *cpu)
546{
547 return 0;
548}
549
550static inline void s390_cpu_unhalt(S390CPU *cpu)
551{
552}
553
554static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
555{
556 return 0;
557}
558#endif
559void cpu_lock(void);
560void cpu_unlock(void);
561
562typedef struct SubchDev SubchDev;
563
564#ifndef CONFIG_USER_ONLY
565extern void subsystem_reset(void);
566SubchDev *css_find_subch(uint8_t m, uint8_t cssid, uint8_t ssid,
567 uint16_t schid);
568bool css_subch_visible(SubchDev *sch);
569void css_conditional_io_interrupt(SubchDev *sch);
570int css_do_stsch(SubchDev *sch, SCHIB *schib);
571bool css_schid_final(int m, uint8_t cssid, uint8_t ssid, uint16_t schid);
572int css_do_msch(SubchDev *sch, const SCHIB *schib);
573int css_do_xsch(SubchDev *sch);
574int css_do_csch(SubchDev *sch);
575int css_do_hsch(SubchDev *sch);
576int css_do_ssch(SubchDev *sch, ORB *orb);
577int css_do_tsch_get_irb(SubchDev *sch, IRB *irb, int *irb_len);
578void css_do_tsch_update_subch(SubchDev *sch);
579int css_do_stcrw(CRW *crw);
580void css_undo_stcrw(CRW *crw);
581int css_do_tpi(IOIntCode *int_code, int lowcore);
582int css_collect_chp_desc(int m, uint8_t cssid, uint8_t f_chpid, uint8_t l_chpid,
583 int rfmt, void *buf);
584void css_do_schm(uint8_t mbk, int update, int dct, uint64_t mbo);
585int css_enable_mcsse(void);
586int css_enable_mss(void);
587int css_do_rsch(SubchDev *sch);
588int css_do_rchp(uint8_t cssid, uint8_t chpid);
589bool css_present(uint8_t cssid);
590#endif
591
592#define cpu_init(model) CPU(cpu_s390x_init(model))
593#define cpu_exec cpu_s390x_exec
594#define cpu_signal_handler cpu_s390x_signal_handler
595
596void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
597#define cpu_list s390_cpu_list
598
599#include "exec/exec-all.h"
600
601#define EXCP_EXT 1
602#define EXCP_SVC 2
603#define EXCP_PGM 3
604#define EXCP_IO 7
605#define EXCP_MCHK 8
606
607#define INTERRUPT_EXT (1 << 0)
608#define INTERRUPT_TOD (1 << 1)
609#define INTERRUPT_CPUTIMER (1 << 2)
610#define INTERRUPT_IO (1 << 3)
611#define INTERRUPT_MCHK (1 << 4)
612
613
614#define S390_PSWM_REGNUM 0
615#define S390_PSWA_REGNUM 1
616
617#define S390_R0_REGNUM 2
618#define S390_R1_REGNUM 3
619#define S390_R2_REGNUM 4
620#define S390_R3_REGNUM 5
621#define S390_R4_REGNUM 6
622#define S390_R5_REGNUM 7
623#define S390_R6_REGNUM 8
624#define S390_R7_REGNUM 9
625#define S390_R8_REGNUM 10
626#define S390_R9_REGNUM 11
627#define S390_R10_REGNUM 12
628#define S390_R11_REGNUM 13
629#define S390_R12_REGNUM 14
630#define S390_R13_REGNUM 15
631#define S390_R14_REGNUM 16
632#define S390_R15_REGNUM 17
633
634#define S390_NUM_CORE_REGS 18
635
636
637
638enum cc_op {
639 CC_OP_CONST0 = 0,
640 CC_OP_CONST1,
641 CC_OP_CONST2,
642 CC_OP_CONST3,
643
644 CC_OP_DYNAMIC,
645 CC_OP_STATIC,
646
647 CC_OP_NZ,
648 CC_OP_LTGT_32,
649 CC_OP_LTGT_64,
650 CC_OP_LTUGTU_32,
651 CC_OP_LTUGTU_64,
652 CC_OP_LTGT0_32,
653 CC_OP_LTGT0_64,
654
655 CC_OP_ADD_64,
656 CC_OP_ADDU_64,
657 CC_OP_ADDC_64,
658 CC_OP_SUB_64,
659 CC_OP_SUBU_64,
660 CC_OP_SUBB_64,
661 CC_OP_ABS_64,
662 CC_OP_NABS_64,
663
664 CC_OP_ADD_32,
665 CC_OP_ADDU_32,
666 CC_OP_ADDC_32,
667 CC_OP_SUB_32,
668 CC_OP_SUBU_32,
669 CC_OP_SUBB_32,
670 CC_OP_ABS_32,
671 CC_OP_NABS_32,
672
673 CC_OP_COMP_32,
674 CC_OP_COMP_64,
675
676 CC_OP_TM_32,
677 CC_OP_TM_64,
678
679 CC_OP_NZ_F32,
680 CC_OP_NZ_F64,
681 CC_OP_NZ_F128,
682
683 CC_OP_ICM,
684 CC_OP_SLA_32,
685 CC_OP_SLA_64,
686 CC_OP_FLOGR,
687 CC_OP_MAX
688};
689
690static const char *cc_names[] = {
691 [CC_OP_CONST0] = "CC_OP_CONST0",
692 [CC_OP_CONST1] = "CC_OP_CONST1",
693 [CC_OP_CONST2] = "CC_OP_CONST2",
694 [CC_OP_CONST3] = "CC_OP_CONST3",
695 [CC_OP_DYNAMIC] = "CC_OP_DYNAMIC",
696 [CC_OP_STATIC] = "CC_OP_STATIC",
697 [CC_OP_NZ] = "CC_OP_NZ",
698 [CC_OP_LTGT_32] = "CC_OP_LTGT_32",
699 [CC_OP_LTGT_64] = "CC_OP_LTGT_64",
700 [CC_OP_LTUGTU_32] = "CC_OP_LTUGTU_32",
701 [CC_OP_LTUGTU_64] = "CC_OP_LTUGTU_64",
702 [CC_OP_LTGT0_32] = "CC_OP_LTGT0_32",
703 [CC_OP_LTGT0_64] = "CC_OP_LTGT0_64",
704 [CC_OP_ADD_64] = "CC_OP_ADD_64",
705 [CC_OP_ADDU_64] = "CC_OP_ADDU_64",
706 [CC_OP_ADDC_64] = "CC_OP_ADDC_64",
707 [CC_OP_SUB_64] = "CC_OP_SUB_64",
708 [CC_OP_SUBU_64] = "CC_OP_SUBU_64",
709 [CC_OP_SUBB_64] = "CC_OP_SUBB_64",
710 [CC_OP_ABS_64] = "CC_OP_ABS_64",
711 [CC_OP_NABS_64] = "CC_OP_NABS_64",
712 [CC_OP_ADD_32] = "CC_OP_ADD_32",
713 [CC_OP_ADDU_32] = "CC_OP_ADDU_32",
714 [CC_OP_ADDC_32] = "CC_OP_ADDC_32",
715 [CC_OP_SUB_32] = "CC_OP_SUB_32",
716 [CC_OP_SUBU_32] = "CC_OP_SUBU_32",
717 [CC_OP_SUBB_32] = "CC_OP_SUBB_32",
718 [CC_OP_ABS_32] = "CC_OP_ABS_32",
719 [CC_OP_NABS_32] = "CC_OP_NABS_32",
720 [CC_OP_COMP_32] = "CC_OP_COMP_32",
721 [CC_OP_COMP_64] = "CC_OP_COMP_64",
722 [CC_OP_TM_32] = "CC_OP_TM_32",
723 [CC_OP_TM_64] = "CC_OP_TM_64",
724 [CC_OP_NZ_F32] = "CC_OP_NZ_F32",
725 [CC_OP_NZ_F64] = "CC_OP_NZ_F64",
726 [CC_OP_NZ_F128] = "CC_OP_NZ_F128",
727 [CC_OP_ICM] = "CC_OP_ICM",
728 [CC_OP_SLA_32] = "CC_OP_SLA_32",
729 [CC_OP_SLA_64] = "CC_OP_SLA_64",
730 [CC_OP_FLOGR] = "CC_OP_FLOGR",
731};
732
733static inline const char *cc_name(int cc_op)
734{
735 return cc_names[cc_op];
736}
737
738static inline void setcc(S390CPU *cpu, uint64_t cc)
739{
740 CPUS390XState *env = &cpu->env;
741
742 env->psw.mask &= ~(3ull << 44);
743 env->psw.mask |= (cc & 3) << 44;
744 env->cc_op = cc;
745}
746
747typedef struct LowCore
748{
749
750 uint32_t ccw1[2];
751 uint32_t ccw2[4];
752 uint8_t pad1[0x80-0x18];
753 uint32_t ext_params;
754 uint16_t cpu_addr;
755 uint16_t ext_int_code;
756 uint16_t svc_ilen;
757 uint16_t svc_code;
758 uint16_t pgm_ilen;
759 uint16_t pgm_code;
760 uint32_t data_exc_code;
761 uint16_t mon_class_num;
762 uint16_t per_perc_atmid;
763 uint64_t per_address;
764 uint8_t exc_access_id;
765 uint8_t per_access_id;
766 uint8_t op_access_id;
767 uint8_t ar_access_id;
768 uint8_t pad2[0xA8-0xA4];
769 uint64_t trans_exc_code;
770 uint64_t monitor_code;
771 uint16_t subchannel_id;
772 uint16_t subchannel_nr;
773 uint32_t io_int_parm;
774 uint32_t io_int_word;
775 uint8_t pad3[0xc8-0xc4];
776 uint32_t stfl_fac_list;
777 uint8_t pad4[0xe8-0xcc];
778 uint32_t mcck_interruption_code[2];
779 uint8_t pad5[0xf4-0xf0];
780 uint32_t external_damage_code;
781 uint64_t failing_storage_address;
782 uint8_t pad6[0x110-0x100];
783 uint64_t per_breaking_event_addr;
784 uint8_t pad7[0x120-0x118];
785 PSW restart_old_psw;
786 PSW external_old_psw;
787 PSW svc_old_psw;
788 PSW program_old_psw;
789 PSW mcck_old_psw;
790 PSW io_old_psw;
791 uint8_t pad8[0x1a0-0x180];
792 PSW restart_new_psw;
793 PSW external_new_psw;
794 PSW svc_new_psw;
795 PSW program_new_psw;
796 PSW mcck_new_psw;
797 PSW io_new_psw;
798 PSW return_psw;
799 uint8_t irb[64];
800 uint64_t sync_enter_timer;
801 uint64_t async_enter_timer;
802 uint64_t exit_timer;
803 uint64_t last_update_timer;
804 uint64_t user_timer;
805 uint64_t system_timer;
806 uint64_t last_update_clock;
807 uint64_t steal_clock;
808 PSW return_mcck_psw;
809 uint8_t pad9[0xc00-0x2a0];
810
811 uint64_t save_area[16];
812 uint8_t pad10[0xd40-0xc80];
813 uint64_t kernel_stack;
814 uint64_t thread_info;
815 uint64_t async_stack;
816 uint64_t kernel_asce;
817 uint64_t user_asce;
818 uint64_t panic_stack;
819 uint64_t user_exec_asce;
820 uint8_t pad11[0xdc0-0xd78];
821
822
823 uint64_t clock_comparator;
824 uint64_t ext_call_fast;
825 uint64_t percpu_offset;
826 uint64_t current_task;
827 uint32_t softirq_pending;
828 uint32_t pad_0x0de4;
829 uint64_t int_clock;
830 uint8_t pad12[0xe00-0xdf0];
831
832
833
834 uint32_t panic_magic;
835
836 uint8_t pad13[0x11b8-0xe04];
837
838
839 uint64_t ext_params2;
840
841 uint8_t pad14[0x1200-0x11C0];
842
843
844
845 uint64_t floating_pt_save_area[16];
846 uint64_t gpregs_save_area[16];
847 uint32_t st_status_fixed_logout[4];
848 uint8_t pad15[0x1318-0x1310];
849 uint32_t prefixreg_save_area;
850 uint32_t fpt_creg_save_area;
851 uint8_t pad16[0x1324-0x1320];
852 uint32_t tod_progreg_save_area;
853 uint32_t cpu_timer_save_area[2];
854 uint32_t clock_comp_save_area[2];
855 uint8_t pad17[0x1340-0x1338];
856 uint32_t access_regs_save_area[16];
857 uint64_t cregs_save_area[16];
858
859
860
861 uint8_t pad18[0x2000-0x1400];
862} QEMU_PACKED LowCore;
863
864
865#define STSI_LEVEL_MASK 0x00000000f0000000ULL
866#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
867#define STSI_LEVEL_1 0x0000000010000000ULL
868#define STSI_LEVEL_2 0x0000000020000000ULL
869#define STSI_LEVEL_3 0x0000000030000000ULL
870#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
871#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
872#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
873#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
874
875
876struct sysib_111 {
877 uint32_t res1[8];
878 uint8_t manuf[16];
879 uint8_t type[4];
880 uint8_t res2[12];
881 uint8_t model[16];
882 uint8_t sequence[16];
883 uint8_t plant[4];
884 uint8_t res3[156];
885};
886
887
888struct sysib_121 {
889 uint32_t res1[80];
890 uint8_t sequence[16];
891 uint8_t plant[4];
892 uint8_t res2[2];
893 uint16_t cpu_addr;
894 uint8_t res3[152];
895};
896
897
898struct sysib_122 {
899 uint8_t res1[32];
900 uint32_t capability;
901 uint16_t total_cpus;
902 uint16_t active_cpus;
903 uint16_t standby_cpus;
904 uint16_t reserved_cpus;
905 uint16_t adjustments[2026];
906};
907
908
909struct sysib_221 {
910 uint32_t res1[80];
911 uint8_t sequence[16];
912 uint8_t plant[4];
913 uint16_t cpu_id;
914 uint16_t cpu_addr;
915 uint8_t res3[152];
916};
917
918
919struct sysib_222 {
920 uint32_t res1[32];
921 uint16_t lpar_num;
922 uint8_t res2;
923 uint8_t lcpuc;
924 uint16_t total_cpus;
925 uint16_t conf_cpus;
926 uint16_t standby_cpus;
927 uint16_t reserved_cpus;
928 uint8_t name[8];
929 uint32_t caf;
930 uint8_t res3[16];
931 uint16_t dedicated_cpus;
932 uint16_t shared_cpus;
933 uint8_t res4[180];
934};
935
936
937struct sysib_322 {
938 uint8_t res1[31];
939 uint8_t count;
940 struct {
941 uint8_t res2[4];
942 uint16_t total_cpus;
943 uint16_t conf_cpus;
944 uint16_t standby_cpus;
945 uint16_t reserved_cpus;
946 uint8_t name[8];
947 uint32_t caf;
948 uint8_t cpi[16];
949 uint8_t res5[3];
950 uint8_t ext_name_encoding;
951 uint32_t res3;
952 uint8_t uuid[16];
953 } vm[8];
954 uint8_t res4[1504];
955 uint8_t ext_names[8][256];
956};
957
958
959#define _ASCE_ORIGIN ~0xfffULL
960#define _ASCE_SUBSPACE 0x200
961#define _ASCE_PRIVATE_SPACE 0x100
962#define _ASCE_ALT_EVENT 0x80
963#define _ASCE_SPACE_SWITCH 0x40
964#define _ASCE_REAL_SPACE 0x20
965#define _ASCE_TYPE_MASK 0x0c
966#define _ASCE_TYPE_REGION1 0x0c
967#define _ASCE_TYPE_REGION2 0x08
968#define _ASCE_TYPE_REGION3 0x04
969#define _ASCE_TYPE_SEGMENT 0x00
970#define _ASCE_TABLE_LENGTH 0x03
971
972#define _REGION_ENTRY_ORIGIN ~0xfffULL
973#define _REGION_ENTRY_RO 0x200
974#define _REGION_ENTRY_TF 0xc0
975#define _REGION_ENTRY_INV 0x20
976#define _REGION_ENTRY_TYPE_MASK 0x0c
977#define _REGION_ENTRY_TYPE_R1 0x0c
978#define _REGION_ENTRY_TYPE_R2 0x08
979#define _REGION_ENTRY_TYPE_R3 0x04
980#define _REGION_ENTRY_LENGTH 0x03
981
982#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL
983#define _SEGMENT_ENTRY_FC 0x400
984#define _SEGMENT_ENTRY_RO 0x200
985#define _SEGMENT_ENTRY_INV 0x20
986
987#define _PAGE_RO 0x200
988#define _PAGE_INVALID 0x400
989#define _PAGE_RES0 0x800
990
991#define SK_C (0x1 << 1)
992#define SK_R (0x1 << 2)
993#define SK_F (0x1 << 3)
994#define SK_ACC_MASK (0xf << 4)
995
996
997#define SIGP_SENSE 0x01
998#define SIGP_EXTERNAL_CALL 0x02
999#define SIGP_EMERGENCY 0x03
1000#define SIGP_START 0x04
1001#define SIGP_STOP 0x05
1002#define SIGP_RESTART 0x06
1003#define SIGP_STOP_STORE_STATUS 0x09
1004#define SIGP_INITIAL_CPU_RESET 0x0b
1005#define SIGP_CPU_RESET 0x0c
1006#define SIGP_SET_PREFIX 0x0d
1007#define SIGP_STORE_STATUS_ADDR 0x0e
1008#define SIGP_SET_ARCH 0x12
1009#define SIGP_STORE_ADTL_STATUS 0x17
1010
1011
1012#define SIGP_CC_ORDER_CODE_ACCEPTED 0
1013#define SIGP_CC_STATUS_STORED 1
1014#define SIGP_CC_BUSY 2
1015#define SIGP_CC_NOT_OPERATIONAL 3
1016
1017
1018#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
1019#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
1020#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
1021#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
1022#define SIGP_STAT_STOPPED 0x00000040UL
1023#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
1024#define SIGP_STAT_CHECK_STOP 0x00000010UL
1025#define SIGP_STAT_INOPERATIVE 0x00000004UL
1026#define SIGP_STAT_INVALID_ORDER 0x00000002UL
1027#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
1028
1029
1030#define SIGP_MODE_ESA_S390 0
1031#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
1032#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
1033
1034void load_psw(CPUS390XState *env, uint64_t mask, uint64_t addr);
1035int mmu_translate(CPUS390XState *env, target_ulong vaddr, int rw, uint64_t asc,
1036 target_ulong *raddr, int *flags, bool exc);
1037int sclp_service_call(CPUS390XState *env, uint64_t sccb, uint32_t code);
1038uint32_t calc_cc(CPUS390XState *env, uint32_t cc_op, uint64_t src, uint64_t dst,
1039 uint64_t vr);
1040void s390_cpu_recompute_watchpoints(CPUState *cs);
1041
1042int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
1043 int len, bool is_write);
1044
1045#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
1046 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
1047#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
1048 s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
1049#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
1050 s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
1051
1052
1053#define TOD_UNIX_EPOCH 0x7d91048bca000000ULL
1054
1055
1056static inline uint64_t time2tod(uint64_t ns) {
1057 return (ns << 9) / 125;
1058}
1059
1060
1061static inline uint64_t tod2time(uint64_t t) {
1062 return (t * 125) >> 9;
1063}
1064
1065static inline void cpu_inject_ext(S390CPU *cpu, uint32_t code, uint32_t param,
1066 uint64_t param64)
1067{
1068 CPUS390XState *env = &cpu->env;
1069
1070 if (env->ext_index == MAX_EXT_QUEUE - 1) {
1071
1072 return;
1073 }
1074
1075 env->ext_index++;
1076 assert(env->ext_index < MAX_EXT_QUEUE);
1077
1078 env->ext_queue[env->ext_index].code = code;
1079 env->ext_queue[env->ext_index].param = param;
1080 env->ext_queue[env->ext_index].param64 = param64;
1081
1082 env->pending_int |= INTERRUPT_EXT;
1083 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1084}
1085
1086static inline void cpu_inject_io(S390CPU *cpu, uint16_t subchannel_id,
1087 uint16_t subchannel_number,
1088 uint32_t io_int_parm, uint32_t io_int_word)
1089{
1090 CPUS390XState *env = &cpu->env;
1091 int isc = IO_INT_WORD_ISC(io_int_word);
1092
1093 if (env->io_index[isc] == MAX_IO_QUEUE - 1) {
1094
1095 return;
1096 }
1097
1098 env->io_index[isc]++;
1099 assert(env->io_index[isc] < MAX_IO_QUEUE);
1100
1101 env->io_queue[env->io_index[isc]][isc].id = subchannel_id;
1102 env->io_queue[env->io_index[isc]][isc].nr = subchannel_number;
1103 env->io_queue[env->io_index[isc]][isc].parm = io_int_parm;
1104 env->io_queue[env->io_index[isc]][isc].word = io_int_word;
1105
1106 env->pending_int |= INTERRUPT_IO;
1107 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1108}
1109
1110static inline void cpu_inject_crw_mchk(S390CPU *cpu)
1111{
1112 CPUS390XState *env = &cpu->env;
1113
1114 if (env->mchk_index == MAX_MCHK_QUEUE - 1) {
1115
1116 return;
1117 }
1118
1119 env->mchk_index++;
1120 assert(env->mchk_index < MAX_MCHK_QUEUE);
1121
1122 env->mchk_queue[env->mchk_index].type = 1;
1123
1124 env->pending_int |= INTERRUPT_MCHK;
1125 cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD);
1126}
1127
1128
1129#define MEM_SECTION_SIZE 0x10000000UL
1130#define MAX_AVAIL_SLOTS 32
1131
1132
1133uint32_t set_cc_nz_f32(float32 v);
1134uint32_t set_cc_nz_f64(float64 v);
1135uint32_t set_cc_nz_f128(float128 v);
1136
1137
1138#ifndef CONFIG_USER_ONLY
1139int handle_diag_288(CPUS390XState *env, uint64_t r1, uint64_t r3);
1140void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3);
1141#endif
1142void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
1143void QEMU_NORETURN runtime_exception(CPUS390XState *env, int excp,
1144 uintptr_t retaddr);
1145
1146#ifdef CONFIG_KVM
1147void kvm_s390_io_interrupt(uint16_t subchannel_id,
1148 uint16_t subchannel_nr, uint32_t io_int_parm,
1149 uint32_t io_int_word);
1150void kvm_s390_crw_mchk(void);
1151void kvm_s390_enable_css_support(S390CPU *cpu);
1152int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch,
1153 int vq, bool assign);
1154int kvm_s390_cpu_restart(S390CPU *cpu);
1155int kvm_s390_get_memslot_count(KVMState *s);
1156void kvm_s390_cmma_reset(void);
1157int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state);
1158void kvm_s390_reset_vcpu(S390CPU *cpu);
1159int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit, uint64_t *hw_limit);
1160void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu);
1161int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu);
1162void kvm_s390_crypto_reset(void);
1163#else
1164static inline void kvm_s390_io_interrupt(uint16_t subchannel_id,
1165 uint16_t subchannel_nr,
1166 uint32_t io_int_parm,
1167 uint32_t io_int_word)
1168{
1169}
1170static inline void kvm_s390_crw_mchk(void)
1171{
1172}
1173static inline void kvm_s390_enable_css_support(S390CPU *cpu)
1174{
1175}
1176static inline int kvm_s390_assign_subch_ioeventfd(EventNotifier *notifier,
1177 uint32_t sch, int vq,
1178 bool assign)
1179{
1180 return -ENOSYS;
1181}
1182static inline int kvm_s390_cpu_restart(S390CPU *cpu)
1183{
1184 return -ENOSYS;
1185}
1186static inline void kvm_s390_cmma_reset(void)
1187{
1188}
1189static inline int kvm_s390_get_memslot_count(KVMState *s)
1190{
1191 return MAX_AVAIL_SLOTS;
1192}
1193static inline int kvm_s390_set_cpu_state(S390CPU *cpu, uint8_t cpu_state)
1194{
1195 return -ENOSYS;
1196}
1197static inline void kvm_s390_reset_vcpu(S390CPU *cpu)
1198{
1199}
1200static inline int kvm_s390_set_mem_limit(KVMState *s, uint64_t new_limit,
1201 uint64_t *hw_limit)
1202{
1203 return 0;
1204}
1205static inline void kvm_s390_vcpu_interrupt_pre_save(S390CPU *cpu)
1206{
1207}
1208static inline int kvm_s390_vcpu_interrupt_post_load(S390CPU *cpu)
1209{
1210 return 0;
1211}
1212static inline void kvm_s390_crypto_reset(void)
1213{
1214}
1215#endif
1216
1217static inline int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit)
1218{
1219 if (kvm_enabled()) {
1220 return kvm_s390_set_mem_limit(kvm_state, new_limit, hw_limit);
1221 }
1222 return 0;
1223}
1224
1225static inline void s390_cmma_reset(void)
1226{
1227 if (kvm_enabled()) {
1228 kvm_s390_cmma_reset();
1229 }
1230}
1231
1232static inline int s390_cpu_restart(S390CPU *cpu)
1233{
1234 if (kvm_enabled()) {
1235 return kvm_s390_cpu_restart(cpu);
1236 }
1237 return -ENOSYS;
1238}
1239
1240static inline int s390_get_memslot_count(KVMState *s)
1241{
1242 if (kvm_enabled()) {
1243 return kvm_s390_get_memslot_count(s);
1244 } else {
1245 return MAX_AVAIL_SLOTS;
1246 }
1247}
1248
1249void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
1250 uint32_t io_int_parm, uint32_t io_int_word);
1251void s390_crw_mchk(void);
1252
1253static inline int s390_assign_subch_ioeventfd(EventNotifier *notifier,
1254 uint32_t sch_id, int vq,
1255 bool assign)
1256{
1257 return kvm_s390_assign_subch_ioeventfd(notifier, sch_id, vq, assign);
1258}
1259
1260static inline void s390_crypto_reset(void)
1261{
1262 if (kvm_enabled()) {
1263 kvm_s390_crypto_reset();
1264 }
1265}
1266
1267#ifdef CONFIG_KVM
1268static inline bool vregs_needed(void *opaque)
1269{
1270 if (kvm_enabled()) {
1271 return kvm_check_extension(kvm_state, KVM_CAP_S390_VECTOR_REGISTERS);
1272 }
1273 return 0;
1274}
1275#else
1276static inline bool vregs_needed(void *opaque)
1277{
1278 return 0;
1279}
1280#endif
1281
1282
1283
1284
1285#define MCIC_SC_SD 0x8000000000000000ULL
1286#define MCIC_SC_PD 0x4000000000000000ULL
1287#define MCIC_SC_SR 0x2000000000000000ULL
1288#define MCIC_SC_CD 0x0800000000000000ULL
1289#define MCIC_SC_ED 0x0400000000000000ULL
1290#define MCIC_SC_DG 0x0100000000000000ULL
1291#define MCIC_SC_W 0x0080000000000000ULL
1292#define MCIC_SC_CP 0x0040000000000000ULL
1293#define MCIC_SC_SP 0x0020000000000000ULL
1294#define MCIC_SC_CK 0x0010000000000000ULL
1295
1296
1297#define MCIC_SCM_B 0x0002000000000000ULL
1298#define MCIC_SCM_DA 0x0000000020000000ULL
1299#define MCIC_SCM_AP 0x0000000000080000ULL
1300
1301
1302#define MCIC_SE_SE 0x0000800000000000ULL
1303#define MCIC_SE_SC 0x0000400000000000ULL
1304#define MCIC_SE_KE 0x0000200000000000ULL
1305#define MCIC_SE_DS 0x0000100000000000ULL
1306#define MCIC_SE_IE 0x0000000080000000ULL
1307
1308
1309#define MCIC_VB_WP 0x0000080000000000ULL
1310#define MCIC_VB_MS 0x0000040000000000ULL
1311#define MCIC_VB_PM 0x0000020000000000ULL
1312#define MCIC_VB_IA 0x0000010000000000ULL
1313#define MCIC_VB_FA 0x0000008000000000ULL
1314#define MCIC_VB_VR 0x0000004000000000ULL
1315#define MCIC_VB_EC 0x0000002000000000ULL
1316#define MCIC_VB_FP 0x0000001000000000ULL
1317#define MCIC_VB_GR 0x0000000800000000ULL
1318#define MCIC_VB_CR 0x0000000400000000ULL
1319#define MCIC_VB_ST 0x0000000100000000ULL
1320#define MCIC_VB_AR 0x0000000040000000ULL
1321#define MCIC_VB_PR 0x0000000000200000ULL
1322#define MCIC_VB_FC 0x0000000000100000ULL
1323#define MCIC_VB_CT 0x0000000000020000ULL
1324#define MCIC_VB_CC 0x0000000000010000ULL
1325
1326#endif
1327
