LXR qemu/target-s390x/ioinst.h

   1/*
   2 * S/390 channel I/O instructions
   3 *
   4 * Copyright 2012 IBM Corp.
   5 * Author(s): Cornelia Huck <cornelia.huck@de.ibm.com>
   6 *
   7 * This work is licensed under the terms of the GNU GPL, version 2 or (at
   8 * your option) any later version. See the COPYING file in the top-level
   9 * directory.
  10*/
  11
  12#ifndef IOINST_S390X_H
  13#define IOINST_S390X_H
  14/*
  15 * Channel I/O related definitions, as defined in the Principles
  16 * Of Operation (and taken from the Linux implementation).
  17 */
  18
  19/* subchannel status word (command mode only) */
  20typedef struct SCSW {
  21    uint16_t flags;
  22    uint16_t ctrl;
  23    uint32_t cpa;
  24    uint8_t dstat;
  25    uint8_t cstat;
  26    uint16_t count;
  27} QEMU_PACKED SCSW;
  28
  29#define SCSW_FLAGS_MASK_KEY 0xf000
  30#define SCSW_FLAGS_MASK_SCTL 0x0800
  31#define SCSW_FLAGS_MASK_ESWF 0x0400
  32#define SCSW_FLAGS_MASK_CC 0x0300
  33#define SCSW_FLAGS_MASK_FMT 0x0080
  34#define SCSW_FLAGS_MASK_PFCH 0x0040
  35#define SCSW_FLAGS_MASK_ISIC 0x0020
  36#define SCSW_FLAGS_MASK_ALCC 0x0010
  37#define SCSW_FLAGS_MASK_SSI 0x0008
  38#define SCSW_FLAGS_MASK_ZCC 0x0004
  39#define SCSW_FLAGS_MASK_ECTL 0x0002
  40#define SCSW_FLAGS_MASK_PNO 0x0001
  41
  42#define SCSW_CTRL_MASK_FCTL 0x7000
  43#define SCSW_CTRL_MASK_ACTL 0x0fe0
  44#define SCSW_CTRL_MASK_STCTL 0x001f
  45
  46#define SCSW_FCTL_CLEAR_FUNC 0x1000
  47#define SCSW_FCTL_HALT_FUNC 0x2000
  48#define SCSW_FCTL_START_FUNC 0x4000
  49
  50#define SCSW_ACTL_SUSP 0x0020
  51#define SCSW_ACTL_DEVICE_ACTIVE 0x0040
  52#define SCSW_ACTL_SUBCH_ACTIVE 0x0080
  53#define SCSW_ACTL_CLEAR_PEND 0x0100
  54#define SCSW_ACTL_HALT_PEND  0x0200
  55#define SCSW_ACTL_START_PEND 0x0400
  56#define SCSW_ACTL_RESUME_PEND 0x0800
  57
  58#define SCSW_STCTL_STATUS_PEND 0x0001
  59#define SCSW_STCTL_SECONDARY 0x0002
  60#define SCSW_STCTL_PRIMARY 0x0004
  61#define SCSW_STCTL_INTERMEDIATE 0x0008
  62#define SCSW_STCTL_ALERT 0x0010
  63
  64#define SCSW_DSTAT_ATTENTION     0x80
  65#define SCSW_DSTAT_STAT_MOD      0x40
  66#define SCSW_DSTAT_CU_END        0x20
  67#define SCSW_DSTAT_BUSY          0x10
  68#define SCSW_DSTAT_CHANNEL_END   0x08
  69#define SCSW_DSTAT_DEVICE_END    0x04
  70#define SCSW_DSTAT_UNIT_CHECK    0x02
  71#define SCSW_DSTAT_UNIT_EXCEP    0x01
  72
  73#define SCSW_CSTAT_PCI           0x80
  74#define SCSW_CSTAT_INCORR_LEN    0x40
  75#define SCSW_CSTAT_PROG_CHECK    0x20
  76#define SCSW_CSTAT_PROT_CHECK    0x10
  77#define SCSW_CSTAT_DATA_CHECK    0x08
  78#define SCSW_CSTAT_CHN_CTRL_CHK  0x04
  79#define SCSW_CSTAT_INTF_CTRL_CHK 0x02
  80#define SCSW_CSTAT_CHAIN_CHECK   0x01
  81
  82/* path management control word */
  83typedef struct PMCW {
  84    uint32_t intparm;
  85    uint16_t flags;
  86    uint16_t devno;
  87    uint8_t  lpm;
  88    uint8_t  pnom;
  89    uint8_t  lpum;
  90    uint8_t  pim;
  91    uint16_t mbi;
  92    uint8_t  pom;
  93    uint8_t  pam;
  94    uint8_t  chpid[8];
  95    uint32_t chars;
  96} QEMU_PACKED PMCW;
  97
  98#define PMCW_FLAGS_MASK_QF 0x8000
  99#define PMCW_FLAGS_MASK_W 0x4000
 100#define PMCW_FLAGS_MASK_ISC 0x3800
 101#define PMCW_FLAGS_MASK_ENA 0x0080
 102#define PMCW_FLAGS_MASK_LM 0x0060
 103#define PMCW_FLAGS_MASK_MME 0x0018
 104#define PMCW_FLAGS_MASK_MP 0x0004
 105#define PMCW_FLAGS_MASK_TF 0x0002
 106#define PMCW_FLAGS_MASK_DNV 0x0001
 107#define PMCW_FLAGS_MASK_INVALID 0x0700
 108
 109#define PMCW_CHARS_MASK_ST 0x00e00000
 110#define PMCW_CHARS_MASK_MBFC 0x00000004
 111#define PMCW_CHARS_MASK_XMWME 0x00000002
 112#define PMCW_CHARS_MASK_CSENSE 0x00000001
 113#define PMCW_CHARS_MASK_INVALID 0xff1ffff8
 114
 115/* subchannel information block */
 116typedef struct SCHIB {
 117    PMCW pmcw;
 118    SCSW scsw;
 119    uint64_t mba;
 120    uint8_t mda[4];
 121} QEMU_PACKED SCHIB;
 122
 123/* interruption response block */
 124typedef struct IRB {
 125    SCSW scsw;
 126    uint32_t esw[5];
 127    uint32_t ecw[8];
 128    uint32_t emw[8];
 129} QEMU_PACKED IRB;
 130
 131/* operation request block */
 132typedef struct ORB {
 133    uint32_t intparm;
 134    uint16_t ctrl0;
 135    uint8_t lpm;
 136    uint8_t ctrl1;
 137    uint32_t cpa;
 138} QEMU_PACKED ORB;
 139
 140#define ORB_CTRL0_MASK_KEY 0xf000
 141#define ORB_CTRL0_MASK_SPND 0x0800
 142#define ORB_CTRL0_MASK_STR 0x0400
 143#define ORB_CTRL0_MASK_MOD 0x0200
 144#define ORB_CTRL0_MASK_SYNC 0x0100
 145#define ORB_CTRL0_MASK_FMT 0x0080
 146#define ORB_CTRL0_MASK_PFCH 0x0040
 147#define ORB_CTRL0_MASK_ISIC 0x0020
 148#define ORB_CTRL0_MASK_ALCC 0x0010
 149#define ORB_CTRL0_MASK_SSIC 0x0008
 150#define ORB_CTRL0_MASK_C64 0x0002
 151#define ORB_CTRL0_MASK_I2K 0x0001
 152#define ORB_CTRL0_MASK_INVALID 0x0004
 153
 154#define ORB_CTRL1_MASK_ILS 0x80
 155#define ORB_CTRL1_MASK_MIDAW 0x40
 156#define ORB_CTRL1_MASK_ORBX 0x01
 157#define ORB_CTRL1_MASK_INVALID 0x3e
 158
 159/* channel command word (type 0) */
 160typedef struct CCW0 {
 161        uint8_t cmd_code;
 162        uint8_t cda0;
 163        uint16_t cda1;
 164        uint8_t flags;
 165        uint8_t reserved;
 166        uint16_t count;
 167} QEMU_PACKED CCW0;
 168
 169/* channel command word (type 1) */
 170typedef struct CCW1 {
 171    uint8_t cmd_code;
 172    uint8_t flags;
 173    uint16_t count;
 174    uint32_t cda;
 175} QEMU_PACKED CCW1;
 176
 177#define CCW_FLAG_DC              0x80
 178#define CCW_FLAG_CC              0x40
 179#define CCW_FLAG_SLI             0x20
 180#define CCW_FLAG_SKIP            0x10
 181#define CCW_FLAG_PCI             0x08
 182#define CCW_FLAG_IDA             0x04
 183#define CCW_FLAG_SUSPEND         0x02
 184
 185#define CCW_CMD_NOOP             0x03
 186#define CCW_CMD_BASIC_SENSE      0x04
 187#define CCW_CMD_TIC              0x08
 188#define CCW_CMD_SENSE_ID         0xe4
 189
 190typedef struct CRW {
 191    uint16_t flags;
 192    uint16_t rsid;
 193} QEMU_PACKED CRW;
 194
 195#define CRW_FLAGS_MASK_S 0x4000
 196#define CRW_FLAGS_MASK_R 0x2000
 197#define CRW_FLAGS_MASK_C 0x1000
 198#define CRW_FLAGS_MASK_RSC 0x0f00
 199#define CRW_FLAGS_MASK_A 0x0080
 200#define CRW_FLAGS_MASK_ERC 0x003f
 201
 202#define CRW_ERC_INIT 0x02
 203#define CRW_ERC_IPI  0x04
 204
 205#define CRW_RSC_SUBCH 0x3
 206#define CRW_RSC_CHP   0x4
 207#define CRW_RSC_CSS   0xb
 208
 209/* I/O interruption code */
 210typedef struct IOIntCode {
 211    uint32_t subsys_id;
 212    uint32_t intparm;
 213    uint32_t interrupt_id;
 214} QEMU_PACKED IOIntCode;
 215
 216/* schid disintegration */
 217#define IOINST_SCHID_ONE(_schid)   ((_schid & 0x00010000) >> 16)
 218#define IOINST_SCHID_M(_schid)     ((_schid & 0x00080000) >> 19)
 219#define IOINST_SCHID_CSSID(_schid) ((_schid & 0xff000000) >> 24)
 220#define IOINST_SCHID_SSID(_schid)  ((_schid & 0x00060000) >> 17)
 221#define IOINST_SCHID_NR(_schid)    (_schid & 0x0000ffff)
 222
 223#define IO_INT_WORD_ISC(_int_word) ((_int_word & 0x38000000) >> 27)
 224#define ISC_TO_ISC_BITS(_isc)      ((0x80 >> _isc) << 24)
 225
 226#define IO_INT_WORD_AI 0x80000000
 227
 228int ioinst_disassemble_sch_ident(uint32_t value, int *m, int *cssid, int *ssid,
 229                                 int *schid);
 230void ioinst_handle_xsch(S390CPU *cpu, uint64_t reg1);
 231void ioinst_handle_csch(S390CPU *cpu, uint64_t reg1);
 232void ioinst_handle_hsch(S390CPU *cpu, uint64_t reg1);
 233void ioinst_handle_msch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 234void ioinst_handle_ssch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 235void ioinst_handle_stcrw(S390CPU *cpu, uint32_t ipb);
 236void ioinst_handle_stsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 237int ioinst_handle_tsch(S390CPU *cpu, uint64_t reg1, uint32_t ipb);
 238void ioinst_handle_chsc(S390CPU *cpu, uint32_t ipb);
 239int ioinst_handle_tpi(S390CPU *cpu, uint32_t ipb);
 240void ioinst_handle_schm(S390CPU *cpu, uint64_t reg1, uint64_t reg2,
 241                        uint32_t ipb);
 242void ioinst_handle_rsch(S390CPU *cpu, uint64_t reg1);
 243void ioinst_handle_rchp(S390CPU *cpu, uint64_t reg1);
 244void ioinst_handle_sal(S390CPU *cpu, uint64_t reg1);
 245
 246#endif
 247