LXR qemu/target-sparc/cpu.h

   1#ifndef CPU_SPARC_H
   2#define CPU_SPARC_H
   3
   4#include "qemu-common.h"
   5#include "qemu/bswap.h"
   6
   7#define ALIGNED_ONLY
   8
   9#if !defined(TARGET_SPARC64)
  10#define TARGET_LONG_BITS 32
  11#define TARGET_DPREGS 16
  12#define TARGET_PAGE_BITS 12 /* 4k */
  13#define TARGET_PHYS_ADDR_SPACE_BITS 36
  14#define TARGET_VIRT_ADDR_SPACE_BITS 32
  15#else
  16#define TARGET_LONG_BITS 64
  17#define TARGET_DPREGS 32
  18#define TARGET_PAGE_BITS 13 /* 8k */
  19#define TARGET_PHYS_ADDR_SPACE_BITS 41
  20# ifdef TARGET_ABI32
  21#  define TARGET_VIRT_ADDR_SPACE_BITS 32
  22# else
  23#  define TARGET_VIRT_ADDR_SPACE_BITS 44
  24# endif
  25#endif
  26
  27#define CPUArchState struct CPUSPARCState
  28
  29#include "exec/cpu-defs.h"
  30
  31#include "fpu/softfloat.h"
  32
  33/*#define EXCP_INTERRUPT 0x100*/
  34
  35/* trap definitions */
  36#ifndef TARGET_SPARC64
  37#define TT_TFAULT   0x01
  38#define TT_ILL_INSN 0x02
  39#define TT_PRIV_INSN 0x03
  40#define TT_NFPU_INSN 0x04
  41#define TT_WIN_OVF  0x05
  42#define TT_WIN_UNF  0x06
  43#define TT_UNALIGNED 0x07
  44#define TT_FP_EXCP  0x08
  45#define TT_DFAULT   0x09
  46#define TT_TOVF     0x0a
  47#define TT_EXTINT   0x10
  48#define TT_CODE_ACCESS 0x21
  49#define TT_UNIMP_FLUSH 0x25
  50#define TT_DATA_ACCESS 0x29
  51#define TT_DIV_ZERO 0x2a
  52#define TT_NCP_INSN 0x24
  53#define TT_TRAP     0x80
  54#else
  55#define TT_POWER_ON_RESET 0x01
  56#define TT_TFAULT   0x08
  57#define TT_CODE_ACCESS 0x0a
  58#define TT_ILL_INSN 0x10
  59#define TT_UNIMP_FLUSH TT_ILL_INSN
  60#define TT_PRIV_INSN 0x11
  61#define TT_NFPU_INSN 0x20
  62#define TT_FP_EXCP  0x21
  63#define TT_TOVF     0x23
  64#define TT_CLRWIN   0x24
  65#define TT_DIV_ZERO 0x28
  66#define TT_DFAULT   0x30
  67#define TT_DATA_ACCESS 0x32
  68#define TT_UNALIGNED 0x34
  69#define TT_PRIV_ACT 0x37
  70#define TT_EXTINT   0x40
  71#define TT_IVEC     0x60
  72#define TT_TMISS    0x64
  73#define TT_DMISS    0x68
  74#define TT_DPROT    0x6c
  75#define TT_SPILL    0x80
  76#define TT_FILL     0xc0
  77#define TT_WOTHER   (1 << 5)
  78#define TT_TRAP     0x100
  79#endif
  80
  81#define PSR_NEG_SHIFT 23
  82#define PSR_NEG   (1 << PSR_NEG_SHIFT)
  83#define PSR_ZERO_SHIFT 22
  84#define PSR_ZERO  (1 << PSR_ZERO_SHIFT)
  85#define PSR_OVF_SHIFT 21
  86#define PSR_OVF   (1 << PSR_OVF_SHIFT)
  87#define PSR_CARRY_SHIFT 20
  88#define PSR_CARRY (1 << PSR_CARRY_SHIFT)
  89#define PSR_ICC   (PSR_NEG|PSR_ZERO|PSR_OVF|PSR_CARRY)
  90#if !defined(TARGET_SPARC64)
  91#define PSR_EF    (1<<12)
  92#define PSR_PIL   0xf00
  93#define PSR_S     (1<<7)
  94#define PSR_PS    (1<<6)
  95#define PSR_ET    (1<<5)
  96#define PSR_CWP   0x1f
  97#endif
  98
  99#define CC_SRC (env->cc_src)
 100#define CC_SRC2 (env->cc_src2)
 101#define CC_DST (env->cc_dst)
 102#define CC_OP  (env->cc_op)
 103
 104enum {
 105    CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */
 106    CC_OP_FLAGS,   /* all cc are back in status register */
 107    CC_OP_DIV,     /* modify N, Z and V, C = 0*/
 108    CC_OP_ADD,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 109    CC_OP_ADDX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 110    CC_OP_TADD,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 111    CC_OP_TADDTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 112    CC_OP_SUB,     /* modify all flags, CC_DST = res, CC_SRC = src1 */
 113    CC_OP_SUBX,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 114    CC_OP_TSUB,    /* modify all flags, CC_DST = res, CC_SRC = src1 */
 115    CC_OP_TSUBTV,  /* modify all flags except V, CC_DST = res, CC_SRC = src1 */
 116    CC_OP_LOGIC,   /* modify N and Z, C = V = 0, CC_DST = res */
 117    CC_OP_NB,
 118};
 119
 120/* Trap base register */
 121#define TBR_BASE_MASK 0xfffff000
 122
 123#if defined(TARGET_SPARC64)
 124#define PS_TCT   (1<<12) /* UA2007, impl.dep. trap on control transfer */
 125#define PS_IG    (1<<11) /* v9, zero on UA2007 */
 126#define PS_MG    (1<<10) /* v9, zero on UA2007 */
 127#define PS_CLE   (1<<9) /* UA2007 */
 128#define PS_TLE   (1<<8) /* UA2007 */
 129#define PS_RMO   (1<<7)
 130#define PS_RED   (1<<5) /* v9, zero on UA2007 */
 131#define PS_PEF   (1<<4) /* enable fpu */
 132#define PS_AM    (1<<3) /* address mask */
 133#define PS_PRIV  (1<<2)
 134#define PS_IE    (1<<1)
 135#define PS_AG    (1<<0) /* v9, zero on UA2007 */
 136
 137#define FPRS_FEF (1<<2)
 138
 139#define HS_PRIV  (1<<2)
 140#endif
 141
 142/* Fcc */
 143#define FSR_RD1        (1ULL << 31)
 144#define FSR_RD0        (1ULL << 30)
 145#define FSR_RD_MASK    (FSR_RD1 | FSR_RD0)
 146#define FSR_RD_NEAREST 0
 147#define FSR_RD_ZERO    FSR_RD0
 148#define FSR_RD_POS     FSR_RD1
 149#define FSR_RD_NEG     (FSR_RD1 | FSR_RD0)
 150
 151#define FSR_NVM   (1ULL << 27)
 152#define FSR_OFM   (1ULL << 26)
 153#define FSR_UFM   (1ULL << 25)
 154#define FSR_DZM   (1ULL << 24)
 155#define FSR_NXM   (1ULL << 23)
 156#define FSR_TEM_MASK (FSR_NVM | FSR_OFM | FSR_UFM | FSR_DZM | FSR_NXM)
 157
 158#define FSR_NVA   (1ULL << 9)
 159#define FSR_OFA   (1ULL << 8)
 160#define FSR_UFA   (1ULL << 7)
 161#define FSR_DZA   (1ULL << 6)
 162#define FSR_NXA   (1ULL << 5)
 163#define FSR_AEXC_MASK (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA)
 164
 165#define FSR_NVC   (1ULL << 4)
 166#define FSR_OFC   (1ULL << 3)
 167#define FSR_UFC   (1ULL << 2)
 168#define FSR_DZC   (1ULL << 1)
 169#define FSR_NXC   (1ULL << 0)
 170#define FSR_CEXC_MASK (FSR_NVC | FSR_OFC | FSR_UFC | FSR_DZC | FSR_NXC)
 171
 172#define FSR_FTT2   (1ULL << 16)
 173#define FSR_FTT1   (1ULL << 15)
 174#define FSR_FTT0   (1ULL << 14)
 175//gcc warns about constant overflow for ~FSR_FTT_MASK
 176//#define FSR_FTT_MASK (FSR_FTT2 | FSR_FTT1 | FSR_FTT0)
 177#ifdef TARGET_SPARC64
 178#define FSR_FTT_NMASK      0xfffffffffffe3fffULL
 179#define FSR_FTT_CEXC_NMASK 0xfffffffffffe3fe0ULL
 180#define FSR_LDFSR_OLDMASK  0x0000003f000fc000ULL
 181#define FSR_LDXFSR_MASK    0x0000003fcfc00fffULL
 182#define FSR_LDXFSR_OLDMASK 0x00000000000fc000ULL
 183#else
 184#define FSR_FTT_NMASK      0xfffe3fffULL
 185#define FSR_FTT_CEXC_NMASK 0xfffe3fe0ULL
 186#define FSR_LDFSR_OLDMASK  0x000fc000ULL
 187#endif
 188#define FSR_LDFSR_MASK     0xcfc00fffULL
 189#define FSR_FTT_IEEE_EXCP (1ULL << 14)
 190#define FSR_FTT_UNIMPFPOP (3ULL << 14)
 191#define FSR_FTT_SEQ_ERROR (4ULL << 14)
 192#define FSR_FTT_INVAL_FPR (6ULL << 14)
 193
 194#define FSR_FCC1_SHIFT 11
 195#define FSR_FCC1  (1ULL << FSR_FCC1_SHIFT)
 196#define FSR_FCC0_SHIFT 10
 197#define FSR_FCC0  (1ULL << FSR_FCC0_SHIFT)
 198
 199/* MMU */
 200#define MMU_E     (1<<0)
 201#define MMU_NF    (1<<1)
 202
 203#define PTE_ENTRYTYPE_MASK 3
 204#define PTE_ACCESS_MASK    0x1c
 205#define PTE_ACCESS_SHIFT   2
 206#define PTE_PPN_SHIFT      7
 207#define PTE_ADDR_MASK      0xffffff00
 208
 209#define PG_ACCESSED_BIT 5
 210#define PG_MODIFIED_BIT 6
 211#define PG_CACHE_BIT    7
 212
 213#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
 214#define PG_MODIFIED_MASK (1 << PG_MODIFIED_BIT)
 215#define PG_CACHE_MASK    (1 << PG_CACHE_BIT)
 216
 217/* 3 <= NWINDOWS <= 32. */
 218#define MIN_NWINDOWS 3
 219#define MAX_NWINDOWS 32
 220
 221#if !defined(TARGET_SPARC64)
 222#define NB_MMU_MODES 2
 223#else
 224#define NB_MMU_MODES 6
 225typedef struct trap_state {
 226    uint64_t tpc;
 227    uint64_t tnpc;
 228    uint64_t tstate;
 229    uint32_t tt;
 230} trap_state;
 231#endif
 232#define TARGET_INSN_START_EXTRA_WORDS 1
 233
 234typedef struct sparc_def_t {
 235    const char *name;
 236    target_ulong iu_version;
 237    uint32_t fpu_version;
 238    uint32_t mmu_version;
 239    uint32_t mmu_bm;
 240    uint32_t mmu_ctpr_mask;
 241    uint32_t mmu_cxr_mask;
 242    uint32_t mmu_sfsr_mask;
 243    uint32_t mmu_trcr_mask;
 244    uint32_t mxcc_version;
 245    uint32_t features;
 246    uint32_t nwindows;
 247    uint32_t maxtl;
 248} sparc_def_t;
 249
 250#define CPU_FEATURE_FLOAT        (1 << 0)
 251#define CPU_FEATURE_FLOAT128     (1 << 1)
 252#define CPU_FEATURE_SWAP         (1 << 2)
 253#define CPU_FEATURE_MUL          (1 << 3)
 254#define CPU_FEATURE_DIV          (1 << 4)
 255#define CPU_FEATURE_FLUSH        (1 << 5)
 256#define CPU_FEATURE_FSQRT        (1 << 6)
 257#define CPU_FEATURE_FMUL         (1 << 7)
 258#define CPU_FEATURE_VIS1         (1 << 8)
 259#define CPU_FEATURE_VIS2         (1 << 9)
 260#define CPU_FEATURE_FSMULD       (1 << 10)
 261#define CPU_FEATURE_HYPV         (1 << 11)
 262#define CPU_FEATURE_CMT          (1 << 12)
 263#define CPU_FEATURE_GL           (1 << 13)
 264#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
 265#define CPU_FEATURE_ASR17        (1 << 15)
 266#define CPU_FEATURE_CACHE_CTRL   (1 << 16)
 267#define CPU_FEATURE_POWERDOWN    (1 << 17)
 268#define CPU_FEATURE_CASA         (1 << 18)
 269
 270#ifndef TARGET_SPARC64
 271#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 272                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 273                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 274                              CPU_FEATURE_FMUL | CPU_FEATURE_FSMULD)
 275#else
 276#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP |  \
 277                              CPU_FEATURE_MUL | CPU_FEATURE_DIV |     \
 278                              CPU_FEATURE_FLUSH | CPU_FEATURE_FSQRT | \
 279                              CPU_FEATURE_FMUL | CPU_FEATURE_VIS1 |   \
 280                              CPU_FEATURE_VIS2 | CPU_FEATURE_FSMULD | \
 281                              CPU_FEATURE_CASA)
 282enum {
 283    mmu_us_12, // Ultrasparc < III (64 entry TLB)
 284    mmu_us_3,  // Ultrasparc III (512 entry TLB)
 285    mmu_us_4,  // Ultrasparc IV (several TLBs, 32 and 256MB pages)
 286    mmu_sun4v, // T1, T2
 287};
 288#endif
 289
 290#define TTE_VALID_BIT       (1ULL << 63)
 291#define TTE_NFO_BIT         (1ULL << 60)
 292#define TTE_USED_BIT        (1ULL << 41)
 293#define TTE_LOCKED_BIT      (1ULL <<  6)
 294#define TTE_SIDEEFFECT_BIT  (1ULL <<  3)
 295#define TTE_PRIV_BIT        (1ULL <<  2)
 296#define TTE_W_OK_BIT        (1ULL <<  1)
 297#define TTE_GLOBAL_BIT      (1ULL <<  0)
 298
 299#define TTE_IS_VALID(tte)   ((tte) & TTE_VALID_BIT)
 300#define TTE_IS_NFO(tte)     ((tte) & TTE_NFO_BIT)
 301#define TTE_IS_USED(tte)    ((tte) & TTE_USED_BIT)
 302#define TTE_IS_LOCKED(tte)  ((tte) & TTE_LOCKED_BIT)
 303#define TTE_IS_SIDEEFFECT(tte) ((tte) & TTE_SIDEEFFECT_BIT)
 304#define TTE_IS_PRIV(tte)    ((tte) & TTE_PRIV_BIT)
 305#define TTE_IS_W_OK(tte)    ((tte) & TTE_W_OK_BIT)
 306#define TTE_IS_GLOBAL(tte)  ((tte) & TTE_GLOBAL_BIT)
 307
 308#define TTE_SET_USED(tte)   ((tte) |= TTE_USED_BIT)
 309#define TTE_SET_UNUSED(tte) ((tte) &= ~TTE_USED_BIT)
 310
 311#define TTE_PGSIZE(tte)     (((tte) >> 61) & 3ULL)
 312#define TTE_PA(tte)         ((tte) & 0x1ffffffe000ULL)
 313
 314#define SFSR_NF_BIT         (1ULL << 24)   /* JPS1 NoFault */
 315#define SFSR_TM_BIT         (1ULL << 15)   /* JPS1 TLB Miss */
 316#define SFSR_FT_VA_IMMU_BIT (1ULL << 13)   /* USIIi VA out of range (IMMU) */
 317#define SFSR_FT_VA_DMMU_BIT (1ULL << 12)   /* USIIi VA out of range (DMMU) */
 318#define SFSR_FT_NFO_BIT     (1ULL << 11)   /* NFO page access */
 319#define SFSR_FT_ILL_BIT     (1ULL << 10)   /* illegal LDA/STA ASI */
 320#define SFSR_FT_ATOMIC_BIT  (1ULL <<  9)   /* atomic op on noncacheable area */
 321#define SFSR_FT_NF_E_BIT    (1ULL <<  8)   /* NF access on side effect area */
 322#define SFSR_FT_PRIV_BIT    (1ULL <<  7)   /* privilege violation */
 323#define SFSR_PR_BIT         (1ULL <<  3)   /* privilege mode */
 324#define SFSR_WRITE_BIT      (1ULL <<  2)   /* write access mode */
 325#define SFSR_OW_BIT         (1ULL <<  1)   /* status overwritten */
 326#define SFSR_VALID_BIT      (1ULL <<  0)   /* status valid */
 327
 328#define SFSR_ASI_SHIFT      16             /* 23:16 ASI value */
 329#define SFSR_ASI_MASK       (0xffULL << SFSR_ASI_SHIFT)
 330#define SFSR_CT_PRIMARY     (0ULL <<  4)   /* 5:4 context type */
 331#define SFSR_CT_SECONDARY   (1ULL <<  4)
 332#define SFSR_CT_NUCLEUS     (2ULL <<  4)
 333#define SFSR_CT_NOTRANS     (3ULL <<  4)
 334#define SFSR_CT_MASK        (3ULL <<  4)
 335
 336/* Leon3 cache control */
 337
 338/* Cache control: emulate the behavior of cache control registers but without
 339   any effect on the emulated */
 340
 341#define CACHE_STATE_MASK 0x3
 342#define CACHE_DISABLED   0x0
 343#define CACHE_FROZEN     0x1
 344#define CACHE_ENABLED    0x3
 345
 346/* Cache Control register fields */
 347
 348#define CACHE_CTRL_IF (1 <<  4)  /* Instruction Cache Freeze on Interrupt */
 349#define CACHE_CTRL_DF (1 <<  5)  /* Data Cache Freeze on Interrupt */
 350#define CACHE_CTRL_DP (1 << 14)  /* Data cache flush pending */
 351#define CACHE_CTRL_IP (1 << 15)  /* Instruction cache flush pending */
 352#define CACHE_CTRL_IB (1 << 16)  /* Instruction burst fetch */
 353#define CACHE_CTRL_FI (1 << 21)  /* Flush Instruction cache (Write only) */
 354#define CACHE_CTRL_FD (1 << 22)  /* Flush Data cache (Write only) */
 355#define CACHE_CTRL_DS (1 << 23)  /* Data cache snoop enable */
 356
 357typedef struct SparcTLBEntry {
 358    uint64_t tag;
 359    uint64_t tte;
 360} SparcTLBEntry;
 361
 362struct CPUTimer
 363{
 364    const char *name;
 365    uint32_t    frequency;
 366    uint32_t    disabled;
 367    uint64_t    disabled_mask;
 368    uint32_t    npt;
 369    uint64_t    npt_mask;
 370    int64_t     clock_offset;
 371    QEMUTimer  *qtimer;
 372};
 373
 374typedef struct CPUTimer CPUTimer;
 375
 376typedef struct CPUSPARCState CPUSPARCState;
 377
 378struct CPUSPARCState {
 379    target_ulong gregs[8]; /* general registers */
 380    target_ulong *regwptr; /* pointer to current register window */
 381    target_ulong pc;       /* program counter */
 382    target_ulong npc;      /* next program counter */
 383    target_ulong y;        /* multiply/divide register */
 384
 385    /* emulator internal flags handling */
 386    target_ulong cc_src, cc_src2;
 387    target_ulong cc_dst;
 388    uint32_t cc_op;
 389
 390    target_ulong cond; /* conditional branch result (XXX: save it in a
 391                          temporary register when possible) */
 392
 393    uint32_t psr;      /* processor state register */
 394    target_ulong fsr;      /* FPU state register */
 395    CPU_DoubleU fpr[TARGET_DPREGS];  /* floating point registers */
 396    uint32_t cwp;      /* index of current register window (extracted
 397                          from PSR) */
 398#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
 399    uint32_t wim;      /* window invalid mask */
 400#endif
 401    target_ulong tbr;  /* trap base register */
 402#if !defined(TARGET_SPARC64)
 403    int      psrs;     /* supervisor mode (extracted from PSR) */
 404    int      psrps;    /* previous supervisor mode */
 405    int      psret;    /* enable traps */
 406#endif
 407    uint32_t psrpil;   /* interrupt blocking level */
 408    uint32_t pil_in;   /* incoming interrupt level bitmap */
 409#if !defined(TARGET_SPARC64)
 410    int      psref;    /* enable fpu */
 411#endif
 412    int interrupt_index;
 413    /* NOTE: we allow 8 more registers to handle wrapping */
 414    target_ulong regbase[MAX_NWINDOWS * 16 + 8];
 415
 416    CPU_COMMON
 417
 418    /* Fields from here on are preserved across CPU reset. */
 419    target_ulong version;
 420    uint32_t nwindows;
 421
 422    /* MMU regs */
 423#if defined(TARGET_SPARC64)
 424    uint64_t lsu;
 425#define DMMU_E 0x8
 426#define IMMU_E 0x4
 427    //typedef struct SparcMMU
 428    union {
 429        uint64_t immuregs[16];
 430        struct {
 431            uint64_t tsb_tag_target;
 432            uint64_t unused_mmu_primary_context;   // use DMMU
 433            uint64_t unused_mmu_secondary_context; // use DMMU
 434            uint64_t sfsr;
 435            uint64_t sfar;
 436            uint64_t tsb;
 437            uint64_t tag_access;
 438        } immu;
 439    };
 440    union {
 441        uint64_t dmmuregs[16];
 442        struct {
 443            uint64_t tsb_tag_target;
 444            uint64_t mmu_primary_context;
 445            uint64_t mmu_secondary_context;
 446            uint64_t sfsr;
 447            uint64_t sfar;
 448            uint64_t tsb;
 449            uint64_t tag_access;
 450        } dmmu;
 451    };
 452    SparcTLBEntry itlb[64];
 453    SparcTLBEntry dtlb[64];
 454    uint32_t mmu_version;
 455#else
 456    uint32_t mmuregs[32];
 457    uint64_t mxccdata[4];
 458    uint64_t mxccregs[8];
 459    uint32_t mmubpctrv, mmubpctrc, mmubpctrs;
 460    uint64_t mmubpaction;
 461    uint64_t mmubpregs[4];
 462    uint64_t prom_addr;
 463#endif
 464    /* temporary float registers */
 465    float128 qt0, qt1;
 466    float_status fp_status;
 467#if defined(TARGET_SPARC64)
 468#define MAXTL_MAX 8
 469#define MAXTL_MASK (MAXTL_MAX - 1)
 470    trap_state ts[MAXTL_MAX];
 471    uint32_t xcc;               /* Extended integer condition codes */
 472    uint32_t asi;
 473    uint32_t pstate;
 474    uint32_t tl;
 475    uint32_t maxtl;
 476    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
 477    uint64_t agregs[8]; /* alternate general registers */
 478    uint64_t bgregs[8]; /* backup for normal global registers */
 479    uint64_t igregs[8]; /* interrupt general registers */
 480    uint64_t mgregs[8]; /* mmu general registers */
 481    uint64_t fprs;
 482    uint64_t tick_cmpr, stick_cmpr;
 483    CPUTimer *tick, *stick;
 484#define TICK_NPT_MASK        0x8000000000000000ULL
 485#define TICK_INT_DIS         0x8000000000000000ULL
 486    uint64_t gsr;
 487    uint32_t gl; // UA2005
 488    /* UA 2005 hyperprivileged registers */
 489    uint64_t hpstate, htstate[MAXTL_MAX], hintp, htba, hver, hstick_cmpr, ssr;
 490    CPUTimer *hstick; // UA 2005
 491    /* Interrupt vector registers */
 492    uint64_t ivec_status;
 493    uint64_t ivec_data[3];
 494    uint32_t softint;
 495#define SOFTINT_TIMER   1
 496#define SOFTINT_STIMER  (1 << 16)
 497#define SOFTINT_INTRMASK (0xFFFE)
 498#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
 499#endif
 500    sparc_def_t *def;
 501
 502    void *irq_manager;
 503    void (*qemu_irq_ack)(CPUSPARCState *env, void *irq_manager, int intno);
 504
 505    /* Leon3 cache control */
 506    uint32_t cache_control;
 507};
 508
 509#include "cpu-qom.h"
 510
 511#ifndef NO_CPU_IO_DEFS
 512/* cpu_init.c */
 513SPARCCPU *cpu_sparc_init(const char *cpu_model);
 514void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu);
 515void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 516/* mmu_helper.c */
 517int sparc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
 518                               int mmu_idx);
 519target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev);
 520void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env);
 521
 522#if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY)
 523int sparc_cpu_memory_rw_debug(CPUState *cpu, vaddr addr,
 524                              uint8_t *buf, int len, bool is_write);
 525#endif
 526
 527
 528/* translate.c */
 529void gen_intermediate_code_init(CPUSPARCState *env);
 530
 531/* cpu-exec.c */
 532int cpu_sparc_exec(CPUState *cpu);
 533
 534/* win_helper.c */
 535target_ulong cpu_get_psr(CPUSPARCState *env1);
 536void cpu_put_psr(CPUSPARCState *env1, target_ulong val);
 537void cpu_put_psr_raw(CPUSPARCState *env1, target_ulong val);
 538#ifdef TARGET_SPARC64
 539target_ulong cpu_get_ccr(CPUSPARCState *env1);
 540void cpu_put_ccr(CPUSPARCState *env1, target_ulong val);
 541target_ulong cpu_get_cwp64(CPUSPARCState *env1);
 542void cpu_put_cwp64(CPUSPARCState *env1, int cwp);
 543void cpu_change_pstate(CPUSPARCState *env1, uint32_t new_pstate);
 544#endif
 545int cpu_cwp_inc(CPUSPARCState *env1, int cwp);
 546int cpu_cwp_dec(CPUSPARCState *env1, int cwp);
 547void cpu_set_cwp(CPUSPARCState *env1, int new_cwp);
 548
 549/* int_helper.c */
 550void leon3_irq_manager(CPUSPARCState *env, void *irq_manager, int intno);
 551
 552/* sun4m.c, sun4u.c */
 553void cpu_check_irqs(CPUSPARCState *env);
 554
 555/* leon3.c */
 556void leon3_irq_ack(void *irq_manager, int intno);
 557
 558#if defined (TARGET_SPARC64)
 559
 560static inline int compare_masked(uint64_t x, uint64_t y, uint64_t mask)
 561{
 562    return (x & mask) == (y & mask);
 563}
 564
 565#define MMU_CONTEXT_BITS 13
 566#define MMU_CONTEXT_MASK ((1 << MMU_CONTEXT_BITS) - 1)
 567
 568static inline int tlb_compare_context(const SparcTLBEntry *tlb,
 569                                      uint64_t context)
 570{
 571    return compare_masked(context, tlb->tag, MMU_CONTEXT_MASK);
 572}
 573
 574#endif
 575#endif
 576
 577/* cpu-exec.c */
 578#if !defined(CONFIG_USER_ONLY)
 579void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr,
 580                                 bool is_write, bool is_exec, int is_asi,
 581                                 unsigned size);
 582#if defined(TARGET_SPARC64)
 583hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr,
 584                                           int mmu_idx);
 585#endif
 586#endif
 587int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc);
 588
 589#ifndef NO_CPU_IO_DEFS
 590#define cpu_init(cpu_model) CPU(cpu_sparc_init(cpu_model))
 591#endif
 592
 593#define cpu_exec cpu_sparc_exec
 594#define cpu_signal_handler cpu_sparc_signal_handler
 595#define cpu_list sparc_cpu_list
 596
 597/* MMU modes definitions */
 598#if defined (TARGET_SPARC64)
 599#define MMU_USER_IDX   0
 600#define MMU_MODE0_SUFFIX _user
 601#define MMU_USER_SECONDARY_IDX   1
 602#define MMU_MODE1_SUFFIX _user_secondary
 603#define MMU_KERNEL_IDX 2
 604#define MMU_MODE2_SUFFIX _kernel
 605#define MMU_KERNEL_SECONDARY_IDX 3
 606#define MMU_MODE3_SUFFIX _kernel_secondary
 607#define MMU_NUCLEUS_IDX 4
 608#define MMU_MODE4_SUFFIX _nucleus
 609#define MMU_HYPV_IDX   5
 610#define MMU_MODE5_SUFFIX _hypv
 611#else
 612#define MMU_USER_IDX   0
 613#define MMU_MODE0_SUFFIX _user
 614#define MMU_KERNEL_IDX 1
 615#define MMU_MODE1_SUFFIX _kernel
 616#endif
 617
 618#if defined (TARGET_SPARC64)
 619static inline int cpu_has_hypervisor(CPUSPARCState *env1)
 620{
 621    return env1->def->features & CPU_FEATURE_HYPV;
 622}
 623
 624static inline int cpu_hypervisor_mode(CPUSPARCState *env1)
 625{
 626    return cpu_has_hypervisor(env1) && (env1->hpstate & HS_PRIV);
 627}
 628
 629static inline int cpu_supervisor_mode(CPUSPARCState *env1)
 630{
 631    return env1->pstate & PS_PRIV;
 632}
 633#endif
 634
 635static inline int cpu_mmu_index(CPUSPARCState *env1, bool ifetch)
 636{
 637#if defined(CONFIG_USER_ONLY)
 638    return MMU_USER_IDX;
 639#elif !defined(TARGET_SPARC64)
 640    return env1->psrs;
 641#else
 642    if (env1->tl > 0) {
 643        return MMU_NUCLEUS_IDX;
 644    } else if (cpu_hypervisor_mode(env1)) {
 645        return MMU_HYPV_IDX;
 646    } else if (cpu_supervisor_mode(env1)) {
 647        return MMU_KERNEL_IDX;
 648    } else {
 649        return MMU_USER_IDX;
 650    }
 651#endif
 652}
 653
 654static inline int cpu_interrupts_enabled(CPUSPARCState *env1)
 655{
 656#if !defined (TARGET_SPARC64)
 657    if (env1->psret != 0)
 658        return 1;
 659#else
 660    if (env1->pstate & PS_IE)
 661        return 1;
 662#endif
 663
 664    return 0;
 665}
 666
 667static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
 668{
 669#if !defined(TARGET_SPARC64)
 670    /* level 15 is non-maskable on sparc v8 */
 671    return pil == 15 || pil > env1->psrpil;
 672#else
 673    return pil > env1->psrpil;
 674#endif
 675}
 676
 677#include "exec/cpu-all.h"
 678
 679#ifdef TARGET_SPARC64
 680/* sun4u.c */
 681void cpu_tick_set_count(CPUTimer *timer, uint64_t count);
 682uint64_t cpu_tick_get_count(CPUTimer *timer);
 683void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit);
 684trap_state* cpu_tsptr(CPUSPARCState* env);
 685#endif
 686
 687#define TB_FLAG_FPU_ENABLED (1 << 4)
 688#define TB_FLAG_AM_ENABLED (1 << 5)
 689
 690static inline void cpu_get_tb_cpu_state(CPUSPARCState *env, target_ulong *pc,
 691                                        target_ulong *cs_base, int *flags)
 692{
 693    *pc = env->pc;
 694    *cs_base = env->npc;
 695#ifdef TARGET_SPARC64
 696    // AM . Combined FPU enable bits . PRIV . DMMU enabled . IMMU enabled
 697    *flags = (env->pstate & PS_PRIV)               /* 2 */
 698        | ((env->lsu & (DMMU_E | IMMU_E)) >> 2)    /* 1, 0 */
 699        | ((env->tl & 0xff) << 8)
 700        | (env->dmmu.mmu_primary_context << 16);   /* 16... */
 701    if (env->pstate & PS_AM) {
 702        *flags |= TB_FLAG_AM_ENABLED;
 703    }
 704    if ((env->def->features & CPU_FEATURE_FLOAT) && (env->pstate & PS_PEF)
 705        && (env->fprs & FPRS_FEF)) {
 706        *flags |= TB_FLAG_FPU_ENABLED;
 707    }
 708#else
 709    // FPU enable . Supervisor
 710    *flags = env->psrs;
 711    if ((env->def->features & CPU_FEATURE_FLOAT) && env->psref) {
 712        *flags |= TB_FLAG_FPU_ENABLED;
 713    }
 714#endif
 715}
 716
 717static inline bool tb_fpu_enabled(int tb_flags)
 718{
 719#if defined(CONFIG_USER_ONLY)
 720    return true;
 721#else
 722    return tb_flags & TB_FLAG_FPU_ENABLED;
 723#endif
 724}
 725
 726static inline bool tb_am_enabled(int tb_flags)
 727{
 728#ifndef TARGET_SPARC64
 729    return false;
 730#else
 731    return tb_flags & TB_FLAG_AM_ENABLED;
 732#endif
 733}
 734
 735#include "exec/exec-all.h"
 736
 737#endif
 738