1/* A(ll) access permited 2 R(ead only) access 3 E(nd init protected) access 4 5 A|R|E(offset, register, feature introducing reg) 6 7 NOTE: PSW is handled as a special case in gen_mtcr/mfcr */ 8 9A(0xfe00, PCXI, TRICORE_FEATURE_13) 10A(0xfe08, PC, TRICORE_FEATURE_13) 11A(0xfe14, SYSCON, TRICORE_FEATURE_13) 12R(0xfe18, CPU_ID, TRICORE_FEATURE_13) 13E(0xfe20, BIV, TRICORE_FEATURE_13) 14E(0xfe24, BTV, TRICORE_FEATURE_13) 15E(0xfe28, ISP, TRICORE_FEATURE_13) 16A(0xfe2c, ICR, TRICORE_FEATURE_13) 17A(0xfe38, FCX, TRICORE_FEATURE_13) 18A(0xfe3c, LCX, TRICORE_FEATURE_13) 19E(0x9400, COMPAT, TRICORE_FEATURE_131) 20/* memory protection register */ 21A(0xC000, DPR0_0L, TRICORE_FEATURE_13) 22A(0xC004, DPR0_0U, TRICORE_FEATURE_13) 23A(0xC008, DPR0_1L, TRICORE_FEATURE_13) 24A(0xC00C, DPR0_1U, TRICORE_FEATURE_13) 25A(0xC010, DPR0_2L, TRICORE_FEATURE_13) 26A(0xC014, DPR0_2U, TRICORE_FEATURE_13) 27A(0xC018, DPR0_3L, TRICORE_FEATURE_13) 28A(0xC01C, DPR0_3U, TRICORE_FEATURE_13) 29A(0xC400, DPR1_0L, TRICORE_FEATURE_13) 30A(0xC404, DPR1_0U, TRICORE_FEATURE_13) 31A(0xC408, DPR1_1L, TRICORE_FEATURE_13) 32A(0xC40C, DPR1_1U, TRICORE_FEATURE_13) 33A(0xC410, DPR1_2L, TRICORE_FEATURE_13) 34A(0xC414, DPR1_2U, TRICORE_FEATURE_13) 35A(0xC418, DPR1_3L, TRICORE_FEATURE_13) 36A(0xC41C, DPR1_3U, TRICORE_FEATURE_13) 37A(0xC800, DPR2_0L, TRICORE_FEATURE_13) 38A(0xC804, DPR2_0U, TRICORE_FEATURE_13) 39A(0xC808, DPR2_1L, TRICORE_FEATURE_13) 40A(0xC80C, DPR2_1U, TRICORE_FEATURE_13) 41A(0xC810, DPR2_2L, TRICORE_FEATURE_13) 42A(0xC814, DPR2_2U, TRICORE_FEATURE_13) 43A(0xC818, DPR2_3L, TRICORE_FEATURE_13) 44A(0xC81C, DPR2_3U, TRICORE_FEATURE_13) 45A(0xCC00, DPR3_0L, TRICORE_FEATURE_13) 46A(0xCC04, DPR3_0U, TRICORE_FEATURE_13) 47A(0xCC08, DPR3_1L, TRICORE_FEATURE_13) 48A(0xCC0C, DPR3_1U, TRICORE_FEATURE_13) 49A(0xCC10, DPR3_2L, TRICORE_FEATURE_13) 50A(0xCC14, DPR3_2U, TRICORE_FEATURE_13) 51A(0xCC18, DPR3_3L, TRICORE_FEATURE_13) 52A(0xCC1C, DPR3_3U, TRICORE_FEATURE_13) 53A(0xD000, CPR0_0L, TRICORE_FEATURE_13) 54A(0xD004, CPR0_0U, TRICORE_FEATURE_13) 55A(0xD008, CPR0_1L, TRICORE_FEATURE_13) 56A(0xD00C, CPR0_1U, TRICORE_FEATURE_13) 57A(0xD010, CPR0_2L, TRICORE_FEATURE_13) 58A(0xD014, CPR0_2U, TRICORE_FEATURE_13) 59A(0xD018, CPR0_3L, TRICORE_FEATURE_13) 60A(0xD01C, CPR0_3U, TRICORE_FEATURE_13) 61A(0xD400, CPR1_0L, TRICORE_FEATURE_13) 62A(0xD404, CPR1_0U, TRICORE_FEATURE_13) 63A(0xD408, CPR1_1L, TRICORE_FEATURE_13) 64A(0xD40C, CPR1_1U, TRICORE_FEATURE_13) 65A(0xD410, CPR1_2L, TRICORE_FEATURE_13) 66A(0xD414, CPR1_2U, TRICORE_FEATURE_13) 67A(0xD418, CPR1_3L, TRICORE_FEATURE_13) 68A(0xD41C, CPR1_3U, TRICORE_FEATURE_13) 69A(0xD800, CPR2_0L, TRICORE_FEATURE_13) 70A(0xD804, CPR2_0U, TRICORE_FEATURE_13) 71A(0xD808, CPR2_1L, TRICORE_FEATURE_13) 72A(0xD80C, CPR2_1U, TRICORE_FEATURE_13) 73A(0xD810, CPR2_2L, TRICORE_FEATURE_13) 74A(0xD814, CPR2_2U, TRICORE_FEATURE_13) 75A(0xD818, CPR2_3L, TRICORE_FEATURE_13) 76A(0xD81C, CPR2_3U, TRICORE_FEATURE_13) 77A(0xDC00, CPR3_0L, TRICORE_FEATURE_13) 78A(0xDC04, CPR3_0U, TRICORE_FEATURE_13) 79A(0xDC08, CPR3_1L, TRICORE_FEATURE_13) 80A(0xDC0C, CPR3_1U, TRICORE_FEATURE_13) 81A(0xDC10, CPR3_2L, TRICORE_FEATURE_13) 82A(0xDC14, CPR3_2U, TRICORE_FEATURE_13) 83A(0xDC18, CPR3_3L, TRICORE_FEATURE_13) 84A(0xDC1C, CPR3_3U, TRICORE_FEATURE_13) 85A(0xE000, DPM0, TRICORE_FEATURE_13) 86A(0xE080, DPM1, TRICORE_FEATURE_13) 87A(0xE100, DPM2, TRICORE_FEATURE_13) 88A(0xE180, DPM3, TRICORE_FEATURE_13) 89A(0xE200, CPM0, TRICORE_FEATURE_13) 90A(0xE280, CPM1, TRICORE_FEATURE_13) 91A(0xE300, CPM2, TRICORE_FEATURE_13) 92A(0xE380, CPM3, TRICORE_FEATURE_13) 93/* memory management registers */ 94A(0x8000, MMU_CON, TRICORE_FEATURE_13) 95A(0x8004, MMU_ASI, TRICORE_FEATURE_13) 96A(0x800C, MMU_TVA, TRICORE_FEATURE_13) 97A(0x8010, MMU_TPA, TRICORE_FEATURE_13) 98A(0x8014, MMU_TPX, TRICORE_FEATURE_13) 99A(0x8018, MMU_TFA, TRICORE_FEATURE_13) 100E(0x9004, BMACON, TRICORE_FEATURE_131) 101E(0x900C, SMACON, TRICORE_FEATURE_131) 102A(0x9020, DIEAR, TRICORE_FEATURE_131) 103A(0x9024, DIETR, TRICORE_FEATURE_131) 104A(0x9028, CCDIER, TRICORE_FEATURE_131) 105E(0x9044, MIECON, TRICORE_FEATURE_131) 106A(0x9210, PIEAR, TRICORE_FEATURE_131) 107A(0x9214, PIETR, TRICORE_FEATURE_131) 108A(0x9218, CCPIER, TRICORE_FEATURE_131) 109/* debug registers */ 110A(0xFD00, DBGSR, TRICORE_FEATURE_13) 111A(0xFD08, EXEVT, TRICORE_FEATURE_13) 112A(0xFD0C, CREVT, TRICORE_FEATURE_13) 113A(0xFD10, SWEVT, TRICORE_FEATURE_13) 114A(0xFD20, TR0EVT, TRICORE_FEATURE_13) 115A(0xFD24, TR1EVT, TRICORE_FEATURE_13) 116A(0xFD40, DMS, TRICORE_FEATURE_13) 117A(0xFD44, DCX, TRICORE_FEATURE_13) 118A(0xFD48, DBGTCR, TRICORE_FEATURE_131) 119A(0xFC00, CCTRL, TRICORE_FEATURE_131) 120A(0xFC04, CCNT, TRICORE_FEATURE_131) 121A(0xFC08, ICNT, TRICORE_FEATURE_131) 122A(0xFC0C, M1CNT, TRICORE_FEATURE_131) 123A(0xFC10, M2CNT, TRICORE_FEATURE_131) 124A(0xFC14, M3CNT, TRICORE_FEATURE_131) 125