LXR qemu/target-tricore/helper.c

   1/*
   2 *  Copyright (c) 2012-2014 Bastian Koppelmann C-Lab/University Paderborn
   3 *
   4 * This library is free software; you can redistribute it and/or
   5 * modify it under the terms of the GNU Lesser General Public
   6 * License as published by the Free Software Foundation; either
   7 * version 2 of the License, or (at your option) any later version.
   8 *
   9 * This library is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  12 * Lesser General Public License for more details.
  13 *
  14 * You should have received a copy of the GNU Lesser General Public
  15 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  16 */
  17
  18#include "qemu/osdep.h"
  19
  20#include "cpu.h"
  21
  22enum {
  23    TLBRET_DIRTY = -4,
  24    TLBRET_INVALID = -3,
  25    TLBRET_NOMATCH = -2,
  26    TLBRET_BADADDR = -1,
  27    TLBRET_MATCH = 0
  28};
  29
  30#if defined(CONFIG_SOFTMMU)
  31static int get_physical_address(CPUTriCoreState *env, hwaddr *physical,
  32                                int *prot, target_ulong address,
  33                                int rw, int access_type)
  34{
  35    int ret = TLBRET_MATCH;
  36
  37    *physical = address & 0xFFFFFFFF;
  38    *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
  39
  40    return ret;
  41}
  42#endif
  43
  44/* TODO: Add exeption support*/
  45static void raise_mmu_exception(CPUTriCoreState *env, target_ulong address,
  46                                int rw, int tlb_error)
  47{
  48}
  49
  50int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address,
  51                                 int rw, int mmu_idx)
  52{
  53    TriCoreCPU *cpu = TRICORE_CPU(cs);
  54    CPUTriCoreState *env = &cpu->env;
  55    hwaddr physical;
  56    int prot;
  57    int access_type;
  58    int ret = 0;
  59
  60    rw &= 1;
  61    access_type = ACCESS_INT;
  62    ret = get_physical_address(env, &physical, &prot,
  63                               address, rw, access_type);
  64    qemu_log_mask(CPU_LOG_MMU, "%s address=" TARGET_FMT_lx " ret %d physical " TARGET_FMT_plx
  65                  " prot %d\n", __func__, address, ret, physical, prot);
  66
  67    if (ret == TLBRET_MATCH) {
  68        tlb_set_page(cs, address & TARGET_PAGE_MASK,
  69                     physical & TARGET_PAGE_MASK, prot | PAGE_EXEC,
  70                     mmu_idx, TARGET_PAGE_SIZE);
  71        ret = 0;
  72    } else if (ret < 0) {
  73        raise_mmu_exception(env, address, rw, ret);
  74        ret = 1;
  75    }
  76
  77    return ret;
  78}
  79
  80TriCoreCPU *cpu_tricore_init(const char *cpu_model)
  81{
  82    return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model));
  83}
  84
  85static void tricore_cpu_list_entry(gpointer data, gpointer user_data)
  86{
  87    ObjectClass *oc = data;
  88    CPUListState *s = user_data;
  89    const char *typename;
  90    char *name;
  91
  92    typename = object_class_get_name(oc);
  93    name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_TRICORE_CPU));
  94    (*s->cpu_fprintf)(s->file, "  %s\n",
  95                      name);
  96    g_free(name);
  97}
  98
  99void tricore_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 100{
 101    CPUListState s = {
 102        .file = f,
 103        .cpu_fprintf = cpu_fprintf,
 104    };
 105    GSList *list;
 106
 107    list = object_class_get_list(TYPE_TRICORE_CPU, false);
 108    (*cpu_fprintf)(f, "Available CPUs:\n");
 109    g_slist_foreach(list, tricore_cpu_list_entry, &s);
 110    g_slist_free(list);
 111}
 112
 113void fpu_set_state(CPUTriCoreState *env)
 114{
 115    set_float_rounding_mode(env->PSW & MASK_PSW_FPU_RM, &env->fp_status);
 116    set_flush_inputs_to_zero(1, &env->fp_status);
 117    set_flush_to_zero(1, &env->fp_status);
 118    set_default_nan_mode(1, &env->fp_status);
 119}
 120
 121uint32_t psw_read(CPUTriCoreState *env)
 122{
 123    /* clear all USB bits */
 124    env->PSW &= 0x6ffffff;
 125    /* now set them from the cache */
 126    env->PSW |= ((env->PSW_USB_C != 0) << 31);
 127    env->PSW |= ((env->PSW_USB_V   & (1 << 31))  >> 1);
 128    env->PSW |= ((env->PSW_USB_SV  & (1 << 31))  >> 2);
 129    env->PSW |= ((env->PSW_USB_AV  & (1 << 31))  >> 3);
 130    env->PSW |= ((env->PSW_USB_SAV & (1 << 31))  >> 4);
 131
 132    return env->PSW;
 133}
 134
 135void psw_write(CPUTriCoreState *env, uint32_t val)
 136{
 137    env->PSW_USB_C = (val & MASK_USB_C);
 138    env->PSW_USB_V = (val & MASK_USB_V) << 1;
 139    env->PSW_USB_SV = (val & MASK_USB_SV) << 2;
 140    env->PSW_USB_AV = (val & MASK_USB_AV) << 3;
 141    env->PSW_USB_SAV = (val & MASK_USB_SAV) << 4;
 142    env->PSW = val;
 143
 144    fpu_set_state(env);
 145}
 146