LXR qemu/target-unicore32/softmmu.c

   1/*
   2 * Softmmu related functions
   3 *
   4 * Copyright (C) 2010-2012 Guan Xuetao
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation, or any later version.
   9 * See the COPYING file in the top-level directory.
  10 */
  11#ifdef CONFIG_USER_ONLY
  12#error This file only exist under softmmu circumstance
  13#endif
  14
  15#include "qemu/osdep.h"
  16#include <cpu.h>
  17
  18#undef DEBUG_UC32
  19
  20#ifdef DEBUG_UC32
  21#define DPRINTF(fmt, ...) printf("%s: " fmt , __func__, ## __VA_ARGS__)
  22#else
  23#define DPRINTF(fmt, ...) do {} while (0)
  24#endif
  25
  26#define SUPERPAGE_SIZE             (1 << 22)
  27#define UC32_PAGETABLE_READ        (1 << 8)
  28#define UC32_PAGETABLE_WRITE       (1 << 7)
  29#define UC32_PAGETABLE_EXEC        (1 << 6)
  30#define UC32_PAGETABLE_EXIST       (1 << 2)
  31#define PAGETABLE_TYPE(x)          ((x) & 3)
  32
  33
  34/* Map CPU modes onto saved register banks.  */
  35static inline int bank_number(CPUUniCore32State *env, int mode)
  36{
  37    UniCore32CPU *cpu = uc32_env_get_cpu(env);
  38
  39    switch (mode) {
  40    case ASR_MODE_USER:
  41    case ASR_MODE_SUSR:
  42        return 0;
  43    case ASR_MODE_PRIV:
  44        return 1;
  45    case ASR_MODE_TRAP:
  46        return 2;
  47    case ASR_MODE_EXTN:
  48        return 3;
  49    case ASR_MODE_INTR:
  50        return 4;
  51    }
  52    cpu_abort(CPU(cpu), "Bad mode %x\n", mode);
  53    return -1;
  54}
  55
  56void switch_mode(CPUUniCore32State *env, int mode)
  57{
  58    int old_mode;
  59    int i;
  60
  61    old_mode = env->uncached_asr & ASR_M;
  62    if (mode == old_mode) {
  63        return;
  64    }
  65
  66    i = bank_number(env, old_mode);
  67    env->banked_r29[i] = env->regs[29];
  68    env->banked_r30[i] = env->regs[30];
  69    env->banked_bsr[i] = env->bsr;
  70
  71    i = bank_number(env, mode);
  72    env->regs[29] = env->banked_r29[i];
  73    env->regs[30] = env->banked_r30[i];
  74    env->bsr = env->banked_bsr[i];
  75}
  76
  77/* Handle a CPU exception.  */
  78void uc32_cpu_do_interrupt(CPUState *cs)
  79{
  80    UniCore32CPU *cpu = UNICORE32_CPU(cs);
  81    CPUUniCore32State *env = &cpu->env;
  82    uint32_t addr;
  83    int new_mode;
  84
  85    switch (cs->exception_index) {
  86    case UC32_EXCP_PRIV:
  87        new_mode = ASR_MODE_PRIV;
  88        addr = 0x08;
  89        break;
  90    case UC32_EXCP_ITRAP:
  91        DPRINTF("itrap happened at %x\n", env->regs[31]);
  92        new_mode = ASR_MODE_TRAP;
  93        addr = 0x0c;
  94        break;
  95    case UC32_EXCP_DTRAP:
  96        DPRINTF("dtrap happened at %x\n", env->regs[31]);
  97        new_mode = ASR_MODE_TRAP;
  98        addr = 0x10;
  99        break;
 100    case UC32_EXCP_INTR:
 101        new_mode = ASR_MODE_INTR;
 102        addr = 0x18;
 103        break;
 104    default:
 105        cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
 106        return;
 107    }
 108    /* High vectors.  */
 109    if (env->cp0.c1_sys & (1 << 13)) {
 110        addr += 0xffff0000;
 111    }
 112
 113    switch_mode(env, new_mode);
 114    env->bsr = cpu_asr_read(env);
 115    env->uncached_asr = (env->uncached_asr & ~ASR_M) | new_mode;
 116    env->uncached_asr |= ASR_I;
 117    /* The PC already points to the proper instruction.  */
 118    env->regs[30] = env->regs[31];
 119    env->regs[31] = addr;
 120    cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
 121}
 122
 123static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
 124        int access_type, int is_user, uint32_t *phys_ptr, int *prot,
 125        target_ulong *page_size)
 126{
 127    UniCore32CPU *cpu = uc32_env_get_cpu(env);
 128    CPUState *cs = CPU(cpu);
 129    int code;
 130    uint32_t table;
 131    uint32_t desc;
 132    uint32_t phys_addr;
 133
 134    /* Pagetable walk.  */
 135    /* Lookup l1 descriptor.  */
 136    table = env->cp0.c2_base & 0xfffff000;
 137    table |= (address >> 20) & 0xffc;
 138    desc = ldl_phys(cs->as, table);
 139    code = 0;
 140    switch (PAGETABLE_TYPE(desc)) {
 141    case 3:
 142        /* Superpage  */
 143        if (!(desc & UC32_PAGETABLE_EXIST)) {
 144            code = 0x0b; /* superpage miss */
 145            goto do_fault;
 146        }
 147        phys_addr = (desc & 0xffc00000) | (address & 0x003fffff);
 148        *page_size = SUPERPAGE_SIZE;
 149        break;
 150    case 0:
 151        /* Lookup l2 entry.  */
 152        if (is_user) {
 153            DPRINTF("PGD address %x, desc %x\n", table, desc);
 154        }
 155        if (!(desc & UC32_PAGETABLE_EXIST)) {
 156            code = 0x05; /* second pagetable miss */
 157            goto do_fault;
 158        }
 159        table = (desc & 0xfffff000) | ((address >> 10) & 0xffc);
 160        desc = ldl_phys(cs->as, table);
 161        /* 4k page.  */
 162        if (is_user) {
 163            DPRINTF("PTE address %x, desc %x\n", table, desc);
 164        }
 165        if (!(desc & UC32_PAGETABLE_EXIST)) {
 166            code = 0x08; /* page miss */
 167            goto do_fault;
 168        }
 169        switch (PAGETABLE_TYPE(desc)) {
 170        case 0:
 171            phys_addr = (desc & 0xfffff000) | (address & 0xfff);
 172            *page_size = TARGET_PAGE_SIZE;
 173            break;
 174        default:
 175            cpu_abort(CPU(cpu), "wrong page type!");
 176        }
 177        break;
 178    default:
 179        cpu_abort(CPU(cpu), "wrong page type!");
 180    }
 181
 182    *phys_ptr = phys_addr;
 183    *prot = 0;
 184    /* Check access permissions.  */
 185    if (desc & UC32_PAGETABLE_READ) {
 186        *prot |= PAGE_READ;
 187    } else {
 188        if (is_user && (access_type == 0)) {
 189            code = 0x11; /* access unreadable area */
 190            goto do_fault;
 191        }
 192    }
 193
 194    if (desc & UC32_PAGETABLE_WRITE) {
 195        *prot |= PAGE_WRITE;
 196    } else {
 197        if (is_user && (access_type == 1)) {
 198            code = 0x12; /* access unwritable area */
 199            goto do_fault;
 200        }
 201    }
 202
 203    if (desc & UC32_PAGETABLE_EXEC) {
 204        *prot |= PAGE_EXEC;
 205    } else {
 206        if (is_user && (access_type == 2)) {
 207            code = 0x13; /* access unexecutable area */
 208            goto do_fault;
 209        }
 210    }
 211
 212do_fault:
 213    return code;
 214}
 215
 216int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
 217                              int access_type, int mmu_idx)
 218{
 219    UniCore32CPU *cpu = UNICORE32_CPU(cs);
 220    CPUUniCore32State *env = &cpu->env;
 221    uint32_t phys_addr;
 222    target_ulong page_size;
 223    int prot;
 224    int ret, is_user;
 225
 226    ret = 1;
 227    is_user = mmu_idx == MMU_USER_IDX;
 228
 229    if ((env->cp0.c1_sys & 1) == 0) {
 230        /* MMU disabled.  */
 231        phys_addr = address;
 232        prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 233        page_size = TARGET_PAGE_SIZE;
 234        ret = 0;
 235    } else {
 236        if ((address & (1 << 31)) || (is_user)) {
 237            ret = get_phys_addr_ucv2(env, address, access_type, is_user,
 238                                    &phys_addr, &prot, &page_size);
 239            if (is_user) {
 240                DPRINTF("user space access: ret %x, address %" VADDR_PRIx ", "
 241                        "access_type %x, phys_addr %x, prot %x\n",
 242                        ret, address, access_type, phys_addr, prot);
 243            }
 244        } else {
 245            /*IO memory */
 246            phys_addr = address | (1 << 31);
 247            prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
 248            page_size = TARGET_PAGE_SIZE;
 249            ret = 0;
 250        }
 251    }
 252
 253    if (ret == 0) {
 254        /* Map a single page.  */
 255        phys_addr &= TARGET_PAGE_MASK;
 256        address &= TARGET_PAGE_MASK;
 257        tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
 258        return 0;
 259    }
 260
 261    env->cp0.c3_faultstatus = ret;
 262    env->cp0.c4_faultaddr = address;
 263    if (access_type == 2) {
 264        cs->exception_index = UC32_EXCP_ITRAP;
 265    } else {
 266        cs->exception_index = UC32_EXCP_DTRAP;
 267    }
 268    return ret;
 269}
 270
 271hwaddr uc32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
 272{
 273    UniCore32CPU *cpu = UNICORE32_CPU(cs);
 274
 275    cpu_abort(CPU(cpu), "%s not supported yet\n", __func__);
 276    return addr;
 277}
 278