qemu/tests/tcg/xtensa/test_interrupt.S
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   1#include "macros.inc"
   2
   3test_suite interrupt
   4
   5.macro clear_interrupts
   6    movi    a2, 0
   7    wsr     a2, intenable
   8    wsr     a2, ccompare0
   9    wsr     a2, ccompare1
  10    wsr     a2, ccompare2
  11    esync
  12    rsr     a2, interrupt
  13    wsr     a2, intclear
  14
  15    esync
  16    rsr     a2, interrupt
  17    assert  eqi, a2, 0
  18.endm
  19
  20.macro check_l1
  21    rsr     a2, ps
  22    movi    a3, 0x1f        /* EXCM | INTMASK */
  23    and     a2, a2, a3
  24    assert  eqi, a2, 0x10   /* only EXCM is set for level-1 interrupt */
  25    rsr     a2, exccause
  26    assert  eqi, a2, 4
  27.endm
  28
  29test rsil
  30    clear_interrupts
  31
  32    rsr     a2, ps
  33    rsil    a3, 7
  34    rsr     a4, ps
  35    assert  eq, a2, a3
  36    movi    a2, 0xf
  37    and     a2, a4, a2
  38    assert  eqi, a2, 7
  39    xor     a3, a3, a4
  40    movi    a2, 0xfffffff0
  41    and     a2, a3, a2
  42    assert  eqi, a2, 0
  43test_end
  44
  45test soft_disabled
  46    set_vector kernel, 1f
  47    clear_interrupts
  48
  49    movi    a2, 0x80
  50    wsr     a2, intset
  51    esync
  52    rsr     a3, interrupt
  53    assert  eq, a2, a3
  54    wsr     a2, intclear
  55    esync
  56    rsr     a3, interrupt
  57    assert  eqi, a3, 0
  58    j       2f
  591:
  60    test_fail
  612:
  62test_end
  63
  64test soft_intenable
  65    set_vector kernel, 1f
  66    clear_interrupts
  67
  68    movi    a2, 0x80
  69    wsr     a2, intset
  70    esync
  71    rsr     a3, interrupt
  72    assert  eq, a2, a3
  73    rsil    a3, 0
  74    wsr     a2, intenable
  75    esync
  76    test_fail
  771:
  78    check_l1
  79test_end
  80
  81test soft_rsil
  82    set_vector kernel, 1f
  83    clear_interrupts
  84
  85    movi    a2, 0x80
  86    wsr     a2, intset
  87    esync
  88    rsr     a3, interrupt
  89    assert  eq, a2, a3
  90    wsr     a2, intenable
  91    rsil    a3, 0
  92    esync
  93    test_fail
  941:
  95    check_l1
  96test_end
  97
  98test soft_waiti
  99    set_vector kernel, 1f
 100    clear_interrupts
 101
 102    movi    a2, 0x80
 103    wsr     a2, intset
 104    esync
 105    rsr     a3, interrupt
 106    assert  eq, a2, a3
 107    wsr     a2, intenable
 108    waiti   0
 109    test_fail
 1101:
 111    check_l1
 112test_end
 113
 114test soft_user
 115    set_vector kernel, 1f
 116    set_vector user, 2f
 117    clear_interrupts
 118
 119    movi    a2, 0x80
 120    wsr     a2, intset
 121    esync
 122    rsr     a3, interrupt
 123    assert  eq, a2, a3
 124    wsr     a2, intenable
 125
 126    rsr     a2, ps
 127    movi    a3, 0x20
 128    or      a2, a2, a3
 129    wsr     a2, ps
 130    waiti   0
 1311:
 132    test_fail
 1332:
 134    check_l1
 135test_end
 136
 137test soft_priority
 138    set_vector kernel, 1f
 139    set_vector level3, 2f
 140    clear_interrupts
 141
 142    movi    a2, 0x880
 143    wsr     a2, intenable
 144    rsil    a3, 0
 145    esync
 146    wsr     a2, intset
 147    esync
 1481:
 149    test_fail
 1502:
 151    rsr     a2, ps
 152    movi    a3, 0x1f        /* EXCM | INTMASK */
 153    and     a2, a2, a3
 154    movi    a3, 0x13
 155    assert  eq, a2, a3      /* EXCM and INTMASK are set
 156                               for high-priority interrupt */
 157test_end
 158
 159test eps_epc_rfi
 160    set_vector level3, 3f
 161    clear_interrupts
 162    reset_ps
 163
 164    movi    a2, 0x880
 165    wsr     a2, intenable
 166    rsil    a3, 0
 167    rsr     a3, ps
 168    esync
 169    wsr     a2, intset
 1701:
 171    esync
 1722:
 173    test_fail
 1743:
 175    rsr     a2, eps3
 176    assert  eq, a2, a3
 177    rsr     a2, epc3
 178    movi    a3, 1b
 179    assert  ge, a2, a3
 180    movi    a3, 2b
 181    assert  ge, a3, a2
 182    movi    a2, 4f
 183    wsr     a2, epc3
 184    movi    a2, 0x40003
 185    wsr     a2, eps3
 186    rfi     3
 187    test_fail
 1884:
 189    rsr     a2, ps
 190    movi    a3, 0x40003
 191    assert  eq, a2, a3
 192test_end
 193
 194test_suite_end
 195