/* ppc-dis.c -- Disassemble PowerPC instructions
   Copyright 1994, 1995, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007
   Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
2, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not,
see <http://www.gnu.org/licenses/>.  */
#include "qemu/osdep.h"
#include "disas/bfd.h"
#define BFD_DEFAULT_TARGET_SIZE 64

/* ppc.h -- Header file for PowerPC opcode table
   Copyright 1994, 1995, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006,
   2007 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

This file is part of GDB, GAS, and the GNU binutils.

GDB, GAS, and the GNU binutils are free software; you can redistribute
them and/or modify them under the terms of the GNU General Public
License as published by the Free Software Foundation; either version
1, or (at your option) any later version.

GDB, GAS, and the GNU binutils are distributed in the hope that they
will be useful, but WITHOUT ANY WARRANTY; without even the implied
warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
the GNU General Public License for more details.

You should have received a copy of the GNU General Public License
along with this file; see the file COPYING.  If not,
see <http://www.gnu.org/licenses/>.  */

/* The opcode table is an array of struct powerpc_opcode.  */

struct powerpc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned long opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned long mask;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors support the instructions.  The defined values
     are listed below.  */
  unsigned long flags;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[8];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct powerpc_opcode powerpc_opcodes[];
extern const int powerpc_num_opcodes;

/* Values defined for the flags field of a struct powerpc_opcode.  */

/* Opcode is defined for the PowerPC architecture.  */
#define PPC_OPCODE_PPC                   1

/* Opcode is defined for the POWER (RS/6000) architecture.  */
#define PPC_OPCODE_POWER                 2

/* Opcode is defined for the POWER2 (Rios 2) architecture.  */
#define PPC_OPCODE_POWER2                4

/* Opcode is only defined on 32 bit architectures.  */
#define PPC_OPCODE_32                    8

/* Opcode is only defined on 64 bit architectures.  */
#define PPC_OPCODE_64                 0x10

/* Opcode is supported by the Motorola PowerPC 601 processor.  The 601
   is assumed to support all PowerPC (PPC_OPCODE_PPC) instructions,
   but it also supports many additional POWER instructions.  */
#define PPC_OPCODE_601                0x20

/* Opcode is supported in both the Power and PowerPC architectures
   (ie, compiler's -mcpu=common or assembler's -mcom).  */
#define PPC_OPCODE_COMMON             0x40

/* Opcode is supported for any Power or PowerPC platform (this is
   for the assembler's -many option, and it eliminates duplicates).  */
#define PPC_OPCODE_ANY                0x80

/* Opcode is supported as part of the 64-bit bridge.  */
#define PPC_OPCODE_64_BRIDGE         0x100

/* Opcode is supported by Altivec Vector Unit */
#define PPC_OPCODE_ALTIVEC           0x200

/* Opcode is supported by PowerPC 403 processor.  */
#define PPC_OPCODE_403               0x400

/* Opcode is supported by PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE             0x800

/* Opcode is only supported by 64-bit PowerPC BookE processor.  */
#define PPC_OPCODE_BOOKE64          0x1000

/* Opcode is supported by PowerPC 440 processor.  */
#define PPC_OPCODE_440              0x2000

/* Opcode is only supported by Power4 architecture.  */
#define PPC_OPCODE_POWER4           0x4000

/* Opcode isn't supported by Power4 architecture.  */
#define PPC_OPCODE_NOPOWER4         0x8000

/* Opcode is only supported by POWERPC Classic architecture.  */
#define PPC_OPCODE_CLASSIC         0x10000

/* Opcode is only supported by e500x2 Core.  */
#define PPC_OPCODE_SPE             0x20000

/* Opcode is supported by e500x2 Integer select APU.  */
#define PPC_OPCODE_ISEL            0x40000

/* Opcode is an e500 SPE floating point instruction.  */
#define PPC_OPCODE_EFS             0x80000

/* Opcode is supported by branch locking APU.  */
#define PPC_OPCODE_BRLOCK         0x100000

/* Opcode is supported by performance monitor APU.  */
#define PPC_OPCODE_PMR            0x200000

/* Opcode is supported by cache locking APU.  */
#define PPC_OPCODE_CACHELCK       0x400000

/* Opcode is supported by machine check APU.  */
#define PPC_OPCODE_RFMCI          0x800000

/* Opcode is only supported by Power5 architecture.  */
#define PPC_OPCODE_POWER5        0x1000000

/* Opcode is supported by PowerPC e300 family.  */
#define PPC_OPCODE_E300          0x2000000

/* Opcode is only supported by Power6 architecture.  */
#define PPC_OPCODE_POWER6        0x4000000

/* Opcode is only supported by PowerPC Cell family.  */
#define PPC_OPCODE_CELL          0x8000000

/* A macro to extract the major opcode from an instruction.  */
#define PPC_OP(i) (((i) >> 26) & 0x3f)

/* The operands table is an array of struct powerpc_operand.  */

struct powerpc_operand
{
  /* A bitmask of bits in the operand.  */
  unsigned int bitm;

  /* How far the operand is left shifted in the instruction.
     -1 to indicate that BITM and SHIFT cannot be used to determine
     where the operand goes in the insn.  */
  int shift;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
         i |= (op & o->bitm) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the operand value).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.  It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).  If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned long (*insert)
    (unsigned long instruction, long op, int dialect, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
         op = (i >> o->shift) & o->bitm;
         if ((o->flags & PPC_OPERAND_SIGNED) != 0)
           sign_extend (op);
     (i is the instruction, o is a pointer to this structure, and op
     is the result).

     If this field is not NULL, then simply call it with the
     instruction value.  It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     non-zero if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  long (*extract) (unsigned long instruction, int dialect, int *invalid);

  /* One bit syntax flags.  */
  unsigned long flags;
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the powerpc_opcodes table.  */

extern const struct powerpc_operand powerpc_operands[];
extern const unsigned int num_powerpc_operands;

/* Values defined for the flags field of a struct powerpc_operand.  */

/* This operand takes signed values.  */
#define PPC_OPERAND_SIGNED (0x1)

/* This operand takes signed values, but also accepts a full positive
   range of values when running in 32 bit mode.  That is, if bits is
   16, it takes any value from -0x8000 to 0xffff.  In 64 bit mode,
   this flag is ignored.  */
#define PPC_OPERAND_SIGNOPT (0x2)

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics such as mr, for which two
   operands fields are identical.  The assembler should call the
   insert function with any op value.  The disassembler should call
   the extract function, ignore the return value, and check the value
   placed in the valid argument.  */
#define PPC_OPERAND_FAKE (0x4)

/* The next operand should be wrapped in parentheses rather than
   separated from this one by a comma.  This is used for the load and
   store instructions which want their operands to look like
       reg,displacement(reg)
   */
#define PPC_OPERAND_PARENS (0x8)

/* This operand may use the symbolic names for the CR fields, which
   are
       lt  0    gt  1   eq  2   so  3   un  3
       cr0 0    cr1 1   cr2 2   cr3 3
       cr4 4    cr5 5   cr6 6   cr7 7
   These may be combined arithmetically, as in cr2*4+gt.  These are
   only supported on the PowerPC, not the POWER.  */
#define PPC_OPERAND_CR (0x10)

/* This operand names a register.  The disassembler uses this to print
   register names with a leading 'r'.  */
#define PPC_OPERAND_GPR (0x20)

/* Like PPC_OPERAND_GPR, but don't print a leading 'r' for r0.  */
#define PPC_OPERAND_GPR_0 (0x40)

/* This operand names a floating point register.  The disassembler
   prints these with a leading 'f'.  */
#define PPC_OPERAND_FPR (0x80)

/* This operand is a relative branch displacement.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_RELATIVE (0x100)

/* This operand is an absolute branch address.  The disassembler
   prints these symbolically if possible.  */
#define PPC_OPERAND_ABSOLUTE (0x200)

/* This operand is optional, and is zero if omitted.  This is used for
   example, in the optional BF field in the comparison instructions.  The
   assembler must count the number of operands remaining on the line,
   and the number of operands remaining for the opcode, and decide
   whether this operand is present or not.  The disassembler should
   print this operand out only if it is not zero.  */
#define PPC_OPERAND_OPTIONAL (0x400)

/* This flag is only used with PPC_OPERAND_OPTIONAL.  If this operand
   is omitted, then for the next operand use this operand value plus
   1, ignoring the next operand field for the opcode.  This wretched
   hack is needed because the Power rotate instructions can take
   either 4 or 5 operands.  The disassembler should print this operand
   out regardless of the PPC_OPERAND_OPTIONAL field.  */
#define PPC_OPERAND_NEXT (0x800)

/* This operand should be regarded as a negative number for the
   purposes of overflow checking (i.e., the normal most negative
   number is disallowed and one more than the normal most positive
   number is allowed).  This flag will only be set for a signed
   operand.  */
#define PPC_OPERAND_NEGATIVE (0x1000)

/* This operand names a vector unit register.  The disassembler
   prints these with a leading 'v'.  */
#define PPC_OPERAND_VR (0x2000)

/* This operand is for the DS field in a DS form instruction.  */
#define PPC_OPERAND_DS (0x4000)

/* This operand is for the DQ field in a DQ form instruction.  */
#define PPC_OPERAND_DQ (0x8000)

/* Valid range of operand is 0..n rather than 0..n-1.  */
#define PPC_OPERAND_PLUS1 (0x10000)

/* The POWER and PowerPC assemblers use a few macros.  We keep them
   with the operands table for simplicity.  The macro table is an
   array of struct powerpc_macro.  */

struct powerpc_macro
{
  /* The macro name.  */
  const char *name;

  /* The number of operands the macro takes.  */
  unsigned int operands;

  /* One bit flags for the opcode.  These are used to indicate which
     specific processors support the instructions.  The values are the
     same as those for the struct powerpc_opcode flags field.  */
  unsigned long flags;

  /* A format string to turn the macro into a normal instruction.
     Each %N in the string is replaced with operand number N (zero
     based).  */
  const char *format;
};

extern const struct powerpc_macro powerpc_macros[];
extern const int powerpc_num_macros;

/* ppc-opc.c -- PowerPC opcode list
   Copyright 1994, 1995, 1996, 1997, 1998, 2000, 2001, 2002, 2003, 2004,
   2005, 2006, 2007 Free Software Foundation, Inc.
   Written by Ian Lance Taylor, Cygnus Support

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version
   2, or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this file; see the file COPYING.
   If not, see <http://www.gnu.org/licenses/>.  */

/* This file holds the PowerPC opcode table.  The opcode table
   includes almost all of the extended instruction mnemonics.  This
   permits the disassembler to use them, and simplifies the assembler
   logic, at the cost of increasing the table size.  The table is
   strictly constant data, so the compiler should be able to put it in
   the .text section.

   This file also holds the operand table.  All knowledge about
   inserting operands into instructions and vice-versa is kept in this
   file.  */

/* Local insertion and extraction functions.  */

static unsigned long insert_bat (unsigned long, long, int, const char **);
static long extract_bat (unsigned long, int, int *);
static unsigned long insert_bba (unsigned long, long, int, const char **);
static long extract_bba (unsigned long, int, int *);
static unsigned long insert_bdm (unsigned long, long, int, const char **);
static long extract_bdm (unsigned long, int, int *);
static unsigned long insert_bdp (unsigned long, long, int, const char **);
static long extract_bdp (unsigned long, int, int *);
static unsigned long insert_bo (unsigned long, long, int, const char **);
static long extract_bo (unsigned long, int, int *);
static unsigned long insert_boe (unsigned long, long, int, const char **);
static long extract_boe (unsigned long, int, int *);
static unsigned long insert_fxm (unsigned long, long, int, const char **);
static long extract_fxm (unsigned long, int, int *);
static unsigned long insert_mbe (unsigned long, long, int, const char **);
static long extract_mbe (unsigned long, int, int *);
static unsigned long insert_mb6 (unsigned long, long, int, const char **);
static long extract_mb6 (unsigned long, int, int *);
static long extract_nb (unsigned long, int, int *);
static unsigned long insert_nsi (unsigned long, long, int, const char **);
static long extract_nsi (unsigned long, int, int *);
static unsigned long insert_ral (unsigned long, long, int, const char **);
static unsigned long insert_ram (unsigned long, long, int, const char **);
static unsigned long insert_raq (unsigned long, long, int, const char **);
static unsigned long insert_ras (unsigned long, long, int, const char **);
static unsigned long insert_rbs (unsigned long, long, int, const char **);
static long extract_rbs (unsigned long, int, int *);
static unsigned long insert_sh6 (unsigned long, long, int, const char **);
static long extract_sh6 (unsigned long, int, int *);
static unsigned long insert_spr (unsigned long, long, int, const char **);
static long extract_spr (unsigned long, int, int *);
static unsigned long insert_sprg (unsigned long, long, int, const char **);
static long extract_sprg (unsigned long, int, int *);
static unsigned long insert_tbr (unsigned long, long, int, const char **);
static long extract_tbr (unsigned long, int, int *);

/* The operands table.

   The fields are bitm, shift, insert, extract, flags.

   We used to put parens around the various additions, like the one
   for BA just below.  However, that caused trouble with feeble
   compilers with a limit on depth of a parenthesized expression, like
   (reportedly) the compiler in Microsoft Developer Studio 5.  So we
   omit the parens, since the macros are never used in a context where
   the addition will be ambiguous.  */

const struct powerpc_operand powerpc_operands[] =
{
  /* The zero index is used to indicate the end of the list of
     operands.  */
#define UNUSED 0
  { 0, 0, NULL, NULL, 0 },

  /* The BA field in an XL form instruction.  */
#define BA UNUSED + 1
  /* The BI field in a B form or XL form instruction.  */
#define BI BA
#define BI_MASK (0x1f << 16)
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_CR },

  /* The BA field in an XL form instruction when it must be the same
     as the BT field in the same instruction.  */
#define BAT BA + 1
  { 0x1f, 16, insert_bat, extract_bat, PPC_OPERAND_FAKE },

  /* The BB field in an XL form instruction.  */
#define BB BAT + 1
#define BB_MASK (0x1f << 11)
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_CR },

  /* The BB field in an XL form instruction when it must be the same
     as the BA field in the same instruction.  */
#define BBA BB + 1
  { 0x1f, 11, insert_bba, extract_bba, PPC_OPERAND_FAKE },

  /* The BD field in a B form instruction.  The lower two bits are
     forced to zero.  */
#define BD BBA + 1
  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when absolute addressing is
     used.  */
#define BDA BD + 1
  { 0xfffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used.
     This sets the y bit of the BO field appropriately.  */
#define BDM BDA + 1
  { 0xfffc, 0, insert_bdm, extract_bdm,
      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the - modifier is used
     and absolute address is used.  */
#define BDMA BDM + 1
  { 0xfffc, 0, insert_bdm, extract_bdm,
      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used.
     This sets the y bit of the BO field appropriately.  */
#define BDP BDMA + 1
  { 0xfffc, 0, insert_bdp, extract_bdp,
      PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The BD field in a B form instruction when the + modifier is used
     and absolute addressing is used.  */
#define BDPA BDP + 1
  { 0xfffc, 0, insert_bdp, extract_bdp,
      PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The BF field in an X or XL form instruction.  */
#define BF BDPA + 1
  /* The CRFD field in an X form instruction.  */
#define CRFD BF
  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR },

  /* The BF field in an X or XL form instruction.  */
#define BFF BF + 1
  { 0x7, 23, NULL, NULL, 0 },

  /* An optional BF field.  This is used for comparison instructions,
     in which an omitted BF field is taken as zero.  */
#define OBF BFF + 1
  { 0x7, 23, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The BFA field in an X or XL form instruction.  */
#define BFA OBF + 1
  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR },

  /* The BO field in a B form instruction.  Certain values are
     illegal.  */
#define BO BFA + 1
#define BO_MASK (0x1f << 21)
  { 0x1f, 21, insert_bo, extract_bo, 0 },

  /* The BO field in a B form instruction when the + or - modifier is
     used.  This is like the BO field, but it must be even.  */
#define BOE BO + 1
  { 0x1e, 21, insert_boe, extract_boe, 0 },

#define BH BOE + 1
  { 0x3, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The BT field in an X or XL form instruction.  */
#define BT BH + 1
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_CR },

  /* The condition register number portion of the BI field in a B form
     or XL form instruction.  This is used for the extended
     conditional branch mnemonics, which set the lower two bits of the
     BI field.  This field is optional.  */
#define CR BT + 1
  { 0x7, 18, NULL, NULL, PPC_OPERAND_CR | PPC_OPERAND_OPTIONAL },

  /* The CRB field in an X form instruction.  */
#define CRB CR + 1
  /* The MB field in an M form instruction.  */
#define MB CRB
#define MB_MASK (0x1f << 6)
  { 0x1f, 6, NULL, NULL, 0 },

  /* The CRFS field in an X form instruction.  */
#define CRFS CRB + 1
  { 0x7, 0, NULL, NULL, PPC_OPERAND_CR },

  /* The CT field in an X form instruction.  */
#define CT CRFS + 1
  /* The MO field in an mbar instruction.  */
#define MO CT
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The D field in a D form instruction.  This is a displacement off
     a register, and implies that the next operand is a register in
     parentheses.  */
#define D CT + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DE field in a DE form instruction.  This is like D, but is 12
     bits only.  */
#define DE D + 1
  { 0xfff, 4, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DES field in a DES form instruction.  This is like DS, but is 14
     bits only (12 stored.)  */
#define DES DE + 1
  { 0x3ffc, 2, NULL, NULL, PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED },

  /* The DQ field in a DQ form instruction.  This is like D, but the
     lower four bits are forced to zero. */
#define DQ DES + 1
  { 0xfff0, 0, NULL, NULL,
    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DQ },

  /* The DS field in a DS form instruction.  This is like D, but the
     lower two bits are forced to zero.  */
#undef DS
#define DS DQ + 1
  { 0xfffc, 0, NULL, NULL,
    PPC_OPERAND_PARENS | PPC_OPERAND_SIGNED | PPC_OPERAND_DS },

  /* The E field in a wrteei instruction.  */
#define E DS + 1
  { 0x1, 15, NULL, NULL, 0 },

  /* The FL1 field in a POWER SC form instruction.  */
#define FL1 E + 1
  /* The U field in an X form instruction.  */
#define U FL1
  { 0xf, 12, NULL, NULL, 0 },

  /* The FL2 field in a POWER SC form instruction.  */
#define FL2 FL1 + 1
  { 0x7, 2, NULL, NULL, 0 },

  /* The FLM field in an XFL form instruction.  */
#define FLM FL2 + 1
  { 0xff, 17, NULL, NULL, 0 },

  /* The FRA field in an X or A form instruction.  */
#define FRA FLM + 1
#define FRA_MASK (0x1f << 16)
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRB field in an X or A form instruction.  */
#define FRB FRA + 1
#define FRB_MASK (0x1f << 11)
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRC field in an A form instruction.  */
#define FRC FRB + 1
#define FRC_MASK (0x1f << 6)
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_FPR },

  /* The FRS field in an X form instruction or the FRT field in a D, X
     or A form instruction.  */
#define FRS FRC + 1
#define FRT FRS
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_FPR },

  /* The FXM field in an XFX instruction.  */
#define FXM FRS + 1
  { 0xff, 12, insert_fxm, extract_fxm, 0 },

  /* Power4 version for mfcr.  */
#define FXM4 FXM + 1
  { 0xff, 12, insert_fxm, extract_fxm, PPC_OPERAND_OPTIONAL },

  /* The L field in a D or X form instruction.  */
#define L FXM4 + 1
  { 0x1, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The LEV field in a POWER SVC form instruction.  */
#define SVC_LEV L + 1
  { 0x7f, 5, NULL, NULL, 0 },

  /* The LEV field in an SC form instruction.  */
#define LEV SVC_LEV + 1
  { 0x7f, 5, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The LI field in an I form instruction.  The lower two bits are
     forced to zero.  */
#define LI LEV + 1
  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_RELATIVE | PPC_OPERAND_SIGNED },

  /* The LI field in an I form instruction when used as an absolute
     address.  */
#define LIA LI + 1
  { 0x3fffffc, 0, NULL, NULL, PPC_OPERAND_ABSOLUTE | PPC_OPERAND_SIGNED },

  /* The LS field in an X (sync) form instruction.  */
#define LS LIA + 1
  { 0x3, 21, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The ME field in an M form instruction.  */
#define ME LS + 1
#define ME_MASK (0x1f << 1)
  { 0x1f, 1, NULL, NULL, 0 },

  /* The MB and ME fields in an M form instruction expressed a single
     operand which is a bitmask indicating which bits to select.  This
     is a two operand form using PPC_OPERAND_NEXT.  See the
     description in opcode/ppc.h for what this means.  */
#define MBE ME + 1
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_OPTIONAL | PPC_OPERAND_NEXT },
  { -1, 0, insert_mbe, extract_mbe, 0 },

  /* The MB or ME field in an MD or MDS form instruction.  The high
     bit is wrapped to the low end.  */
#define MB6 MBE + 2
#define ME6 MB6
#define MB6_MASK (0x3f << 5)
  { 0x3f, 5, insert_mb6, extract_mb6, 0 },

  /* The NB field in an X form instruction.  The value 32 is stored as
     0.  */
#define NB MB6 + 1
  { 0x1f, 11, NULL, extract_nb, PPC_OPERAND_PLUS1 },

  /* The NSI field in a D form instruction.  This is the same as the
     SI field, only negated.  */
#define NSI NB + 1
  { 0xffff, 0, insert_nsi, extract_nsi,
      PPC_OPERAND_NEGATIVE | PPC_OPERAND_SIGNED },

  /* The RA field in an D, DS, DQ, X, XO, M, or MDS form instruction.  */
#define RA NSI + 1
#define RA_MASK (0x1f << 16)
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR },

  /* As above, but 0 in the RA field means zero, not r0.  */
#define RA0 RA + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in the DQ form lq instruction, which has special
     value restrictions.  */
#define RAQ RA0 + 1
  { 0x1f, 16, insert_raq, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in a D or X form instruction which is an updating
     load, which means that the RA field may not be zero and may not
     equal the RT field.  */
#define RAL RAQ + 1
  { 0x1f, 16, insert_ral, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in an lmw instruction, which has special value
     restrictions.  */
#define RAM RAL + 1
  { 0x1f, 16, insert_ram, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field in a D or X form instruction which is an updating
     store or an updating floating point load, which means that the RA
     field may not be zero.  */
#define RAS RAM + 1
  { 0x1f, 16, insert_ras, NULL, PPC_OPERAND_GPR_0 },

  /* The RA field of the tlbwe instruction, which is optional.  */
#define RAOPT RAS + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The RB field in an X, XO, M, or MDS form instruction.  */
#define RB RAOPT + 1
#define RB_MASK (0x1f << 11)
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_GPR },

  /* The RB field in an X form instruction when it must be the same as
     the RS field in the instruction.  This is used for extended
     mnemonics like mr.  */
#define RBS RB + 1
  { 0x1f, 11, insert_rbs, extract_rbs, PPC_OPERAND_FAKE },

  /* The RS field in a D, DS, X, XFX, XS, M, MD or MDS form
     instruction or the RT field in a D, DS, X, XFX or XO form
     instruction.  */
#define RS RBS + 1
#define RT RS
#define RT_MASK (0x1f << 21)
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR },

  /* The RS and RT fields of the DS form stq instruction, which have
     special value restrictions.  */
#define RSQ RS + 1
#define RTQ RSQ
  { 0x1e, 21, NULL, NULL, PPC_OPERAND_GPR_0 },

  /* The RS field of the tlbwe instruction, which is optional.  */
#define RSO RSQ + 1
#define RTO RSO
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_GPR | PPC_OPERAND_OPTIONAL },

  /* The SH field in an X or M form instruction.  */
#define SH RSO + 1
#define SH_MASK (0x1f << 11)
  /* The other UIMM field in a EVX form instruction.  */
#define EVUIMM SH
  { 0x1f, 11, NULL, NULL, 0 },

  /* The SH field in an MD form instruction.  This is split.  */
#define SH6 SH + 1
#define SH6_MASK ((0x1f << 11) | (1 << 1))
  { 0x3f, -1, insert_sh6, extract_sh6, 0 },

  /* The SH field of the tlbwe instruction, which is optional.  */
#define SHO SH6 + 1
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The SI field in a D form instruction.  */
#define SI SHO + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED },

  /* The SI field in a D form instruction when we accept a wide range
     of positive values.  */
#define SISIGNOPT SI + 1
  { 0xffff, 0, NULL, NULL, PPC_OPERAND_SIGNED | PPC_OPERAND_SIGNOPT },

  /* The SPR field in an XFX form instruction.  This is flipped--the
     lower 5 bits are stored in the upper 5 and vice- versa.  */
#define SPR SISIGNOPT + 1
#define PMR SPR
#define SPR_MASK (0x3ff << 11)
  { 0x3ff, 11, insert_spr, extract_spr, 0 },

  /* The BAT index number in an XFX form m[ft]ibat[lu] instruction.  */
#define SPRBAT SPR + 1
#define SPRBAT_MASK (0x3 << 17)
  { 0x3, 17, NULL, NULL, 0 },

  /* The SPRG register number in an XFX form m[ft]sprg instruction.  */
#define SPRG SPRBAT + 1
  { 0x1f, 16, insert_sprg, extract_sprg, 0 },

  /* The SR field in an X form instruction.  */
#define SR SPRG + 1
  { 0xf, 16, NULL, NULL, 0 },

  /* The STRM field in an X AltiVec form instruction.  */
#define STRM SR + 1
  { 0x3, 21, NULL, NULL, 0 },

  /* The SV field in a POWER SC form instruction.  */
#define SV STRM + 1
  { 0x3fff, 2, NULL, NULL, 0 },

  /* The TBR field in an XFX form instruction.  This is like the SPR
     field, but it is optional.  */
#define TBR SV + 1
  { 0x3ff, 11, insert_tbr, extract_tbr, PPC_OPERAND_OPTIONAL },

  /* The TO field in a D or X form instruction.  */
#define TO TBR + 1
#define TO_MASK (0x1f << 21)
  { 0x1f, 21, NULL, NULL, 0 },

  /* The UI field in a D form instruction.  */
#define UI TO + 1
  { 0xffff, 0, NULL, NULL, 0 },

  /* The VA field in a VA, VX or VXR form instruction.  */
#define VA UI + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_VR },

  /* The VB field in a VA, VX or VXR form instruction.  */
#define VB VA + 1
  { 0x1f, 11, NULL, NULL, PPC_OPERAND_VR },

  /* The VC field in a VA form instruction.  */
#define VC VB + 1
  { 0x1f, 6, NULL, NULL, PPC_OPERAND_VR },

  /* The VD or VS field in a VA, VX, VXR or X form instruction.  */
#define VD VC + 1
#define VS VD
  { 0x1f, 21, NULL, NULL, PPC_OPERAND_VR },

  /* The SIMM field in a VX form instruction.  */
#define SIMM VD + 1
  { 0x1f, 16, NULL, NULL, PPC_OPERAND_SIGNED},

  /* The UIMM field in a VX form instruction, and TE in Z form.  */
#define UIMM SIMM + 1
#define TE UIMM
  { 0x1f, 16, NULL, NULL, 0 },

  /* The SHB field in a VA form instruction.  */
#define SHB UIMM + 1
  { 0xf, 6, NULL, NULL, 0 },

  /* The other UIMM field in a half word EVX form instruction.  */
#define EVUIMM_2 SHB + 1
  { 0x3e, 10, NULL, NULL, PPC_OPERAND_PARENS },

  /* The other UIMM field in a word EVX form instruction.  */
#define EVUIMM_4 EVUIMM_2 + 1
  { 0x7c, 9, NULL, NULL, PPC_OPERAND_PARENS },

  /* The other UIMM field in a double EVX form instruction.  */
#define EVUIMM_8 EVUIMM_4 + 1
  { 0xf8, 8, NULL, NULL, PPC_OPERAND_PARENS },

  /* The WS field.  */
#define WS EVUIMM_8 + 1
  { 0x7, 11, NULL, NULL, 0 },

  /* The L field in an mtmsrd or A form instruction or W in an X form.  */
#define A_L WS + 1
#define W A_L
  { 0x1, 16, NULL, NULL, PPC_OPERAND_OPTIONAL },

#define RMC A_L + 1
  { 0x3, 9, NULL, NULL, 0 },

#define R RMC + 1
  { 0x1, 16, NULL, NULL, 0 },

#define SP R + 1
  { 0x3, 19, NULL, NULL, 0 },

#define S SP + 1
  { 0x1, 20, NULL, NULL, 0 },

  /* SH field starting at bit position 16.  */
#define SH16 S + 1
  /* The DCM and DGM fields in a Z form instruction.  */
#define DCM SH16
#define DGM DCM
  { 0x3f, 10, NULL, NULL, 0 },

  /* The EH field in larx instruction.  */
#define EH SH16 + 1
  { 0x1, 0, NULL, NULL, PPC_OPERAND_OPTIONAL },

  /* The L field in an mtfsf or XFL form instruction.  */
#define XFL_L EH + 1
  { 0x1, 25, NULL, NULL, PPC_OPERAND_OPTIONAL},
};

const unsigned int num_powerpc_operands = (sizeof (powerpc_operands)
                                           / sizeof (powerpc_operands[0]));

/* The functions used to insert and extract complicated operands.  */

/* The BA field in an XL form instruction when it must be the same as
   the BT field in the same instruction.  This operand is marked FAKE.
   The insertion function just copies the BT field into the BA field,
   and the extraction function just checks that the fields are the
   same.  */

static unsigned long
insert_bat (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 21) & 0x1f) << 16);
}

static long
extract_bat (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if (((insn >> 21) & 0x1f) != ((insn >> 16) & 0x1f))
    *invalid = 1;
  return 0;
}

/* The BB field in an XL form instruction when it must be the same as
   the BA field in the same instruction.  This operand is marked FAKE.
   The insertion function just copies the BA field into the BB field,
   and the extraction function just checks that the fields are the
   same.  */

static unsigned long
insert_bba (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 16) & 0x1f) << 11);
}

static long
extract_bba (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if (((insn >> 16) & 0x1f) != ((insn >> 11) & 0x1f))
    *invalid = 1;
  return 0;
}

/* The BD field in a B form instruction when the - modifier is used.
   This modifier means that the branch is not expected to be taken.
   For chips built to versions of the architecture prior to version 2
   (ie. not Power4 compatible), we set the y bit of the BO field to 1
   if the offset is negative.  When extracting, we require that the y
   bit be 1 and that the offset be positive, since if the y bit is 0
   we just want to print the normal form of the instruction.
   Power4 compatible targets use two bits, "a", and "t", instead of
   the "y" bit.  "at" == 00 => no hint, "at" == 01 => unpredictable,
   "at" == 10 => not taken, "at" == 11 => taken.  The "t" bit is 00001
   in BO field, the "a" bit is 00010 for branch on CR(BI) and 01000
   for branch on CTR.  We only handle the taken/not-taken hint here.
   Note that we don't relax the conditions tested here when
   disassembling with -Many because insns using extract_bdm and
   extract_bdp always occur in pairs.  One or the other will always
   be valid.  */

static unsigned long
insert_bdm (unsigned long insn,
            long value,
            int dialect,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if ((dialect & PPC_OPCODE_POWER4) == 0)
    {
      if ((value & 0x8000) != 0)
        insn |= 1 << 21;
    }
  else
    {
      if ((insn & (0x14 << 21)) == (0x04 << 21))
        insn |= 0x02 << 21;
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
        insn |= 0x08 << 21;
    }
  return insn | (value & 0xfffc);
}

static long
extract_bdm (unsigned long insn,
             int dialect,
             int *invalid)
{
  if ((dialect & PPC_OPCODE_POWER4) == 0)
    {
      if (((insn & (1 << 21)) == 0) != ((insn & (1 << 15)) == 0))
        *invalid = 1;
    }
  else
    {

      if ((insn & (0x17 << 21)) != (0x06 << 21)
          && (insn & (0x1d << 21)) != (0x18 << 21))
        *invalid = 1;
    }

  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}

/* The BD field in a B form instruction when the + modifier is used.
   This is like BDM, above, except that the branch is expected to be
   taken.  */

static unsigned long
insert_bdp (unsigned long insn,
            long value,
            int dialect,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if ((dialect & PPC_OPCODE_POWER4) == 0)
    {
      if ((value & 0x8000) == 0)
        insn |= 1 << 21;
    }
  else
    {
      if ((insn & (0x14 << 21)) == (0x04 << 21))
        insn |= 0x03 << 21;
      else if ((insn & (0x14 << 21)) == (0x10 << 21))
        insn |= 0x09 << 21;
    }
  return insn | (value & 0xfffc);
}

static long
extract_bdp (unsigned long insn,
             int dialect,
             int *invalid)
{
  if ((dialect & PPC_OPCODE_POWER4) == 0)
    {
      if (((insn & (1 << 21)) == 0) == ((insn & (1 << 15)) == 0))
        *invalid = 1;
    }
  else
    {
      if ((insn & (0x17 << 21)) != (0x07 << 21)
          && (insn & (0x1d << 21)) != (0x19 << 21))
        *invalid = 1;
    }

  return ((insn & 0xfffc) ^ 0x8000) - 0x8000;
}

/* Check for legal values of a BO field.  */

static int
valid_bo (long value, int dialect, int extract)
{
  if ((dialect & PPC_OPCODE_POWER4) == 0)
    {
      int valid;
      /* Certain encodings have bits that are required to be zero.
         These are (z must be zero, y may be anything):
             001zy
             011zy
             1z00y
             1z01y
             1z1zz
      */
      switch (value & 0x14)
        {
        default:
        case 0:
          valid = 1;
          break;
        case 0x4:
          valid = (value & 0x2) == 0;
          break;
        case 0x10:
          valid = (value & 0x8) == 0;
          break;
        case 0x14:
          valid = value == 0x14;
          break;
        }
      /* When disassembling with -Many, accept power4 encodings too.  */
      if (valid
          || (dialect & PPC_OPCODE_ANY) == 0
          || !extract)
        return valid;
    }

  /* Certain encodings have bits that are required to be zero.
     These are (z must be zero, a & t may be anything):
         0000z
         0001z
         0100z
         0101z
         001at
         011at
         1a00t
         1a01t
         1z1zz
  */
  if ((value & 0x14) == 0)
    return (value & 0x1) == 0;
  else if ((value & 0x14) == 0x14)
    return value == 0x14;
  else
    return 1;
}

/* The BO field in a B form instruction.  Warn about attempts to set
   the field to an illegal value.  */

static unsigned long
insert_bo (unsigned long insn,
           long value,
           int dialect,
           const char **errmsg)
{
  if (!valid_bo (value, dialect, 0))
    *errmsg = _("invalid conditional option");
  return insn | ((value & 0x1f) << 21);
}

static long
extract_bo (unsigned long insn,
            int dialect,
            int *invalid)
{
  long value;

  value = (insn >> 21) & 0x1f;
  if (!valid_bo (value, dialect, 1))
    *invalid = 1;
  return value;
}

/* The BO field in a B form instruction when the + or - modifier is
   used.  This is like the BO field, but it must be even.  When
   extracting it, we force it to be even.  */

static unsigned long
insert_boe (unsigned long insn,
            long value,
            int dialect,
            const char **errmsg)
{
  if (!valid_bo (value, dialect, 0))
    *errmsg = _("invalid conditional option");
  else if ((value & 1) != 0)
    *errmsg = _("attempt to set y bit when using + or - modifier");

  return insn | ((value & 0x1f) << 21);
}

static long
extract_boe (unsigned long insn,
             int dialect,
             int *invalid)
{
  long value;

  value = (insn >> 21) & 0x1f;
  if (!valid_bo (value, dialect, 1))
    *invalid = 1;
  return value & 0x1e;
}

/* FXM mask in mfcr and mtcrf instructions.  */

static unsigned long
insert_fxm (unsigned long insn,
            long value,
            int dialect,
            const char **errmsg)
{
  /* If we're handling the mfocrf and mtocrf insns ensure that exactly
     one bit of the mask field is set.  */
  if ((insn & (1 << 20)) != 0)
    {
      if (value == 0 || (value & -value) != value)
        {
          *errmsg = _("invalid mask field");
          value = 0;
        }
    }

  /* If the optional field on mfcr is missing that means we want to use
     the old form of the instruction that moves the whole cr.  In that
     case we'll have VALUE zero.  There doesn't seem to be a way to
     distinguish this from the case where someone writes mfcr %r3,0.  */
  else if (value == 0)
    ;

  /* If only one bit of the FXM field is set, we can use the new form
     of the instruction, which is faster.  Unlike the Power4 branch hint
     encoding, this is not backward compatible.  Do not generate the
     new form unless -mpower4 has been given, or -many and the two
     operand form of mfcr was used.  */
  else if ((value & -value) == value
           && ((dialect & PPC_OPCODE_POWER4) != 0
               || ((dialect & PPC_OPCODE_ANY) != 0
                   && (insn & (0x3ff << 1)) == 19 << 1)))
    insn |= 1 << 20;

  /* Any other value on mfcr is an error.  */
  else if ((insn & (0x3ff << 1)) == 19 << 1)
    {
      *errmsg = _("ignoring invalid mfcr mask");
      value = 0;
    }

  return insn | ((value & 0xff) << 12);
}

static long
extract_fxm (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  long mask = (insn >> 12) & 0xff;

  /* Is this a Power4 insn?  */
  if ((insn & (1 << 20)) != 0)
    {
      /* Exactly one bit of MASK should be set.  */
      if (mask == 0 || (mask & -mask) != mask)
        *invalid = 1;
    }

  /* Check that non-power4 form of mfcr has a zero MASK.  */
  else if ((insn & (0x3ff << 1)) == 19 << 1)
    {
      if (mask != 0)
        *invalid = 1;
    }

  return mask;
}

/* The MB and ME fields in an M form instruction expressed as a single
   operand which is itself a bitmask.  The extraction function always
   marks it as invalid, since we never want to recognize an
   instruction which uses a field of this type.  */

static unsigned long
insert_mbe (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  unsigned long uval, mask;
  int mb, me, mx, count, last;

  uval = value;

  if (uval == 0)
    {
      *errmsg = _("illegal bitmask");
      return insn;
    }

  mb = 0;
  me = 32;
  if ((uval & 1) != 0)
    last = 1;
  else
    last = 0;
  count = 0;

  /* mb: location of last 0->1 transition */
  /* me: location of last 1->0 transition */
  /* count: # transitions */

  for (mx = 0, mask = 1L << 31; mx < 32; ++mx, mask >>= 1)
    {
      if ((uval & mask) && !last)
        {
          ++count;
          mb = mx;
          last = 1;
        }
      else if (!(uval & mask) && last)
        {
          ++count;
          me = mx;
          last = 0;
        }
    }
  if (me == 0)
    me = 32;

  if (count != 2 && (count != 0 || ! last))
    *errmsg = _("illegal bitmask");

  return insn | (mb << 6) | ((me - 1) << 1);
}

static long
extract_mbe (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  long ret;
  int mb, me;
  int i;

  *invalid = 1;

  mb = (insn >> 6) & 0x1f;
  me = (insn >> 1) & 0x1f;
  if (mb < me + 1)
    {
      ret = 0;
      for (i = mb; i <= me; i++)
        ret |= 1L << (31 - i);
    }
  else if (mb == me + 1)
    ret = ~0;
  else /* (mb > me + 1) */
    {
      ret = ~0;
      for (i = me + 1; i < mb; i++)
        ret &= ~(1L << (31 - i));
    }
  return ret;
}

/* The MB or ME field in an MD or MDS form instruction.  The high bit
   is wrapped to the low end.  */

static unsigned long
insert_mb6 (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 6) | (value & 0x20);
}

static long
extract_mb6 (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 6) & 0x1f) | (insn & 0x20);
}

/* The NB field in an X form instruction.  The value 32 is stored as
   0.  */

static long
extract_nb (unsigned long insn,
            int dialect ATTRIBUTE_UNUSED,
            int *invalid ATTRIBUTE_UNUSED)
{
  long ret;

  ret = (insn >> 11) & 0x1f;
  if (ret == 0)
    ret = 32;
  return ret;
}

/* The NSI field in a D form instruction.  This is the same as the SI
   field, only negated.  The extraction function always marks it as
   invalid, since we never want to recognize an instruction which uses
   a field of this type.  */

static unsigned long
insert_nsi (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (-value & 0xffff);
}

static long
extract_nsi (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  *invalid = 1;
  return -(((insn & 0xffff) ^ 0x8000) - 0x8000);
}

/* The RA field in a D or X form instruction which is an updating
   load, which means that the RA field may not be zero and may not
   equal the RT field.  */

static unsigned long
insert_ral (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if (value == 0
      || (unsigned long) value == ((insn >> 21) & 0x1f))
    *errmsg = "invalid register operand when updating";
  return insn | ((value & 0x1f) << 16);
}

/* The RA field in an lmw instruction, which has special value
   restrictions.  */

static unsigned long
insert_ram (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if ((unsigned long) value >= ((insn >> 21) & 0x1f))
    *errmsg = _("index register in load range");
  return insn | ((value & 0x1f) << 16);
}

/* The RA field in the DQ form lq instruction, which has special
   value restrictions.  */

static unsigned long
insert_raq (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  long rtvalue = (insn & RT_MASK) >> 21;

  if (value == rtvalue)
    *errmsg = _("source and target register operands must be different");
  return insn | ((value & 0x1f) << 16);
}

/* The RA field in a D or X form instruction which is an updating
   store or an updating floating point load, which means that the RA
   field may not be zero.  */

static unsigned long
insert_ras (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg)
{
  if (value == 0)
    *errmsg = _("invalid register operand when updating");
  return insn | ((value & 0x1f) << 16);
}

/* The RB field in an X form instruction when it must be the same as
   the RS field in the instruction.  This is used for extended
   mnemonics like mr.  This operand is marked FAKE.  The insertion
   function just copies the BT field into the BA field, and the
   extraction function just checks that the fields are the same.  */

static unsigned long
insert_rbs (unsigned long insn,
            long value ATTRIBUTE_UNUSED,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | (((insn >> 21) & 0x1f) << 11);
}

static long
extract_rbs (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid)
{
  if (((insn >> 21) & 0x1f) != ((insn >> 11) & 0x1f))
    *invalid = 1;
  return 0;
}

/* The SH field in an MD form instruction.  This is split.  */

static unsigned long
insert_sh6 (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 11) | ((value & 0x20) >> 4);
}

static long
extract_sh6 (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 11) & 0x1f) | ((insn << 4) & 0x20);
}

/* The SPR field in an XFX form instruction.  This is flipped--the
   lower 5 bits are stored in the upper 5 and vice- versa.  */

static unsigned long
insert_spr (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
}

static long
extract_spr (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  return ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
}

/* Some dialects have 8 SPRG registers instead of the standard 4.  */

static unsigned long
insert_sprg (unsigned long insn,
             long value,
             int dialect,
             const char **errmsg)
{
  /* This check uses PPC_OPCODE_403 because PPC405 is later defined
     as a synonym.  If ever a 405 specific dialect is added this
     check should use that instead.  */
  if (value > 7
      || (value > 3
          && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
    *errmsg = _("invalid sprg number");

  /* If this is mfsprg4..7 then use spr 260..263 which can be read in
     user mode.  Anything else must use spr 272..279.  */
  if (value <= 3 || (insn & 0x100) != 0)
    value |= 0x10;

  return insn | ((value & 0x17) << 16);
}

static long
extract_sprg (unsigned long insn,
              int dialect,
              int *invalid)
{
  unsigned long val = (insn >> 16) & 0x1f;

  /* mfsprg can use 260..263 and 272..279.  mtsprg only uses spr 272..279
     If not BOOKE or 405, then both use only 272..275.  */
  if (val <= 3
      || (val < 0x10 && (insn & 0x100) != 0)
      || (val - 0x10 > 3
          && (dialect & (PPC_OPCODE_BOOKE | PPC_OPCODE_403)) == 0))
    *invalid = 1;
  return val & 7;
}

/* The TBR field in an XFX instruction.  This is just like SPR, but it
   is optional.  When TBR is omitted, it must be inserted as 268 (the
   magic number of the TB register).  These functions treat 0
   (indicating an omitted optional operand) as 268.  This means that
   ``mftb 4,0'' is not handled correctly.  This does not matter very
   much, since the architecture manual does not define mftb as
   accepting any values other than 268 or 269.  */

#define TB (268)

static unsigned long
insert_tbr (unsigned long insn,
            long value,
            int dialect ATTRIBUTE_UNUSED,
            const char **errmsg ATTRIBUTE_UNUSED)
{
  if (value == 0)
    value = TB;
  return insn | ((value & 0x1f) << 16) | ((value & 0x3e0) << 6);
}

static long
extract_tbr (unsigned long insn,
             int dialect ATTRIBUTE_UNUSED,
             int *invalid ATTRIBUTE_UNUSED)
{
  long ret;

  ret = ((insn >> 16) & 0x1f) | ((insn >> 6) & 0x3e0);
  if (ret == TB)
    ret = 0;
  return ret;
}

/* Macros used to form opcodes.  */

/* The main opcode.  */
#define OP(x) ((((unsigned long)(x)) & 0x3f) << 26)
#define OP_MASK OP (0x3f)

/* The main opcode combined with a trap code in the TO field of a D
   form instruction.  Used for extended mnemonics for the trap
   instructions.  */
#define OPTO(x,to) (OP (x) | ((((unsigned long)(to)) & 0x1f) << 21))
#define OPTO_MASK (OP_MASK | TO_MASK)

/* The main opcode combined with a comparison size bit in the L field
   of a D form or X form instruction.  Used for extended mnemonics for
   the comparison instructions.  */
#define OPL(x,l) (OP (x) | ((((unsigned long)(l)) & 1) << 21))
#define OPL_MASK OPL (0x3f,1)

/* An A form instruction.  */
#define A(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1) | (((unsigned long)(rc)) & 1))
#define A_MASK A (0x3f, 0x1f, 1)

/* An A_MASK with the FRB field fixed.  */
#define AFRB_MASK (A_MASK | FRB_MASK)

/* An A_MASK with the FRC field fixed.  */
#define AFRC_MASK (A_MASK | FRC_MASK)

/* An A_MASK with the FRA and FRC fields fixed.  */
#define AFRAFRC_MASK (A_MASK | FRA_MASK | FRC_MASK)

/* An AFRAFRC_MASK, but with L bit clear.  */
#define AFRALFRC_MASK (AFRAFRC_MASK & ~((unsigned long) 1 << 16))

/* A B form instruction.  */
#define B(op, aa, lk) (OP (op) | ((((unsigned long)(aa)) & 1) << 1) | ((lk) & 1))
#define B_MASK B (0x3f, 1, 1)

/* A B form instruction setting the BO field.  */
#define BBO(op, bo, aa, lk) (B ((op), (aa), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
#define BBO_MASK BBO (0x3f, 0x1f, 1, 1)

/* A BBO_MASK with the y bit of the BO field removed.  This permits
   matching a conditional branch regardless of the setting of the y
   bit.  Similarly for the 'at' bits used for power4 branch hints.  */
#define Y_MASK   (((unsigned long) 1) << 21)
#define AT1_MASK (((unsigned long) 3) << 21)
#define AT2_MASK (((unsigned long) 9) << 21)
#define BBOY_MASK  (BBO_MASK &~ Y_MASK)
#define BBOAT_MASK (BBO_MASK &~ AT1_MASK)

/* A B form instruction setting the BO field and the condition bits of
   the BI field.  */
#define BBOCB(op, bo, cb, aa, lk) \
  (BBO ((op), (bo), (aa), (lk)) | ((((unsigned long)(cb)) & 0x3) << 16))
#define BBOCB_MASK BBOCB (0x3f, 0x1f, 0x3, 1, 1)

/* A BBOCB_MASK with the y bit of the BO field removed.  */
#define BBOYCB_MASK (BBOCB_MASK &~ Y_MASK)
#define BBOATCB_MASK (BBOCB_MASK &~ AT1_MASK)
#define BBOAT2CB_MASK (BBOCB_MASK &~ AT2_MASK)

/* A BBOYCB_MASK in which the BI field is fixed.  */
#define BBOYBI_MASK (BBOYCB_MASK | BI_MASK)
#define BBOATBI_MASK (BBOAT2CB_MASK | BI_MASK)

/* An Context form instruction.  */
#define CTX(op, xop)   (OP (op) | (((unsigned long)(xop)) & 0x7))
#define CTX_MASK CTX(0x3f, 0x7)

/* An User Context form instruction.  */
#define UCTX(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define UCTX_MASK UCTX(0x3f, 0x1f)

/* The main opcode mask with the RA field clear.  */
#define DRA_MASK (OP_MASK | RA_MASK)

/* A DS form instruction.  */
#define DSO(op, xop) (OP (op) | ((xop) & 0x3))
#define DS_MASK DSO (0x3f, 3)

/* A DE form instruction.  */
#define DEO(op, xop) (OP (op) | ((xop) & 0xf))
#define DE_MASK DEO (0x3e, 0xf)

/* An EVSEL form instruction.  */
#define EVSEL(op, xop) (OP (op) | (((unsigned long)(xop)) & 0xff) << 3)
#define EVSEL_MASK EVSEL(0x3f, 0xff)

/* An M form instruction.  */
#define M(op, rc) (OP (op) | ((rc) & 1))
#define M_MASK M (0x3f, 1)

/* An M form instruction with the ME field specified.  */
#define MME(op, me, rc) (M ((op), (rc)) | ((((unsigned long)(me)) & 0x1f) << 1))

/* An M_MASK with the MB and ME fields fixed.  */
#define MMBME_MASK (M_MASK | MB_MASK | ME_MASK)

/* An M_MASK with the SH and ME fields fixed.  */
#define MSHME_MASK (M_MASK | SH_MASK | ME_MASK)

/* An MD form instruction.  */
#define MD(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x7) << 2) | ((rc) & 1))
#define MD_MASK MD (0x3f, 0x7, 1)

/* An MD_MASK with the MB field fixed.  */
#define MDMB_MASK (MD_MASK | MB6_MASK)

/* An MD_MASK with the SH field fixed.  */
#define MDSH_MASK (MD_MASK | SH6_MASK)

/* An MDS form instruction.  */
#define MDS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0xf) << 1) | ((rc) & 1))
#define MDS_MASK MDS (0x3f, 0xf, 1)

/* An MDS_MASK with the MB field fixed.  */
#define MDSMB_MASK (MDS_MASK | MB6_MASK)

/* An SC form instruction.  */
#define SC(op, sa, lk) (OP (op) | ((((unsigned long)(sa)) & 1) << 1) | ((lk) & 1))
#define SC_MASK (OP_MASK | (((unsigned long)0x3ff) << 16) | (((unsigned long)1) << 1) | 1)

/* An VX form instruction.  */
#define VX(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x7ff))

/* The mask for an VX form instruction.  */
#define VX_MASK VX(0x3f, 0x7ff)

/* An VA form instruction.  */
#define VXA(op, xop) (OP (op) | (((unsigned long)(xop)) & 0x03f))

/* The mask for an VA form instruction.  */
#define VXA_MASK VXA(0x3f, 0x3f)

/* An VXR form instruction.  */
#define VXR(op, xop, rc) (OP (op) | (((rc) & 1) << 10) | (((unsigned long)(xop)) & 0x3ff))

/* The mask for a VXR form instruction.  */
#define VXR_MASK VXR(0x3f, 0x3ff, 1)

/* An X form instruction.  */
#define X(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))

/* A Z form instruction.  */
#define Z(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1))

/* An X form instruction with the RC bit specified.  */
#define XRC(op, xop, rc) (X ((op), (xop)) | ((rc) & 1))

/* A Z form instruction with the RC bit specified.  */
#define ZRC(op, xop, rc) (Z ((op), (xop)) | ((rc) & 1))

/* The mask for an X form instruction.  */
#define X_MASK XRC (0x3f, 0x3ff, 1)

/* The mask for a Z form instruction.  */
#define Z_MASK ZRC (0x3f, 0x1ff, 1)
#define Z2_MASK ZRC (0x3f, 0xff, 1)

/* An X_MASK with the RA field fixed.  */
#define XRA_MASK (X_MASK | RA_MASK)

/* An XRA_MASK with the W field clear.  */
#define XWRA_MASK (XRA_MASK & ~((unsigned long) 1 << 16))

/* An X_MASK with the RB field fixed.  */
#define XRB_MASK (X_MASK | RB_MASK)

/* An X_MASK with the RT field fixed.  */
#define XRT_MASK (X_MASK | RT_MASK)

/* An XRT_MASK mask with the L bits clear.  */
#define XLRT_MASK (XRT_MASK & ~((unsigned long) 0x3 << 21))

/* An X_MASK with the RA and RB fields fixed.  */
#define XRARB_MASK (X_MASK | RA_MASK | RB_MASK)

/* An XRARB_MASK, but with the L bit clear.  */
#define XRLARB_MASK (XRARB_MASK & ~((unsigned long) 1 << 16))

/* An X_MASK with the RT and RA fields fixed.  */
#define XRTRA_MASK (X_MASK | RT_MASK | RA_MASK)

/* An XRTRA_MASK, but with L bit clear.  */
#define XRTLRA_MASK (XRTRA_MASK & ~((unsigned long) 1 << 21))

/* An X form instruction with the L bit specified.  */
#define XOPL(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 1) << 21))

/* The mask for an X form comparison instruction.  */
#define XCMP_MASK (X_MASK | (((unsigned long)1) << 22))

/* The mask for an X form comparison instruction with the L field
   fixed.  */
#define XCMPL_MASK (XCMP_MASK | (((unsigned long)1) << 21))

/* An X form trap instruction with the TO field specified.  */
#define XTO(op, xop, to) (X ((op), (xop)) | ((((unsigned long)(to)) & 0x1f) << 21))
#define XTO_MASK (X_MASK | TO_MASK)

/* An X form tlb instruction with the SH field specified.  */
#define XTLB(op, xop, sh) (X ((op), (xop)) | ((((unsigned long)(sh)) & 0x1f) << 11))
#define XTLB_MASK (X_MASK | SH_MASK)

/* An X form sync instruction.  */
#define XSYNC(op, xop, l) (X ((op), (xop)) | ((((unsigned long)(l)) & 3) << 21))

/* An X form sync instruction with everything filled in except the LS field.  */
#define XSYNC_MASK (0xff9fffff)

/* An X_MASK, but with the EH bit clear.  */
#define XEH_MASK (X_MASK & ~((unsigned long )1))

/* An X form AltiVec dss instruction.  */
#define XDSS(op, xop, a) (X ((op), (xop)) | ((((unsigned long)(a)) & 1) << 25))
#define XDSS_MASK XDSS(0x3f, 0x3ff, 1)

/* An XFL form instruction.  */
#define XFL(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1) | (((unsigned long)(rc)) & 1))
#define XFL_MASK XFL (0x3f, 0x3ff, 1)

/* An X form isel instruction.  */
#define XISEL(op, xop)  (OP (op) | ((((unsigned long)(xop)) & 0x1f) << 1))
#define XISEL_MASK      XISEL(0x3f, 0x1f)

/* An XL form instruction with the LK field set to 0.  */
#define XL(op, xop) (OP (op) | ((((unsigned long)(xop)) & 0x3ff) << 1))

/* An XL form instruction which uses the LK field.  */
#define XLLK(op, xop, lk) (XL ((op), (xop)) | ((lk) & 1))

/* The mask for an XL form instruction.  */
#define XL_MASK XLLK (0x3f, 0x3ff, 1)

/* An XL form instruction which explicitly sets the BO field.  */
#define XLO(op, bo, xop, lk) \
  (XLLK ((op), (xop), (lk)) | ((((unsigned long)(bo)) & 0x1f) << 21))
#define XLO_MASK (XL_MASK | BO_MASK)

/* An XL form instruction which explicitly sets the y bit of the BO
   field.  */
#define XLYLK(op, xop, y, lk) (XLLK ((op), (xop), (lk)) | ((((unsigned long)(y)) & 1) << 21))
#define XLYLK_MASK (XL_MASK | Y_MASK)

/* An XL form instruction which sets the BO field and the condition
   bits of the BI field.  */
#define XLOCB(op, bo, cb, xop, lk) \
  (XLO ((op), (bo), (xop), (lk)) | ((((unsigned long)(cb)) & 3) << 16))
#define XLOCB_MASK XLOCB (0x3f, 0x1f, 0x3, 0x3ff, 1)

/* An XL_MASK or XLYLK_MASK or XLOCB_MASK with the BB field fixed.  */
#define XLBB_MASK (XL_MASK | BB_MASK)
#define XLYBB_MASK (XLYLK_MASK | BB_MASK)
#define XLBOCBBB_MASK (XLOCB_MASK | BB_MASK)

/* A mask for branch instructions using the BH field.  */
#define XLBH_MASK (XL_MASK | (0x1c << 11))

/* An XL_MASK with the BO and BB fields fixed.  */
#define XLBOBB_MASK (XL_MASK | BO_MASK | BB_MASK)

/* An XL_MASK with the BO, BI and BB fields fixed.  */
#define XLBOBIBB_MASK (XL_MASK | BO_MASK | BI_MASK | BB_MASK)

/* An XO form instruction.  */
#define XO(op, xop, oe, rc) \
  (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 1) | ((((unsigned long)(oe)) & 1) << 10) | (((unsigned long)(rc)) & 1))
#define XO_MASK XO (0x3f, 0x1ff, 1, 1)

/* An XO_MASK with the RB field fixed.  */
#define XORB_MASK (XO_MASK | RB_MASK)

/* An XS form instruction.  */
#define XS(op, xop, rc) (OP (op) | ((((unsigned long)(xop)) & 0x1ff) << 2) | (((unsigned long)(rc)) & 1))
#define XS_MASK XS (0x3f, 0x1ff, 1)

/* A mask for the FXM version of an XFX form instruction.  */
#define XFXFXM_MASK (X_MASK | (1 << 11) | (1 << 20))

/* An XFX form instruction with the FXM field filled in.  */
#define XFXM(op, xop, fxm, p4) \
  (X ((op), (xop)) | ((((unsigned long)(fxm)) & 0xff) << 12) \
   | ((unsigned long)(p4) << 20))

/* An XFX form instruction with the SPR field filled in.  */
#define XSPR(op, xop, spr) \
  (X ((op), (xop)) | ((((unsigned long)(spr)) & 0x1f) << 16) | ((((unsigned long)(spr)) & 0x3e0) << 6))
#define XSPR_MASK (X_MASK | SPR_MASK)

/* An XFX form instruction with the SPR field filled in except for the
   SPRBAT field.  */
#define XSPRBAT_MASK (XSPR_MASK &~ SPRBAT_MASK)

/* An XFX form instruction with the SPR field filled in except for the
   SPRG field.  */
#define XSPRG_MASK (XSPR_MASK & ~(0x1f << 16))

/* An X form instruction with everything filled in except the E field.  */
#define XE_MASK (0xffff7fff)

/* An X form user context instruction.  */
#define XUC(op, xop)  (OP (op) | (((unsigned long)(xop)) & 0x1f))
#define XUC_MASK      XUC(0x3f, 0x1f)

/* The BO encodings used in extended conditional branch mnemonics.  */
#define BODNZF  (0x0)
#define BODNZFP (0x1)
#define BODZF   (0x2)
#define BODZFP  (0x3)
#define BODNZT  (0x8)
#define BODNZTP (0x9)
#define BODZT   (0xa)
#define BODZTP  (0xb)

#define BOF     (0x4)
#define BOFP    (0x5)
#define BOFM4   (0x6)
#define BOFP4   (0x7)
#define BOT     (0xc)
#define BOTP    (0xd)
#define BOTM4   (0xe)
#define BOTP4   (0xf)

#define BODNZ   (0x10)
#define BODNZP  (0x11)
#define BODZ    (0x12)
#define BODZP   (0x13)
#define BODNZM4 (0x18)
#define BODNZP4 (0x19)
#define BODZM4  (0x1a)
#define BODZP4  (0x1b)

#define BOU     (0x14)

/* The BI condition bit encodings used in extended conditional branch
   mnemonics.  */
#define CBLT    (0)
#define CBGT    (1)
#define CBEQ    (2)
#define CBSO    (3)

/* The TO encodings used in extended trap mnemonics.  */
#define TOLGT   (0x1)
#define TOLLT   (0x2)
#define TOEQ    (0x4)
#define TOLGE   (0x5)
#define TOLNL   (0x5)
#define TOLLE   (0x6)
#define TOLNG   (0x6)
#define TOGT    (0x8)
#define TOGE    (0xc)
#define TONL    (0xc)
#define TOLT    (0x10)
#define TOLE    (0x14)
#define TONG    (0x14)
#define TONE    (0x18)
#define TOU     (0x1f)

/* Smaller names for the flags so each entry in the opcodes table will
   fit on a single line.  */
#undef  PPC
#define PPC     PPC_OPCODE_PPC
#define PPCCOM  PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define NOPOWER4 PPC_OPCODE_NOPOWER4 | PPCCOM
#define POWER4  PPC_OPCODE_POWER4
#define POWER5  PPC_OPCODE_POWER5
#define POWER6  PPC_OPCODE_POWER6
#define CELL    PPC_OPCODE_CELL
#define PPC32   PPC_OPCODE_32 | PPC_OPCODE_PPC
#define PPC64   PPC_OPCODE_64 | PPC_OPCODE_PPC
#define PPC403  PPC_OPCODE_403
#define PPC405  PPC403
#define PPC440  PPC_OPCODE_440
#define PPC750  PPC
#define PPC860  PPC
#define PPCVEC  PPC_OPCODE_ALTIVEC
#define POWER   PPC_OPCODE_POWER
#define POWER2  PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define PPCPWR2 PPC_OPCODE_PPC | PPC_OPCODE_POWER | PPC_OPCODE_POWER2
#define POWER32 PPC_OPCODE_POWER | PPC_OPCODE_32
#define COM     PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON
#define COM32   PPC_OPCODE_POWER | PPC_OPCODE_PPC | PPC_OPCODE_COMMON | PPC_OPCODE_32
#define M601    PPC_OPCODE_POWER | PPC_OPCODE_601
#define PWRCOM  PPC_OPCODE_POWER | PPC_OPCODE_601 | PPC_OPCODE_COMMON
#define MFDEC1  PPC_OPCODE_POWER
#define MFDEC2  PPC_OPCODE_PPC | PPC_OPCODE_601 | PPC_OPCODE_BOOKE
#define BOOKE   PPC_OPCODE_BOOKE
#define BOOKE64 PPC_OPCODE_BOOKE64
#define CLASSIC PPC_OPCODE_CLASSIC
#define PPCE300 PPC_OPCODE_E300
#define PPCSPE  PPC_OPCODE_SPE
#define PPCISEL PPC_OPCODE_ISEL
#define PPCEFS  PPC_OPCODE_EFS
#define PPCBRLK PPC_OPCODE_BRLOCK
#define PPCPMR  PPC_OPCODE_PMR
#define PPCCHLK PPC_OPCODE_CACHELCK
#define PPCCHLK64       PPC_OPCODE_CACHELCK | PPC_OPCODE_BOOKE64
#define PPCRFMCI        PPC_OPCODE_RFMCI

/* The opcode table.

   The format of the opcode table is:

   NAME      OPCODE     MASK            FLAGS           { OPERANDS }

   NAME is the name of the instruction.
   OPCODE is the instruction opcode.
   MASK is the opcode mask; this is used to tell the disassembler
     which bits in the actual opcode must match OPCODE.
   FLAGS are flags indicated what processors support the instruction.

   OPERANDS is the list of operands.

   The disassembler reads the table in order and prints the first
   instruction which matches, so this table is sorted to put more
   specific instructions before more general instructions.  It is also
   sorted by major opcode.  */

const struct powerpc_opcode powerpc_opcodes[] = {
{ "attn",    X(0,256), X_MASK,          POWER4,         { 0 } },
{ "tdlgti",  OPTO(2,TOLGT), OPTO_MASK,  PPC64,          { RA, SI } },
{ "tdllti",  OPTO(2,TOLLT), OPTO_MASK,  PPC64,          { RA, SI } },
{ "tdeqi",   OPTO(2,TOEQ), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdlgei",  OPTO(2,TOLGE), OPTO_MASK,  PPC64,          { RA, SI } },
{ "tdlnli",  OPTO(2,TOLNL), OPTO_MASK,  PPC64,          { RA, SI } },
{ "tdllei",  OPTO(2,TOLLE), OPTO_MASK,  PPC64,          { RA, SI } },
{ "tdlngi",  OPTO(2,TOLNG), OPTO_MASK,  PPC64,          { RA, SI } },
{ "tdgti",   OPTO(2,TOGT), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdgei",   OPTO(2,TOGE), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdnli",   OPTO(2,TONL), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdlti",   OPTO(2,TOLT), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdlei",   OPTO(2,TOLE), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdngi",   OPTO(2,TONG), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdnei",   OPTO(2,TONE), OPTO_MASK,   PPC64,          { RA, SI } },
{ "tdi",     OP(2),     OP_MASK,        PPC64,          { TO, RA, SI } },

{ "twlgti",  OPTO(3,TOLGT), OPTO_MASK,  PPCCOM,         { RA, SI } },
{ "tlgti",   OPTO(3,TOLGT), OPTO_MASK,  PWRCOM,         { RA, SI } },
{ "twllti",  OPTO(3,TOLLT), OPTO_MASK,  PPCCOM,         { RA, SI } },
{ "tllti",   OPTO(3,TOLLT), OPTO_MASK,  PWRCOM,         { RA, SI } },
{ "tweqi",   OPTO(3,TOEQ), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "teqi",    OPTO(3,TOEQ), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twlgei",  OPTO(3,TOLGE), OPTO_MASK,  PPCCOM,         { RA, SI } },
{ "tlgei",   OPTO(3,TOLGE), OPTO_MASK,  PWRCOM,         { RA, SI } },
{ "twlnli",  OPTO(3,TOLNL), OPTO_MASK,  PPCCOM,         { RA, SI } },
{ "tlnli",   OPTO(3,TOLNL), OPTO_MASK,  PWRCOM,         { RA, SI } },
{ "twllei",  OPTO(3,TOLLE), OPTO_MASK,  PPCCOM,         { RA, SI } },
{ "tllei",   OPTO(3,TOLLE), OPTO_MASK,  PWRCOM,         { RA, SI } },
{ "twlngi",  OPTO(3,TOLNG), OPTO_MASK,  PPCCOM,         { RA, SI } },
{ "tlngi",   OPTO(3,TOLNG), OPTO_MASK,  PWRCOM,         { RA, SI } },
{ "twgti",   OPTO(3,TOGT), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tgti",    OPTO(3,TOGT), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twgei",   OPTO(3,TOGE), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tgei",    OPTO(3,TOGE), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twnli",   OPTO(3,TONL), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tnli",    OPTO(3,TONL), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twlti",   OPTO(3,TOLT), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tlti",    OPTO(3,TOLT), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twlei",   OPTO(3,TOLE), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tlei",    OPTO(3,TOLE), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twngi",   OPTO(3,TONG), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tngi",    OPTO(3,TONG), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twnei",   OPTO(3,TONE), OPTO_MASK,   PPCCOM,         { RA, SI } },
{ "tnei",    OPTO(3,TONE), OPTO_MASK,   PWRCOM,         { RA, SI } },
{ "twi",     OP(3),     OP_MASK,        PPCCOM,         { TO, RA, SI } },
{ "ti",      OP(3),     OP_MASK,        PWRCOM,         { TO, RA, SI } },

{ "macchw",     XO(4,172,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchw.",    XO(4,172,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwo",    XO(4,172,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwo.",   XO(4,172,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchws",    XO(4,236,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchws.",   XO(4,236,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwso",   XO(4,236,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwso.",  XO(4,236,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwsu",   XO(4,204,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwsu.",  XO(4,204,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwsuo",  XO(4,204,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwsuo.", XO(4,204,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwu",    XO(4,140,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwu.",   XO(4,140,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwuo",   XO(4,140,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "macchwuo.",  XO(4,140,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhw",     XO(4,44,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhw.",    XO(4,44,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwo",    XO(4,44,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwo.",   XO(4,44,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhws",    XO(4,108,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhws.",   XO(4,108,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwso",   XO(4,108,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwso.",  XO(4,108,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwsu",   XO(4,76,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwsu.",  XO(4,76,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwsuo",  XO(4,76,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwsuo.", XO(4,76,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwu",    XO(4,12,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwu.",   XO(4,12,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwuo",   XO(4,12,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "machhwuo.",  XO(4,12,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhw",     XO(4,428,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhw.",    XO(4,428,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwo",    XO(4,428,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwo.",   XO(4,428,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhws",    XO(4,492,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhws.",   XO(4,492,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwso",   XO(4,492,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwso.",  XO(4,492,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwsu",   XO(4,460,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwsu.",  XO(4,460,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwsuo",  XO(4,460,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwsuo.", XO(4,460,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwu",    XO(4,396,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwu.",   XO(4,396,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwuo",   XO(4,396,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "maclhwuo.",  XO(4,396,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "mulchw",     XRC(4,168,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulchw.",    XRC(4,168,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulchwu",    XRC(4,136,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulchwu.",   XRC(4,136,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulhhw",     XRC(4,40,0),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulhhw.",    XRC(4,40,1),   X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulhhwu",    XRC(4,8,0),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mulhhwu.",   XRC(4,8,1),    X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mullhw",     XRC(4,424,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mullhw.",    XRC(4,424,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mullhwu",    XRC(4,392,0),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "mullhwu.",   XRC(4,392,1),  X_MASK,  PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchw",    XO(4,174,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchw.",   XO(4,174,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchwo",   XO(4,174,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchwo.",  XO(4,174,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchws",   XO(4,238,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchws.",  XO(4,238,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchwso",  XO(4,238,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmacchwso.", XO(4,238,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhw",    XO(4,46,0,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhw.",   XO(4,46,0,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhwo",   XO(4,46,1,0),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhwo.",  XO(4,46,1,1),  XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhws",   XO(4,110,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhws.",  XO(4,110,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhwso",  XO(4,110,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmachhwso.", XO(4,110,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhw",    XO(4,430,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhw.",   XO(4,430,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhwo",   XO(4,430,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhwo.",  XO(4,430,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhws",   XO(4,494,0,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhws.",  XO(4,494,0,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhwso",  XO(4,494,1,0), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "nmaclhwso.", XO(4,494,1,1), XO_MASK, PPC405|PPC440,  { RT, RA, RB } },
{ "mfvscr",  VX(4, 1540), VX_MASK,      PPCVEC,         { VD } },
{ "mtvscr",  VX(4, 1604), VX_MASK,      PPCVEC,         { VB } },

  /* Double-precision opcodes.  */
  /* Some of these conflict with AltiVec, so move them before, since
     PPCVEC includes the PPC_OPCODE_PPC set.  */
{ "efscfd",   VX(4, 719), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdabs",   VX(4, 740), VX_MASK,      PPCEFS,         { RS, RA } },
{ "efdnabs",  VX(4, 741), VX_MASK,      PPCEFS,         { RS, RA } },
{ "efdneg",   VX(4, 742), VX_MASK,      PPCEFS,         { RS, RA } },
{ "efdadd",   VX(4, 736), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efdsub",   VX(4, 737), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efdmul",   VX(4, 744), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efddiv",   VX(4, 745), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efdcmpgt", VX(4, 748), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efdcmplt", VX(4, 749), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efdcmpeq", VX(4, 750), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efdtstgt", VX(4, 764), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efdtstlt", VX(4, 765), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efdtsteq", VX(4, 766), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efdcfsi",  VX(4, 753), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdcfsid", VX(4, 739), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdcfui",  VX(4, 752), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdcfuid", VX(4, 738), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdcfsf",  VX(4, 755), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdcfuf",  VX(4, 754), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctsi",  VX(4, 757), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctsidz",VX(4, 747), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctsiz", VX(4, 762), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctui",  VX(4, 756), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctuidz",VX(4, 746), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctuiz", VX(4, 760), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctsf",  VX(4, 759), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdctuf",  VX(4, 758), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efdcfs",   VX(4, 751), VX_MASK,      PPCEFS,         { RS, RB } },
  /* End of double-precision opcodes.  */

{ "vaddcuw", VX(4,  384), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vaddfp",  VX(4,   10), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vaddsbs", VX(4,  768), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vaddshs", VX(4,  832), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vaddsws", VX(4,  896), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vaddubm", VX(4,    0), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vaddubs", VX(4,  512), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vadduhm", VX(4,   64), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vadduhs", VX(4,  576), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vadduwm", VX(4,  128), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vadduws", VX(4,  640), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vand",    VX(4, 1028), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vandc",   VX(4, 1092), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vavgsb",  VX(4, 1282), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vavgsh",  VX(4, 1346), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vavgsw",  VX(4, 1410), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vavgub",  VX(4, 1026), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vavguh",  VX(4, 1090), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vavguw",  VX(4, 1154), VX_MASK,      PPCVEC,         { VD, VA, VB } },
{ "vcfsx",   VX(4,  842), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
{ "vcfux",   VX(4,  778), VX_MASK,      PPCVEC,         { VD, VB, UIMM } },
{ "vcmpbfp",   VXR(4, 966, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpbfp.",  VXR(4, 966, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpeqfp",  VXR(4, 198, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpeqfp.", VXR(4, 198, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpequb",  VXR(4,   6, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpequb.", VXR(4,   6, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpequh",  VXR(4,  70, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpequh.", VXR(4,  70, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpequw",  VXR(4, 134, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpequw.", VXR(4, 134, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgefp",  VXR(4, 454, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgefp.", VXR(4, 454, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtfp",  VXR(4, 710, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtfp.", VXR(4, 710, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtsb",  VXR(4, 774, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtsb.", VXR(4, 774, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtsh",  VXR(4, 838, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtsh.", VXR(4, 838, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtsw",  VXR(4, 902, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtsw.", VXR(4, 902, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtub",  VXR(4, 518, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtub.", VXR(4, 518, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtuh",  VXR(4, 582, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtuh.", VXR(4, 582, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtuw",  VXR(4, 646, 0), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vcmpgtuw.", VXR(4, 646, 1), VXR_MASK, PPCVEC,        { VD, VA, VB } },
{ "vctsxs",    VX(4,  970), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
{ "vctuxs",    VX(4,  906), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
{ "vexptefp",  VX(4,  394), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vlogefp",   VX(4,  458), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vmaddfp",   VXA(4,  46), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
{ "vmaxfp",    VX(4, 1034), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmaxsb",    VX(4,  258), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmaxsh",    VX(4,  322), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmaxsw",    VX(4,  386), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmaxub",    VX(4,    2), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmaxuh",    VX(4,   66), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmaxuw",    VX(4,  130), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmhaddshs", VXA(4,  32), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmhraddshs", VXA(4, 33), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vminfp",    VX(4, 1098), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vminsb",    VX(4,  770), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vminsh",    VX(4,  834), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vminsw",    VX(4,  898), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vminub",    VX(4,  514), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vminuh",    VX(4,  578), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vminuw",    VX(4,  642), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmladduhm", VXA(4,  34), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmrghb",    VX(4,   12), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmrghh",    VX(4,   76), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmrghw",    VX(4,  140), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmrglb",    VX(4,  268), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmrglh",    VX(4,  332), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmrglw",    VX(4,  396), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmsummbm",  VXA(4,  37), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmsumshm",  VXA(4,  40), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmsumshs",  VXA(4,  41), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmsumubm",  VXA(4,  36), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmsumuhm",  VXA(4,  38), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmsumuhs",  VXA(4,  39), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vmulesb",   VX(4,  776), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmulesh",   VX(4,  840), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmuleub",   VX(4,  520), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmuleuh",   VX(4,  584), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmulosb",   VX(4,  264), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmulosh",   VX(4,  328), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmuloub",   VX(4,    8), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vmulouh",   VX(4,   72), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vnmsubfp",  VXA(4,  47), VXA_MASK,   PPCVEC,         { VD, VA, VC, VB } },
{ "vnor",      VX(4, 1284), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vor",       VX(4, 1156), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vperm",     VXA(4,  43), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vpkpx",     VX(4,  782), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkshss",   VX(4,  398), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkshus",   VX(4,  270), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkswss",   VX(4,  462), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkswus",   VX(4,  334), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkuhum",   VX(4,   14), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkuhus",   VX(4,  142), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkuwum",   VX(4,   78), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vpkuwus",   VX(4,  206), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vrefp",     VX(4,  266), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vrfim",     VX(4,  714), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vrfin",     VX(4,  522), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vrfip",     VX(4,  650), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vrfiz",     VX(4,  586), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vrlb",      VX(4,    4), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vrlh",      VX(4,   68), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vrlw",      VX(4,  132), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vrsqrtefp", VX(4,  330), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vsel",      VXA(4,  42), VXA_MASK,   PPCVEC,         { VD, VA, VB, VC } },
{ "vsl",       VX(4,  452), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vslb",      VX(4,  260), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsldoi",    VXA(4,  44), VXA_MASK,   PPCVEC,         { VD, VA, VB, SHB } },
{ "vslh",      VX(4,  324), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vslo",      VX(4, 1036), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vslw",      VX(4,  388), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vspltb",    VX(4,  524), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
{ "vsplth",    VX(4,  588), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
{ "vspltisb",  VX(4,  780), VX_MASK,    PPCVEC,         { VD, SIMM } },
{ "vspltish",  VX(4,  844), VX_MASK,    PPCVEC,         { VD, SIMM } },
{ "vspltisw",  VX(4,  908), VX_MASK,    PPCVEC,         { VD, SIMM } },
{ "vspltw",    VX(4,  652), VX_MASK,    PPCVEC,         { VD, VB, UIMM } },
{ "vsr",       VX(4,  708), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsrab",     VX(4,  772), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsrah",     VX(4,  836), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsraw",     VX(4,  900), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsrb",      VX(4,  516), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsrh",      VX(4,  580), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsro",      VX(4, 1100), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsrw",      VX(4,  644), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubcuw",   VX(4, 1408), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubfp",    VX(4,   74), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubsbs",   VX(4, 1792), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubshs",   VX(4, 1856), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubsws",   VX(4, 1920), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsububm",   VX(4, 1024), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsububs",   VX(4, 1536), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubuhm",   VX(4, 1088), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubuhs",   VX(4, 1600), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubuwm",   VX(4, 1152), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsubuws",   VX(4, 1664), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsumsws",   VX(4, 1928), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsum2sws",  VX(4, 1672), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsum4sbs",  VX(4, 1800), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsum4shs",  VX(4, 1608), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vsum4ubs",  VX(4, 1544), VX_MASK,    PPCVEC,         { VD, VA, VB } },
{ "vupkhpx",   VX(4,  846), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vupkhsb",   VX(4,  526), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vupkhsh",   VX(4,  590), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vupklpx",   VX(4,  974), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vupklsb",   VX(4,  654), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vupklsh",   VX(4,  718), VX_MASK,    PPCVEC,         { VD, VB } },
{ "vxor",      VX(4, 1220), VX_MASK,    PPCVEC,         { VD, VA, VB } },

{ "evaddw",    VX(4, 512), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evaddiw",   VX(4, 514), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
{ "evsubfw",   VX(4, 516), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evsubw",    VX(4, 516), VX_MASK,     PPCSPE,         { RS, RB, RA } },
{ "evsubifw",  VX(4, 518), VX_MASK,     PPCSPE,         { RS, UIMM, RB } },
{ "evsubiw",   VX(4, 518), VX_MASK,     PPCSPE,         { RS, RB, UIMM } },
{ "evabs",     VX(4, 520), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evneg",     VX(4, 521), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evextsb",   VX(4, 522), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evextsh",   VX(4, 523), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evrndw",    VX(4, 524), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evcntlzw",  VX(4, 525), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evcntlsw",  VX(4, 526), VX_MASK,     PPCSPE,         { RS, RA } },

{ "brinc",     VX(4, 527), VX_MASK,     PPCSPE,         { RS, RA, RB } },

{ "evand",     VX(4, 529), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evandc",    VX(4, 530), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evmr",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
{ "evor",      VX(4, 535), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evorc",     VX(4, 539), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evxor",     VX(4, 534), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "eveqv",     VX(4, 537), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evnand",    VX(4, 542), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evnot",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, BBA } },
{ "evnor",     VX(4, 536), VX_MASK,     PPCSPE,         { RS, RA, RB } },

{ "evrlw",     VX(4, 552), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evrlwi",    VX(4, 554), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
{ "evslw",     VX(4, 548), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evslwi",    VX(4, 550), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
{ "evsrws",    VX(4, 545), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evsrwu",    VX(4, 544), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evsrwis",   VX(4, 547), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
{ "evsrwiu",   VX(4, 546), VX_MASK,     PPCSPE,         { RS, RA, EVUIMM } },
{ "evsplati",  VX(4, 553), VX_MASK,     PPCSPE,         { RS, SIMM } },
{ "evsplatfi", VX(4, 555), VX_MASK,     PPCSPE,         { RS, SIMM } },
{ "evmergehi", VX(4, 556), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evmergelo", VX(4, 557), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evmergehilo",VX(4,558), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evmergelohi",VX(4,559), VX_MASK,     PPCSPE,         { RS, RA, RB } },

{ "evcmpgts",  VX(4, 561), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evcmpgtu",  VX(4, 560), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evcmplts",  VX(4, 563), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evcmpltu",  VX(4, 562), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evcmpeq",   VX(4, 564), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evsel",     EVSEL(4,79),EVSEL_MASK,  PPCSPE,         { RS, RA, RB, CRFS } },

{ "evldd",     VX(4, 769), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
{ "evlddx",    VX(4, 768), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evldw",     VX(4, 771), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
{ "evldwx",    VX(4, 770), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evldh",     VX(4, 773), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
{ "evldhx",    VX(4, 772), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evlwhe",    VX(4, 785), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evlwhex",   VX(4, 784), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evlwhou",   VX(4, 789), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evlwhoux",  VX(4, 788), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evlwhos",   VX(4, 791), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evlwhosx",  VX(4, 790), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evlwwsplat",VX(4, 793), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evlwwsplatx",VX(4, 792), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evlwhsplat",VX(4, 797), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evlwhsplatx",VX(4, 796), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evlhhesplat",VX(4, 777), VX_MASK,    PPCSPE,         { RS, EVUIMM_2, RA } },
{ "evlhhesplatx",VX(4, 776), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evlhhousplat",VX(4, 781), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
{ "evlhhousplatx",VX(4, 780), VX_MASK,  PPCSPE,         { RS, RA, RB } },
{ "evlhhossplat",VX(4, 783), VX_MASK,   PPCSPE,         { RS, EVUIMM_2, RA } },
{ "evlhhossplatx",VX(4, 782), VX_MASK,  PPCSPE,         { RS, RA, RB } },

{ "evstdd",    VX(4, 801), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
{ "evstddx",   VX(4, 800), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evstdw",    VX(4, 803), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
{ "evstdwx",   VX(4, 802), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evstdh",    VX(4, 805), VX_MASK,     PPCSPE,         { RS, EVUIMM_8, RA } },
{ "evstdhx",   VX(4, 804), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evstwwe",   VX(4, 825), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evstwwex",  VX(4, 824), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evstwwo",   VX(4, 829), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evstwwox",  VX(4, 828), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evstwhe",   VX(4, 817), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evstwhex",  VX(4, 816), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evstwho",   VX(4, 821), VX_MASK,     PPCSPE,         { RS, EVUIMM_4, RA } },
{ "evstwhox",  VX(4, 820), VX_MASK,     PPCSPE,         { RS, RA, RB } },

{ "evfsabs",   VX(4, 644), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evfsnabs",  VX(4, 645), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evfsneg",   VX(4, 646), VX_MASK,     PPCSPE,         { RS, RA } },
{ "evfsadd",   VX(4, 640), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evfssub",   VX(4, 641), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evfsmul",   VX(4, 648), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evfsdiv",   VX(4, 649), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evfscmpgt", VX(4, 652), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evfscmplt", VX(4, 653), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evfscmpeq", VX(4, 654), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evfststgt", VX(4, 668), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evfststlt", VX(4, 669), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evfststeq", VX(4, 670), VX_MASK,     PPCSPE,         { CRFD, RA, RB } },
{ "evfscfui",  VX(4, 656), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfsctuiz", VX(4, 664), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfscfsi",  VX(4, 657), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfscfuf",  VX(4, 658), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfscfsf",  VX(4, 659), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfsctui",  VX(4, 660), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfsctsi",  VX(4, 661), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfsctsiz", VX(4, 666), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfsctuf",  VX(4, 662), VX_MASK,     PPCSPE,         { RS, RB } },
{ "evfsctsf",  VX(4, 663), VX_MASK,     PPCSPE,         { RS, RB } },

{ "efsabs",   VX(4, 708), VX_MASK,      PPCEFS,         { RS, RA } },
{ "efsnabs",  VX(4, 709), VX_MASK,      PPCEFS,         { RS, RA } },
{ "efsneg",   VX(4, 710), VX_MASK,      PPCEFS,         { RS, RA } },
{ "efsadd",   VX(4, 704), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efssub",   VX(4, 705), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efsmul",   VX(4, 712), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efsdiv",   VX(4, 713), VX_MASK,      PPCEFS,         { RS, RA, RB } },
{ "efscmpgt", VX(4, 716), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efscmplt", VX(4, 717), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efscmpeq", VX(4, 718), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efststgt", VX(4, 732), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efststlt", VX(4, 733), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efststeq", VX(4, 734), VX_MASK,      PPCEFS,         { CRFD, RA, RB } },
{ "efscfui",  VX(4, 720), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efsctuiz", VX(4, 728), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efscfsi",  VX(4, 721), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efscfuf",  VX(4, 722), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efscfsf",  VX(4, 723), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efsctui",  VX(4, 724), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efsctsi",  VX(4, 725), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efsctsiz", VX(4, 730), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efsctuf",  VX(4, 726), VX_MASK,      PPCEFS,         { RS, RB } },
{ "efsctsf",  VX(4, 727), VX_MASK,      PPCEFS,         { RS, RB } },

{ "evmhossf",  VX(4, 1031), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhossfa", VX(4, 1063), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhosmf",  VX(4, 1039), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhosmfa", VX(4, 1071), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhosmi",  VX(4, 1037), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhosmia", VX(4, 1069), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhoumi",  VX(4, 1036), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhoumia", VX(4, 1068), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhessf",  VX(4, 1027), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhessfa", VX(4, 1059), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhesmf",  VX(4, 1035), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhesmfa", VX(4, 1067), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhesmi",  VX(4, 1033), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmhesmia", VX(4, 1065), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmheumi",  VX(4, 1032), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmheumia", VX(4, 1064), VX_MASK,    PPCSPE,         { RS, RA, RB } },

{ "evmhossfaaw",VX(4, 1287), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhossiaaw",VX(4, 1285), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhosmfaaw",VX(4, 1295), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhosmiaaw",VX(4, 1293), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhousiaaw",VX(4, 1284), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhoumiaaw",VX(4, 1292), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhessfaaw",VX(4, 1283), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhessiaaw",VX(4, 1281), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhesmfaaw",VX(4, 1291), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhesmiaaw",VX(4, 1289), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmheusiaaw",VX(4, 1280), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmheumiaaw",VX(4, 1288), VX_MASK,   PPCSPE,         { RS, RA, RB } },

{ "evmhossfanw",VX(4, 1415), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhossianw",VX(4, 1413), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhosmfanw",VX(4, 1423), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhosmianw",VX(4, 1421), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhousianw",VX(4, 1412), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhoumianw",VX(4, 1420), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhessfanw",VX(4, 1411), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhessianw",VX(4, 1409), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhesmfanw",VX(4, 1419), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhesmianw",VX(4, 1417), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmheusianw",VX(4, 1408), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmheumianw",VX(4, 1416), VX_MASK,   PPCSPE,         { RS, RA, RB } },

{ "evmhogsmfaa",VX(4, 1327), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhogsmiaa",VX(4, 1325), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhogumiaa",VX(4, 1324), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhegsmfaa",VX(4, 1323), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhegsmiaa",VX(4, 1321), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhegumiaa",VX(4, 1320), VX_MASK,   PPCSPE,         { RS, RA, RB } },

{ "evmhogsmfan",VX(4, 1455), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhogsmian",VX(4, 1453), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhogumian",VX(4, 1452), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhegsmfan",VX(4, 1451), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhegsmian",VX(4, 1449), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmhegumian",VX(4, 1448), VX_MASK,   PPCSPE,         { RS, RA, RB } },

{ "evmwhssf",  VX(4, 1095), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhssfa", VX(4, 1127), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhsmf",  VX(4, 1103), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhsmfa", VX(4, 1135), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhsmi",  VX(4, 1101), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhsmia", VX(4, 1133), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhumi",  VX(4, 1100), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwhumia", VX(4, 1132), VX_MASK,    PPCSPE,         { RS, RA, RB } },

{ "evmwlumi",  VX(4, 1096), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwlumia", VX(4, 1128), VX_MASK,    PPCSPE,         { RS, RA, RB } },

{ "evmwlssiaaw",VX(4, 1345), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmwlsmiaaw",VX(4, 1353), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmwlusiaaw",VX(4, 1344), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmwlumiaaw",VX(4, 1352), VX_MASK,   PPCSPE,         { RS, RA, RB } },

{ "evmwlssianw",VX(4, 1473), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmwlsmianw",VX(4, 1481), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmwlusianw",VX(4, 1472), VX_MASK,   PPCSPE,         { RS, RA, RB } },
{ "evmwlumianw",VX(4, 1480), VX_MASK,   PPCSPE,         { RS, RA, RB } },

{ "evmwssf",   VX(4, 1107), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwssfa",  VX(4, 1139), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmf",   VX(4, 1115), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmfa",  VX(4, 1147), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmi",   VX(4, 1113), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmia",  VX(4, 1145), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwumi",   VX(4, 1112), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwumia",  VX(4, 1144), VX_MASK,    PPCSPE,         { RS, RA, RB } },

{ "evmwssfaa", VX(4, 1363), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmfaa", VX(4, 1371), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmiaa", VX(4, 1369), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwumiaa", VX(4, 1368), VX_MASK,    PPCSPE,         { RS, RA, RB } },

{ "evmwssfan", VX(4, 1491), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmfan", VX(4, 1499), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwsmian", VX(4, 1497), VX_MASK,    PPCSPE,         { RS, RA, RB } },
{ "evmwumian", VX(4, 1496), VX_MASK,    PPCSPE,         { RS, RA, RB } },

{ "evaddssiaaw",VX(4, 1217), VX_MASK,   PPCSPE,         { RS, RA } },
{ "evaddsmiaaw",VX(4, 1225), VX_MASK,   PPCSPE,         { RS, RA } },
{ "evaddusiaaw",VX(4, 1216), VX_MASK,   PPCSPE,         { RS, RA } },
{ "evaddumiaaw",VX(4, 1224), VX_MASK,   PPCSPE,         { RS, RA } },

{ "evsubfssiaaw",VX(4, 1219), VX_MASK,  PPCSPE,         { RS, RA } },
{ "evsubfsmiaaw",VX(4, 1227), VX_MASK,  PPCSPE,         { RS, RA } },
{ "evsubfusiaaw",VX(4, 1218), VX_MASK,  PPCSPE,         { RS, RA } },
{ "evsubfumiaaw",VX(4, 1226), VX_MASK,  PPCSPE,         { RS, RA } },

{ "evmra",    VX(4, 1220), VX_MASK,     PPCSPE,         { RS, RA } },

{ "evdivws",  VX(4, 1222), VX_MASK,     PPCSPE,         { RS, RA, RB } },
{ "evdivwu",  VX(4, 1223), VX_MASK,     PPCSPE,         { RS, RA, RB } },

{ "mulli",   OP(7),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
{ "muli",    OP(7),     OP_MASK,        PWRCOM,         { RT, RA, SI } },

{ "subfic",  OP(8),     OP_MASK,        PPCCOM,         { RT, RA, SI } },
{ "sfi",     OP(8),     OP_MASK,        PWRCOM,         { RT, RA, SI } },

{ "dozi",    OP(9),     OP_MASK,        M601,           { RT, RA, SI } },

{ "bce",     B(9,0,0),  B_MASK,         BOOKE64,        { BO, BI, BD } },
{ "bcel",    B(9,0,1),  B_MASK,         BOOKE64,        { BO, BI, BD } },
{ "bcea",    B(9,1,0),  B_MASK,         BOOKE64,        { BO, BI, BDA } },
{ "bcela",   B(9,1,1),  B_MASK,         BOOKE64,        { BO, BI, BDA } },

{ "cmplwi",  OPL(10,0), OPL_MASK,       PPCCOM,         { OBF, RA, UI } },
{ "cmpldi",  OPL(10,1), OPL_MASK,       PPC64,          { OBF, RA, UI } },
{ "cmpli",   OP(10),    OP_MASK,        PPC,            { BF, L, RA, UI } },
{ "cmpli",   OP(10),    OP_MASK,        PWRCOM,         { BF, RA, UI } },

{ "cmpwi",   OPL(11,0), OPL_MASK,       PPCCOM,         { OBF, RA, SI } },
{ "cmpdi",   OPL(11,1), OPL_MASK,       PPC64,          { OBF, RA, SI } },
{ "cmpi",    OP(11),    OP_MASK,        PPC,            { BF, L, RA, SI } },
{ "cmpi",    OP(11),    OP_MASK,        PWRCOM,         { BF, RA, SI } },

{ "addic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
{ "ai",      OP(12),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
{ "subic",   OP(12),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },

{ "addic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, SI } },
{ "ai.",     OP(13),    OP_MASK,        PWRCOM,         { RT, RA, SI } },
{ "subic.",  OP(13),    OP_MASK,        PPCCOM,         { RT, RA, NSI } },

{ "li",      OP(14),    DRA_MASK,       PPCCOM,         { RT, SI } },
{ "lil",     OP(14),    DRA_MASK,       PWRCOM,         { RT, SI } },
{ "addi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, SI } },
{ "cal",     OP(14),    OP_MASK,        PWRCOM,         { RT, D, RA0 } },
{ "subi",    OP(14),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },
{ "la",      OP(14),    OP_MASK,        PPCCOM,         { RT, D, RA0 } },

{ "lis",     OP(15),    DRA_MASK,       PPCCOM,         { RT, SISIGNOPT } },
{ "liu",     OP(15),    DRA_MASK,       PWRCOM,         { RT, SISIGNOPT } },
{ "addis",   OP(15),    OP_MASK,        PPCCOM,         { RT,RA0,SISIGNOPT } },
{ "cau",     OP(15),    OP_MASK,        PWRCOM,         { RT,RA0,SISIGNOPT } },
{ "subis",   OP(15),    OP_MASK,        PPCCOM,         { RT, RA0, NSI } },

{ "bdnz-",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDM } },
{ "bdnz+",   BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BDP } },
{ "bdnz",    BBO(16,BODNZ,0,0),      BBOATBI_MASK, PPCCOM,      { BD } },
{ "bdn",     BBO(16,BODNZ,0,0),      BBOATBI_MASK, PWRCOM,      { BD } },
{ "bdnzl-",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDM } },
{ "bdnzl+",  BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BDP } },
{ "bdnzl",   BBO(16,BODNZ,0,1),      BBOATBI_MASK, PPCCOM,      { BD } },
{ "bdnl",    BBO(16,BODNZ,0,1),      BBOATBI_MASK, PWRCOM,      { BD } },
{ "bdnza-",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDMA } },
{ "bdnza+",  BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDPA } },
{ "bdnza",   BBO(16,BODNZ,1,0),      BBOATBI_MASK, PPCCOM,      { BDA } },
{ "bdna",    BBO(16,BODNZ,1,0),      BBOATBI_MASK, PWRCOM,      { BDA } },
{ "bdnzla-", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDMA } },
{ "bdnzla+", BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDPA } },
{ "bdnzla",  BBO(16,BODNZ,1,1),      BBOATBI_MASK, PPCCOM,      { BDA } },
{ "bdnla",   BBO(16,BODNZ,1,1),      BBOATBI_MASK, PWRCOM,      { BDA } },
{ "bdz-",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDM } },
{ "bdz+",    BBO(16,BODZ,0,0),       BBOATBI_MASK, PPCCOM,      { BDP } },
{ "bdz",     BBO(16,BODZ,0,0),       BBOATBI_MASK, COM,         { BD } },
{ "bdzl-",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDM } },
{ "bdzl+",   BBO(16,BODZ,0,1),       BBOATBI_MASK, PPCCOM,      { BDP } },
{ "bdzl",    BBO(16,BODZ,0,1),       BBOATBI_MASK, COM,         { BD } },
{ "bdza-",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDMA } },
{ "bdza+",   BBO(16,BODZ,1,0),       BBOATBI_MASK, PPCCOM,      { BDPA } },
{ "bdza",    BBO(16,BODZ,1,0),       BBOATBI_MASK, COM,         { BDA } },
{ "bdzla-",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDMA } },
{ "bdzla+",  BBO(16,BODZ,1,1),       BBOATBI_MASK, PPCCOM,      { BDPA } },
{ "bdzla",   BBO(16,BODZ,1,1),       BBOATBI_MASK, COM,         { BDA } },
{ "blt-",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "blt+",    BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "blt",     BBOCB(16,BOT,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bltl-",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bltl+",   BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bltl",    BBOCB(16,BOT,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "blta-",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "blta+",   BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "blta",    BBOCB(16,BOT,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bltla-",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bltla+",  BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bltla",   BBOCB(16,BOT,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bgt-",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bgt+",    BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bgt",     BBOCB(16,BOT,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bgtl-",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bgtl+",   BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bgtl",    BBOCB(16,BOT,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bgta-",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bgta+",   BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bgta",    BBOCB(16,BOT,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bgtla-",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bgtla+",  BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bgtla",   BBOCB(16,BOT,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "beq-",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "beq+",    BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "beq",     BBOCB(16,BOT,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "beql-",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "beql+",   BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "beql",    BBOCB(16,BOT,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "beqa-",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "beqa+",   BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "beqa",    BBOCB(16,BOT,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "beqla-",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "beqla+",  BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "beqla",   BBOCB(16,BOT,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bso-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bso+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bso",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bsol-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bsol+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bsol",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bsoa-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bsoa+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bsoa",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bsola-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bsola+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bsola",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bun-",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bun+",    BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bun",     BBOCB(16,BOT,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
{ "bunl-",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bunl+",   BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bunl",    BBOCB(16,BOT,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
{ "buna-",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "buna+",   BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "buna",    BBOCB(16,BOT,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
{ "bunla-",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bunla+",  BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bunla",   BBOCB(16,BOT,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
{ "bge-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bge+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bge",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bgel-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bgel+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bgel",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bgea-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bgea+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bgea",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bgela-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bgela+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bgela",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bnl-",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bnl+",    BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bnl",     BBOCB(16,BOF,CBLT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnll-",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bnll+",   BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bnll",    BBOCB(16,BOF,CBLT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnla-",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnla+",   BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnla",    BBOCB(16,BOF,CBLT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bnlla-",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnlla+",  BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnlla",   BBOCB(16,BOF,CBLT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "ble-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "ble+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "ble",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "blel-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "blel+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "blel",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "blea-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "blea+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "blea",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "blela-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "blela+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "blela",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bng-",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bng+",    BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bng",     BBOCB(16,BOF,CBGT,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bngl-",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bngl+",   BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bngl",    BBOCB(16,BOF,CBGT,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnga-",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnga+",   BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnga",    BBOCB(16,BOF,CBGT,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bngla-",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bngla+",  BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bngla",   BBOCB(16,BOF,CBGT,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bne-",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bne+",    BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bne",     BBOCB(16,BOF,CBEQ,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnel-",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bnel+",   BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bnel",    BBOCB(16,BOF,CBEQ,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnea-",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnea+",   BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnea",    BBOCB(16,BOF,CBEQ,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bnela-",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnela+",  BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnela",   BBOCB(16,BOF,CBEQ,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bns-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bns+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bns",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnsl-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bnsl+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bnsl",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, COM,         { CR, BD } },
{ "bnsa-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnsa+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnsa",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bnsla-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnsla+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnsla",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, COM,         { CR, BDA } },
{ "bnu-",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bnu+",    BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bnu",     BBOCB(16,BOF,CBSO,0,0), BBOATCB_MASK, PPCCOM,      { CR, BD } },
{ "bnul-",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDM } },
{ "bnul+",   BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BDP } },
{ "bnul",    BBOCB(16,BOF,CBSO,0,1), BBOATCB_MASK, PPCCOM,      { CR, BD } },
{ "bnua-",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnua+",   BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnua",    BBOCB(16,BOF,CBSO,1,0), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
{ "bnula-",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDMA } },
{ "bnula+",  BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDPA } },
{ "bnula",   BBOCB(16,BOF,CBSO,1,1), BBOATCB_MASK, PPCCOM,      { CR, BDA } },
{ "bdnzt-",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
{ "bdnzt+",  BBO(16,BODNZT,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
{ "bdnzt",   BBO(16,BODNZT,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
{ "bdnztl-", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
{ "bdnztl+", BBO(16,BODNZT,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
{ "bdnztl",  BBO(16,BODNZT,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
{ "bdnzta-", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
{ "bdnzta+", BBO(16,BODNZT,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
{ "bdnzta",  BBO(16,BODNZT,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
{ "bdnztla-",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
{ "bdnztla+",BBO(16,BODNZT,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
{ "bdnztla", BBO(16,BODNZT,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
{ "bdnzf-",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDM } },
{ "bdnzf+",  BBO(16,BODNZF,0,0), BBOY_MASK, NOPOWER4,   { BI, BDP } },
{ "bdnzf",   BBO(16,BODNZF,0,0), BBOY_MASK, PPCCOM,     { BI, BD } },
{ "bdnzfl-", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDM } },
{ "bdnzfl+", BBO(16,BODNZF,0,1), BBOY_MASK, NOPOWER4,   { BI, BDP } },
{ "bdnzfl",  BBO(16,BODNZF,0,1), BBOY_MASK, PPCCOM,     { BI, BD } },
{ "bdnzfa-", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
{ "bdnzfa+", BBO(16,BODNZF,1,0), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
{ "bdnzfa",  BBO(16,BODNZF,1,0), BBOY_MASK, PPCCOM,     { BI, BDA } },
{ "bdnzfla-",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDMA } },
{ "bdnzfla+",BBO(16,BODNZF,1,1), BBOY_MASK, NOPOWER4,   { BI, BDPA } },
{ "bdnzfla", BBO(16,BODNZF,1,1), BBOY_MASK, PPCCOM,     { BI, BDA } },
{ "bt-",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
{ "bt+",     BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
{ "bt",      BBO(16,BOT,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
{ "bbt",     BBO(16,BOT,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
{ "btl-",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
{ "btl+",    BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
{ "btl",     BBO(16,BOT,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
{ "bbtl",    BBO(16,BOT,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
{ "bta-",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
{ "bta+",    BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
{ "bta",     BBO(16,BOT,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
{ "bbta",    BBO(16,BOT,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
{ "btla-",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
{ "btla+",   BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
{ "btla",    BBO(16,BOT,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
{ "bbtla",   BBO(16,BOT,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
{ "bf-",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDM } },
{ "bf+",     BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BDP } },
{ "bf",      BBO(16,BOF,0,0), BBOAT_MASK, PPCCOM,       { BI, BD } },
{ "bbf",     BBO(16,BOF,0,0), BBOAT_MASK, PWRCOM,       { BI, BD } },
{ "bfl-",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDM } },
{ "bfl+",    BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BDP } },
{ "bfl",     BBO(16,BOF,0,1), BBOAT_MASK, PPCCOM,       { BI, BD } },
{ "bbfl",    BBO(16,BOF,0,1), BBOAT_MASK, PWRCOM,       { BI, BD } },
{ "bfa-",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
{ "bfa+",    BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
{ "bfa",     BBO(16,BOF,1,0), BBOAT_MASK, PPCCOM,       { BI, BDA } },
{ "bbfa",    BBO(16,BOF,1,0), BBOAT_MASK, PWRCOM,       { BI, BDA } },
{ "bfla-",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDMA } },
{ "bfla+",   BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDPA } },
{ "bfla",    BBO(16,BOF,1,1), BBOAT_MASK, PPCCOM,       { BI, BDA } },
{ "bbfla",   BBO(16,BOF,1,1), BBOAT_MASK, PWRCOM,       { BI, BDA } },
{ "bdzt-",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
{ "bdzt+",   BBO(16,BODZT,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
{ "bdzt",    BBO(16,BODZT,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
{ "bdztl-",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
{ "bdztl+",  BBO(16,BODZT,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
{ "bdztl",   BBO(16,BODZT,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
{ "bdzta-",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
{ "bdzta+",  BBO(16,BODZT,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
{ "bdzta",   BBO(16,BODZT,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
{ "bdztla-", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
{ "bdztla+", BBO(16,BODZT,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
{ "bdztla",  BBO(16,BODZT,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
{ "bdzf-",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDM } },
{ "bdzf+",   BBO(16,BODZF,0,0), BBOY_MASK, NOPOWER4,    { BI, BDP } },
{ "bdzf",    BBO(16,BODZF,0,0), BBOY_MASK, PPCCOM,      { BI, BD } },
{ "bdzfl-",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDM } },
{ "bdzfl+",  BBO(16,BODZF,0,1), BBOY_MASK, NOPOWER4,    { BI, BDP } },
{ "bdzfl",   BBO(16,BODZF,0,1), BBOY_MASK, PPCCOM,      { BI, BD } },
{ "bdzfa-",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
{ "bdzfa+",  BBO(16,BODZF,1,0), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
{ "bdzfa",   BBO(16,BODZF,1,0), BBOY_MASK, PPCCOM,      { BI, BDA } },
{ "bdzfla-", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDMA } },
{ "bdzfla+", BBO(16,BODZF,1,1), BBOY_MASK, NOPOWER4,    { BI, BDPA } },
{ "bdzfla",  BBO(16,BODZF,1,1), BBOY_MASK, PPCCOM,      { BI, BDA } },
{ "bc-",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
{ "bc+",     B(16,0,0), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
{ "bc",      B(16,0,0), B_MASK,         COM,            { BO, BI, BD } },
{ "bcl-",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDM } },
{ "bcl+",    B(16,0,1), B_MASK,         PPCCOM,         { BOE, BI, BDP } },
{ "bcl",     B(16,0,1), B_MASK,         COM,            { BO, BI, BD } },
{ "bca-",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
{ "bca+",    B(16,1,0), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
{ "bca",     B(16,1,0), B_MASK,         COM,            { BO, BI, BDA } },
{ "bcla-",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDMA } },
{ "bcla+",   B(16,1,1), B_MASK,         PPCCOM,         { BOE, BI, BDPA } },
{ "bcla",    B(16,1,1), B_MASK,         COM,            { BO, BI, BDA } },

{ "sc",      SC(17,1,0), SC_MASK,       PPC,            { LEV } },
{ "svc",     SC(17,0,0), SC_MASK,       POWER,          { SVC_LEV, FL1, FL2 } },
{ "svcl",    SC(17,0,1), SC_MASK,       POWER,          { SVC_LEV, FL1, FL2 } },
{ "svca",    SC(17,1,0), SC_MASK,       PWRCOM,         { SV } },
{ "svcla",   SC(17,1,1), SC_MASK,       POWER,          { SV } },

{ "b",       B(18,0,0), B_MASK,         COM,            { LI } },
{ "bl",      B(18,0,1), B_MASK,         COM,            { LI } },
{ "ba",      B(18,1,0), B_MASK,         COM,            { LIA } },
{ "bla",     B(18,1,1), B_MASK,         COM,            { LIA } },

{ "mcrf",    XL(19,0),  XLBB_MASK|(3 << 21)|(3 << 16), COM,     { BF, BFA } },

{ "blr",     XLO(19,BOU,16,0), XLBOBIBB_MASK, PPCCOM,   { 0 } },
{ "br",      XLO(19,BOU,16,0), XLBOBIBB_MASK, PWRCOM,   { 0 } },
{ "blrl",    XLO(19,BOU,16,1), XLBOBIBB_MASK, PPCCOM,   { 0 } },
{ "brl",     XLO(19,BOU,16,1), XLBOBIBB_MASK, PWRCOM,   { 0 } },
{ "bdnzlr",  XLO(19,BODNZ,16,0), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdnzlr-", XLO(19,BODNZ,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
{ "bdnzlr-", XLO(19,BODNZM4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
{ "bdnzlr+", XLO(19,BODNZP,16,0), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
{ "bdnzlr+", XLO(19,BODNZP4,16,0), XLBOBIBB_MASK, POWER4,       { 0 } },
{ "bdnzlrl", XLO(19,BODNZ,16,1), XLBOBIBB_MASK, PPCCOM, { 0 } },
{ "bdnzlrl-",XLO(19,BODNZ,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
{ "bdnzlrl-",XLO(19,BODNZM4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
{ "bdnzlrl+",XLO(19,BODNZP,16,1), XLBOBIBB_MASK, NOPOWER4,      { 0 } },
{ "bdnzlrl+",XLO(19,BODNZP4,16,1), XLBOBIBB_MASK, POWER4,       { 0 } },
{ "bdzlr",   XLO(19,BODZ,16,0), XLBOBIBB_MASK, PPCCOM,  { 0 } },
{ "bdzlr-",  XLO(19,BODZ,16,0), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
{ "bdzlr-",  XLO(19,BODZM4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
{ "bdzlr+",  XLO(19,BODZP,16,0), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
{ "bdzlr+",  XLO(19,BODZP4,16,0), XLBOBIBB_MASK, POWER4,        { 0 } },
{ "bdzlrl",  XLO(19,BODZ,16,1), XLBOBIBB_MASK, PPCCOM,  { 0 } },
{ "bdzlrl-", XLO(19,BODZ,16,1), XLBOBIBB_MASK, NOPOWER4,        { 0 } },
{ "bdzlrl-", XLO(19,BODZM4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
{ "bdzlrl+", XLO(19,BODZP,16,1), XLBOBIBB_MASK, NOPOWER4,       { 0 } },
{ "bdzlrl+", XLO(19,BODZP4,16,1), XLBOBIBB_MASK, POWER4,        { 0 } },
{ "bltlr",   XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bltlr-",  XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlr-",  XLOCB(19,BOTM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltlr+",  XLOCB(19,BOTP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlr+",  XLOCB(19,BOTP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltr",    XLOCB(19,BOT,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bltlrl",  XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bltlrl-", XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlrl-", XLOCB(19,BOTM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltlrl+", XLOCB(19,BOTP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bltlrl+", XLOCB(19,BOTP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bltrl",   XLOCB(19,BOT,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bgtlr",   XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgtlr-",  XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlr-",  XLOCB(19,BOTM4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtlr+",  XLOCB(19,BOTP,CBGT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlr+",  XLOCB(19,BOTP4,CBGT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtr",    XLOCB(19,BOT,CBGT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bgtlrl",  XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgtlrl-", XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlrl-", XLOCB(19,BOTM4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtlrl+", XLOCB(19,BOTP,CBGT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgtlrl+", XLOCB(19,BOTP4,CBGT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgtrl",   XLOCB(19,BOT,CBGT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "beqlr",   XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "beqlr-",  XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlr-",  XLOCB(19,BOTM4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqlr+",  XLOCB(19,BOTP,CBEQ,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlr+",  XLOCB(19,BOTP4,CBEQ,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqr",    XLOCB(19,BOT,CBEQ,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "beqlrl",  XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "beqlrl-", XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlrl-", XLOCB(19,BOTM4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqlrl+", XLOCB(19,BOTP,CBEQ,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "beqlrl+", XLOCB(19,BOTP4,CBEQ,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "beqrl",   XLOCB(19,BOT,CBEQ,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bsolr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bsolr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsolr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsor",    XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bsolrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bsolrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsolrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bsolrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bsorl",   XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bunlr",   XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bunlr-",  XLOCB(19,BOT,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlr-",  XLOCB(19,BOTM4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bunlr+",  XLOCB(19,BOTP,CBSO,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlr+",  XLOCB(19,BOTP4,CBSO,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bunlrl",  XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bunlrl-", XLOCB(19,BOT,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlrl-", XLOCB(19,BOTM4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bunlrl+", XLOCB(19,BOTP,CBSO,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bunlrl+", XLOCB(19,BOTP4,CBSO,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgelr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgelr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgelr+",  XLOCB(19,BOFP,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelr+",  XLOCB(19,BOFP4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },
{ "bger",    XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bgelrl",  XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bgelrl-", XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelrl-", XLOCB(19,BOFM4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgelrl+", XLOCB(19,BOFP,CBLT,16,1), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bgelrl+", XLOCB(19,BOFP4,CBLT,16,1), XLBOCBBB_MASK, POWER4, { CR } },
{ "bgerl",   XLOCB(19,BOF,CBLT,16,1), XLBOCBBB_MASK, PWRCOM, { CR } },
{ "bnllr",   XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, PPCCOM, { CR } },
{ "bnllr-",  XLOCB(19,BOF,CBLT,16,0), XLBOCBBB_MASK, NOPOWER4, { CR } },
{ "bnllr-",  XLOCB(19,BOFM4,CBLT,16,0), XLBOCBBB_MASK, POWER4, { CR } },