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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/ppc/mac.h"
28#include "hw/ppc/mac_dbdma.h"
29#include "sysemu/block-backend.h"
30#include "sysemu/dma.h"
31
32#include <hw/ide/internal.h>
33
34
35
36
37#ifdef DEBUG_MACIO
38static const int debug_macio = 1;
39#else
40static const int debug_macio = 0;
41#endif
42
43#define MACIO_DPRINTF(fmt, ...) do { \
44 if (debug_macio) { \
45 printf(fmt , ## __VA_ARGS__); \
46 } \
47 } while (0)
48
49
50
51
52
53#define MACIO_PAGE_SIZE 4096
54
55
56
57
58
59
60
61
62static void pmac_dma_read(BlockBackend *blk,
63 int64_t offset, unsigned int bytes,
64 void (*cb)(void *opaque, int ret), void *opaque)
65{
66 DBDMA_io *io = opaque;
67 MACIOIDEState *m = io->opaque;
68 IDEState *s = idebus_active_if(&m->bus);
69 dma_addr_t dma_addr, dma_len;
70 void *mem;
71 int64_t sector_num;
72 int nsector;
73 uint64_t align = BDRV_SECTOR_SIZE;
74 size_t head_bytes, tail_bytes;
75
76 qemu_iovec_destroy(&io->iov);
77 qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
78
79 sector_num = (offset >> 9);
80 nsector = (io->len >> 9);
81
82 MACIO_DPRINTF("--- DMA read transfer (0x%" HWADDR_PRIx ",0x%x): "
83 "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
84 sector_num, nsector);
85
86 dma_addr = io->addr;
87 dma_len = io->len;
88 mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
89 DMA_DIRECTION_FROM_DEVICE);
90
91 if (offset & (align - 1)) {
92 head_bytes = offset & (align - 1);
93
94 MACIO_DPRINTF("--- DMA unaligned head: sector %" PRId64 ", "
95 "discarding %zu bytes\n", sector_num, head_bytes);
96
97 qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
98
99 bytes += offset & (align - 1);
100 offset = offset & ~(align - 1);
101 }
102
103 qemu_iovec_add(&io->iov, mem, io->len);
104
105 if ((offset + bytes) & (align - 1)) {
106 tail_bytes = (offset + bytes) & (align - 1);
107
108 MACIO_DPRINTF("--- DMA unaligned tail: sector %" PRId64 ", "
109 "discarding bytes %zu\n", sector_num, tail_bytes);
110
111 qemu_iovec_add(&io->iov, &io->tail_remainder, align - tail_bytes);
112 bytes = ROUND_UP(bytes, align);
113 }
114
115 s->io_buffer_size -= io->len;
116 s->io_buffer_index += io->len;
117
118 io->len = 0;
119
120 MACIO_DPRINTF("--- Block read transfer - sector_num: %" PRIx64 " "
121 "nsector: %x\n", (offset >> 9), (bytes >> 9));
122
123 s->bus->dma->aiocb = blk_aio_readv(blk, (offset >> 9), &io->iov,
124 (bytes >> 9), cb, io);
125}
126
127static void pmac_dma_write(BlockBackend *blk,
128 int64_t offset, int bytes,
129 void (*cb)(void *opaque, int ret), void *opaque)
130{
131 DBDMA_io *io = opaque;
132 MACIOIDEState *m = io->opaque;
133 IDEState *s = idebus_active_if(&m->bus);
134 dma_addr_t dma_addr, dma_len;
135 void *mem;
136 int64_t sector_num;
137 int nsector;
138 uint64_t align = BDRV_SECTOR_SIZE;
139 size_t head_bytes, tail_bytes;
140 bool unaligned_head = false, unaligned_tail = false;
141
142 qemu_iovec_destroy(&io->iov);
143 qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
144
145 sector_num = (offset >> 9);
146 nsector = (io->len >> 9);
147
148 MACIO_DPRINTF("--- DMA write transfer (0x%" HWADDR_PRIx ",0x%x): "
149 "sector_num: %" PRId64 ", nsector: %d\n", io->addr, io->len,
150 sector_num, nsector);
151
152 dma_addr = io->addr;
153 dma_len = io->len;
154 mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
155 DMA_DIRECTION_TO_DEVICE);
156
157 if (offset & (align - 1)) {
158 head_bytes = offset & (align - 1);
159 sector_num = ((offset & ~(align - 1)) >> 9);
160
161 MACIO_DPRINTF("--- DMA unaligned head: pre-reading head sector %"
162 PRId64 "\n", sector_num);
163
164 blk_pread(s->blk, (sector_num << 9), &io->head_remainder, align);
165
166 qemu_iovec_add(&io->iov, &io->head_remainder, head_bytes);
167 qemu_iovec_add(&io->iov, mem, io->len);
168
169 bytes += offset & (align - 1);
170 offset = offset & ~(align - 1);
171
172 unaligned_head = true;
173 }
174
175 if ((offset + bytes) & (align - 1)) {
176 tail_bytes = (offset + bytes) & (align - 1);
177 sector_num = (((offset + bytes) & ~(align - 1)) >> 9);
178
179 MACIO_DPRINTF("--- DMA unaligned tail: pre-reading tail sector %"
180 PRId64 "\n", sector_num);
181
182 blk_pread(s->blk, (sector_num << 9), &io->tail_remainder, align);
183
184 if (!unaligned_head) {
185 qemu_iovec_add(&io->iov, mem, io->len);
186 }
187
188 qemu_iovec_add(&io->iov, &io->tail_remainder + tail_bytes,
189 align - tail_bytes);
190
191 bytes = ROUND_UP(bytes, align);
192
193 unaligned_tail = true;
194 }
195
196 if (!unaligned_head && !unaligned_tail) {
197 qemu_iovec_add(&io->iov, mem, io->len);
198 }
199
200 s->io_buffer_size -= io->len;
201 s->io_buffer_index += io->len;
202
203 io->len = 0;
204
205 MACIO_DPRINTF("--- Block write transfer - sector_num: %" PRIx64 " "
206 "nsector: %x\n", (offset >> 9), (bytes >> 9));
207
208 s->bus->dma->aiocb = blk_aio_writev(blk, (offset >> 9), &io->iov,
209 (bytes >> 9), cb, io);
210}
211
212static void pmac_dma_trim(BlockBackend *blk,
213 int64_t offset, int bytes,
214 void (*cb)(void *opaque, int ret), void *opaque)
215{
216 DBDMA_io *io = opaque;
217 MACIOIDEState *m = io->opaque;
218 IDEState *s = idebus_active_if(&m->bus);
219 dma_addr_t dma_addr, dma_len;
220 void *mem;
221
222 qemu_iovec_destroy(&io->iov);
223 qemu_iovec_init(&io->iov, io->len / MACIO_PAGE_SIZE + 1);
224
225 dma_addr = io->addr;
226 dma_len = io->len;
227 mem = dma_memory_map(&address_space_memory, dma_addr, &dma_len,
228 DMA_DIRECTION_TO_DEVICE);
229
230 qemu_iovec_add(&io->iov, mem, io->len);
231 s->io_buffer_size -= io->len;
232 s->io_buffer_index += io->len;
233 io->len = 0;
234
235 s->bus->dma->aiocb = ide_issue_trim(blk, (offset >> 9), &io->iov,
236 (bytes >> 9), cb, io);
237}
238
239static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
240{
241 DBDMA_io *io = opaque;
242 MACIOIDEState *m = io->opaque;
243 IDEState *s = idebus_active_if(&m->bus);
244 int64_t offset;
245
246 MACIO_DPRINTF("pmac_ide_atapi_transfer_cb\n");
247
248 if (ret < 0) {
249 MACIO_DPRINTF("DMA error: %d\n", ret);
250 ide_atapi_io_error(s, ret);
251 goto done;
252 }
253
254 if (!m->dma_active) {
255 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
256 s->nsector, io->len, s->status);
257
258 io->processing = false;
259 return;
260 }
261
262 if (s->io_buffer_size <= 0) {
263 MACIO_DPRINTF("End of IDE transfer\n");
264 ide_atapi_cmd_ok(s);
265 m->dma_active = false;
266 goto done;
267 }
268
269 if (io->len == 0) {
270 MACIO_DPRINTF("End of DMA transfer\n");
271 goto done;
272 }
273
274 if (s->lba == -1) {
275
276 s->io_buffer_size = MIN(s->io_buffer_size, io->len);
277 cpu_physical_memory_write(io->addr, s->io_buffer, s->io_buffer_size);
278 ide_atapi_cmd_ok(s);
279 m->dma_active = false;
280 goto done;
281 }
282
283
284 offset = ((int64_t)s->lba << 11) + s->io_buffer_index;
285
286 pmac_dma_read(s->blk, offset, io->len, pmac_ide_atapi_transfer_cb, io);
287 return;
288
289done:
290 if (ret < 0) {
291 block_acct_failed(blk_get_stats(s->blk), &s->acct);
292 } else {
293 block_acct_done(blk_get_stats(s->blk), &s->acct);
294 }
295
296 ide_set_inactive(s, false);
297 io->dma_end(opaque);
298}
299
300static void pmac_ide_transfer_cb(void *opaque, int ret)
301{
302 DBDMA_io *io = opaque;
303 MACIOIDEState *m = io->opaque;
304 IDEState *s = idebus_active_if(&m->bus);
305 int64_t offset;
306
307 MACIO_DPRINTF("pmac_ide_transfer_cb\n");
308
309 if (ret < 0) {
310 MACIO_DPRINTF("DMA error: %d\n", ret);
311 ide_dma_error(s);
312 goto done;
313 }
314
315 if (!m->dma_active) {
316 MACIO_DPRINTF("waiting for data (%#x - %#x - %x)\n",
317 s->nsector, io->len, s->status);
318
319 io->processing = false;
320 return;
321 }
322
323 if (s->io_buffer_size <= 0) {
324 MACIO_DPRINTF("End of IDE transfer\n");
325 s->status = READY_STAT | SEEK_STAT;
326 ide_set_irq(s->bus);
327 m->dma_active = false;
328 goto done;
329 }
330
331 if (io->len == 0) {
332 MACIO_DPRINTF("End of DMA transfer\n");
333 goto done;
334 }
335
336
337 offset = (ide_get_sector(s) << 9) + s->io_buffer_index;
338
339 switch (s->dma_cmd) {
340 case IDE_DMA_READ:
341 pmac_dma_read(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
342 break;
343 case IDE_DMA_WRITE:
344 pmac_dma_write(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
345 break;
346 case IDE_DMA_TRIM:
347 pmac_dma_trim(s->blk, offset, io->len, pmac_ide_transfer_cb, io);
348 break;
349 default:
350 abort();
351 }
352
353 return;
354
355done:
356 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
357 if (ret < 0) {
358 block_acct_failed(blk_get_stats(s->blk), &s->acct);
359 } else {
360 block_acct_done(blk_get_stats(s->blk), &s->acct);
361 }
362 }
363
364 ide_set_inactive(s, false);
365 io->dma_end(opaque);
366}
367
368static void pmac_ide_transfer(DBDMA_io *io)
369{
370 MACIOIDEState *m = io->opaque;
371 IDEState *s = idebus_active_if(&m->bus);
372
373 MACIO_DPRINTF("\n");
374
375 if (s->drive_kind == IDE_CD) {
376 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
377 BLOCK_ACCT_READ);
378
379 pmac_ide_atapi_transfer_cb(io, 0);
380 return;
381 }
382
383 switch (s->dma_cmd) {
384 case IDE_DMA_READ:
385 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
386 BLOCK_ACCT_READ);
387 break;
388 case IDE_DMA_WRITE:
389 block_acct_start(blk_get_stats(s->blk), &s->acct, io->len,
390 BLOCK_ACCT_WRITE);
391 break;
392 default:
393 break;
394 }
395
396 pmac_ide_transfer_cb(io, 0);
397}
398
399static void pmac_ide_flush(DBDMA_io *io)
400{
401 MACIOIDEState *m = io->opaque;
402 IDEState *s = idebus_active_if(&m->bus);
403
404 if (s->bus->dma->aiocb) {
405 blk_drain_all();
406 }
407}
408
409
410static void pmac_ide_writeb (void *opaque,
411 hwaddr addr, uint32_t val)
412{
413 MACIOIDEState *d = opaque;
414
415 addr = (addr & 0xFFF) >> 4;
416 switch (addr) {
417 case 1 ... 7:
418 ide_ioport_write(&d->bus, addr, val);
419 break;
420 case 8:
421 case 22:
422 ide_cmd_write(&d->bus, 0, val);
423 break;
424 default:
425 break;
426 }
427}
428
429static uint32_t pmac_ide_readb (void *opaque,hwaddr addr)
430{
431 uint8_t retval;
432 MACIOIDEState *d = opaque;
433
434 addr = (addr & 0xFFF) >> 4;
435 switch (addr) {
436 case 1 ... 7:
437 retval = ide_ioport_read(&d->bus, addr);
438 break;
439 case 8:
440 case 22:
441 retval = ide_status_read(&d->bus, 0);
442 break;
443 default:
444 retval = 0xFF;
445 break;
446 }
447 return retval;
448}
449
450static void pmac_ide_writew (void *opaque,
451 hwaddr addr, uint32_t val)
452{
453 MACIOIDEState *d = opaque;
454
455 addr = (addr & 0xFFF) >> 4;
456 val = bswap16(val);
457 if (addr == 0) {
458 ide_data_writew(&d->bus, 0, val);
459 }
460}
461
462static uint32_t pmac_ide_readw (void *opaque,hwaddr addr)
463{
464 uint16_t retval;
465 MACIOIDEState *d = opaque;
466
467 addr = (addr & 0xFFF) >> 4;
468 if (addr == 0) {
469 retval = ide_data_readw(&d->bus, 0);
470 } else {
471 retval = 0xFFFF;
472 }
473 retval = bswap16(retval);
474 return retval;
475}
476
477static void pmac_ide_writel (void *opaque,
478 hwaddr addr, uint32_t val)
479{
480 MACIOIDEState *d = opaque;
481
482 addr = (addr & 0xFFF) >> 4;
483 val = bswap32(val);
484 if (addr == 0) {
485 ide_data_writel(&d->bus, 0, val);
486 }
487}
488
489static uint32_t pmac_ide_readl (void *opaque,hwaddr addr)
490{
491 uint32_t retval;
492 MACIOIDEState *d = opaque;
493
494 addr = (addr & 0xFFF) >> 4;
495 if (addr == 0) {
496 retval = ide_data_readl(&d->bus, 0);
497 } else {
498 retval = 0xFFFFFFFF;
499 }
500 retval = bswap32(retval);
501 return retval;
502}
503
504static const MemoryRegionOps pmac_ide_ops = {
505 .old_mmio = {
506 .write = {
507 pmac_ide_writeb,
508 pmac_ide_writew,
509 pmac_ide_writel,
510 },
511 .read = {
512 pmac_ide_readb,
513 pmac_ide_readw,
514 pmac_ide_readl,
515 },
516 },
517 .endianness = DEVICE_NATIVE_ENDIAN,
518};
519
520static const VMStateDescription vmstate_pmac = {
521 .name = "ide",
522 .version_id = 4,
523 .minimum_version_id = 0,
524 .fields = (VMStateField[]) {
525 VMSTATE_IDE_BUS(bus, MACIOIDEState),
526 VMSTATE_IDE_DRIVES(bus.ifs, MACIOIDEState),
527 VMSTATE_BOOL(dma_active, MACIOIDEState),
528 VMSTATE_END_OF_LIST()
529 }
530};
531
532static void macio_ide_reset(DeviceState *dev)
533{
534 MACIOIDEState *d = MACIO_IDE(dev);
535
536 ide_bus_reset(&d->bus);
537}
538
539static int ide_nop_int(IDEDMA *dma, int x)
540{
541 return 0;
542}
543
544static int32_t ide_nop_int32(IDEDMA *dma, int32_t l)
545{
546 return 0;
547}
548
549static void ide_dbdma_start(IDEDMA *dma, IDEState *s,
550 BlockCompletionFunc *cb)
551{
552 MACIOIDEState *m = container_of(dma, MACIOIDEState, dma);
553
554 s->io_buffer_index = 0;
555 if (s->drive_kind == IDE_CD) {
556 s->io_buffer_size = s->packet_transfer_size;
557 } else {
558 s->io_buffer_size = s->nsector * BDRV_SECTOR_SIZE;
559 }
560
561 MACIO_DPRINTF("\n\n------------ IDE transfer\n");
562 MACIO_DPRINTF("buffer_size: %x buffer_index: %x\n",
563 s->io_buffer_size, s->io_buffer_index);
564 MACIO_DPRINTF("lba: %x size: %x\n", s->lba, s->io_buffer_size);
565 MACIO_DPRINTF("-------------------------\n");
566
567 m->dma_active = true;
568 DBDMA_kick(m->dbdma);
569}
570
571static const IDEDMAOps dbdma_ops = {
572 .start_dma = ide_dbdma_start,
573 .prepare_buf = ide_nop_int32,
574 .rw_buf = ide_nop_int,
575};
576
577static void macio_ide_realizefn(DeviceState *dev, Error **errp)
578{
579 MACIOIDEState *s = MACIO_IDE(dev);
580
581 ide_init2(&s->bus, s->irq);
582
583
584 s->dma.ops = &dbdma_ops;
585 s->bus.dma = &s->dma;
586}
587
588static void macio_ide_initfn(Object *obj)
589{
590 SysBusDevice *d = SYS_BUS_DEVICE(obj);
591 MACIOIDEState *s = MACIO_IDE(obj);
592
593 ide_bus_new(&s->bus, sizeof(s->bus), DEVICE(obj), 0, 2);
594 memory_region_init_io(&s->mem, obj, &pmac_ide_ops, s, "pmac-ide", 0x1000);
595 sysbus_init_mmio(d, &s->mem);
596 sysbus_init_irq(d, &s->irq);
597 sysbus_init_irq(d, &s->dma_irq);
598}
599
600static void macio_ide_class_init(ObjectClass *oc, void *data)
601{
602 DeviceClass *dc = DEVICE_CLASS(oc);
603
604 dc->realize = macio_ide_realizefn;
605 dc->reset = macio_ide_reset;
606 dc->vmsd = &vmstate_pmac;
607 set_bit(DEVICE_CATEGORY_STORAGE, dc->categories);
608}
609
610static const TypeInfo macio_ide_type_info = {
611 .name = TYPE_MACIO_IDE,
612 .parent = TYPE_SYS_BUS_DEVICE,
613 .instance_size = sizeof(MACIOIDEState),
614 .instance_init = macio_ide_initfn,
615 .class_init = macio_ide_class_init,
616};
617
618static void macio_ide_register_types(void)
619{
620 type_register_static(&macio_ide_type_info);
621}
622
623
624void macio_ide_init_drives(MACIOIDEState *s, DriveInfo **hd_table)
625{
626 int i;
627
628 for (i = 0; i < 2; i++) {
629 if (hd_table[i]) {
630 ide_create_drive(&s->bus, i, hd_table[i]);
631 }
632 }
633}
634
635void macio_ide_register_dma(MACIOIDEState *s, void *dbdma, int channel)
636{
637 s->dbdma = dbdma;
638 DBDMA_register_channel(dbdma, channel, s->dma_irq,
639 pmac_ide_transfer, pmac_ide_flush, s);
640}
641
642type_init(macio_ide_register_types)
643
