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25#include "qemu/osdep.h"
26#include "hw/sysbus.h"
27#include "qapi/error.h"
28#include "qemu/log.h"
29#include "net/net.h"
30#include "net/checksum.h"
31
32#include "hw/stream.h"
33
34#define DPHY(x)
35
36#define TYPE_XILINX_AXI_ENET "xlnx.axi-ethernet"
37#define TYPE_XILINX_AXI_ENET_DATA_STREAM "xilinx-axienet-data-stream"
38#define TYPE_XILINX_AXI_ENET_CONTROL_STREAM "xilinx-axienet-control-stream"
39
40#define XILINX_AXI_ENET(obj) \
41 OBJECT_CHECK(XilinxAXIEnet, (obj), TYPE_XILINX_AXI_ENET)
42
43#define XILINX_AXI_ENET_DATA_STREAM(obj) \
44 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
45 TYPE_XILINX_AXI_ENET_DATA_STREAM)
46
47#define XILINX_AXI_ENET_CONTROL_STREAM(obj) \
48 OBJECT_CHECK(XilinxAXIEnetStreamSlave, (obj),\
49 TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
50
51
52#define ADVERTISE_10HALF 0x0020
53#define ADVERTISE_10FULL 0x0040
54#define ADVERTISE_100HALF 0x0080
55#define ADVERTISE_100FULL 0x0100
56
57#define CONTROL_PAYLOAD_WORDS 5
58#define CONTROL_PAYLOAD_SIZE (CONTROL_PAYLOAD_WORDS * (sizeof(uint32_t)))
59
60struct PHY {
61 uint32_t regs[32];
62
63 int link;
64
65 unsigned int (*read)(struct PHY *phy, unsigned int req);
66 void (*write)(struct PHY *phy, unsigned int req,
67 unsigned int data);
68};
69
70static unsigned int tdk_read(struct PHY *phy, unsigned int req)
71{
72 int regnum;
73 unsigned r = 0;
74
75 regnum = req & 0x1f;
76
77 switch (regnum) {
78 case 1:
79 if (!phy->link) {
80 break;
81 }
82
83
84 r |= (1 << 13) | (1 << 14);
85 r |= (1 << 11) | (1 << 12);
86 r |= (1 << 5);
87 r |= (1 << 3);
88 r |= (1 << 2);
89 r |= (1 << 1);
90 break;
91 case 5:
92
93
94
95 r = 1 << 14;
96
97 r |= phy->regs[4] & (15 << 5);
98
99 r |= 1;
100 break;
101 case 17:
102
103 r = 0x8c00;
104 break;
105 case 18:
106 {
107
108 int duplex = 0;
109 int speed_100 = 0;
110
111 if (!phy->link) {
112 break;
113 }
114
115
116 speed_100 = !!(phy->regs[4] & ADVERTISE_100HALF);
117 speed_100 |= !!(phy->regs[4] & ADVERTISE_100FULL);
118
119
120 duplex = !!(phy->regs[4] & ADVERTISE_100FULL);
121 duplex |= !!(phy->regs[4] & ADVERTISE_10FULL);
122 r = (speed_100 << 10) | (duplex << 11);
123 }
124 break;
125
126 default:
127 r = phy->regs[regnum];
128 break;
129 }
130 DPHY(qemu_log("\n%s %x = reg[%d]\n", __func__, r, regnum));
131 return r;
132}
133
134static void
135tdk_write(struct PHY *phy, unsigned int req, unsigned int data)
136{
137 int regnum;
138
139 regnum = req & 0x1f;
140 DPHY(qemu_log("%s reg[%d] = %x\n", __func__, regnum, data));
141 switch (regnum) {
142 default:
143 phy->regs[regnum] = data;
144 break;
145 }
146
147
148 phy->regs[0] &= ~0x8000;
149}
150
151static void
152tdk_init(struct PHY *phy)
153{
154 phy->regs[0] = 0x3100;
155
156 phy->regs[2] = 0x0141;
157 phy->regs[3] = 0x0cc2;
158
159 phy->regs[4] = 0x01E1;
160 phy->link = 1;
161
162 phy->read = tdk_read;
163 phy->write = tdk_write;
164}
165
166struct MDIOBus {
167
168 int mdc;
169 int mdio;
170
171
172 enum {
173 PREAMBLE,
174 SOF,
175 OPC,
176 ADDR,
177 REQ,
178 TURNAROUND,
179 DATA
180 } state;
181 unsigned int drive;
182
183 unsigned int cnt;
184 unsigned int addr;
185 unsigned int opc;
186 unsigned int req;
187 unsigned int data;
188
189 struct PHY *devs[32];
190};
191
192static void
193mdio_attach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
194{
195 bus->devs[addr & 0x1f] = phy;
196}
197
198#ifdef USE_THIS_DEAD_CODE
199static void
200mdio_detach(struct MDIOBus *bus, struct PHY *phy, unsigned int addr)
201{
202 bus->devs[addr & 0x1f] = NULL;
203}
204#endif
205
206static uint16_t mdio_read_req(struct MDIOBus *bus, unsigned int addr,
207 unsigned int reg)
208{
209 struct PHY *phy;
210 uint16_t data;
211
212 phy = bus->devs[addr];
213 if (phy && phy->read) {
214 data = phy->read(phy, reg);
215 } else {
216 data = 0xffff;
217 }
218 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
219 return data;
220}
221
222static void mdio_write_req(struct MDIOBus *bus, unsigned int addr,
223 unsigned int reg, uint16_t data)
224{
225 struct PHY *phy;
226
227 DPHY(qemu_log("%s addr=%d reg=%d data=%x\n", __func__, addr, reg, data));
228 phy = bus->devs[addr];
229 if (phy && phy->write) {
230 phy->write(phy, reg, data);
231 }
232}
233
234#define DENET(x)
235
236#define R_RAF (0x000 / 4)
237enum {
238 RAF_MCAST_REJ = (1 << 1),
239 RAF_BCAST_REJ = (1 << 2),
240 RAF_EMCF_EN = (1 << 12),
241 RAF_NEWFUNC_EN = (1 << 11)
242};
243
244#define R_IS (0x00C / 4)
245enum {
246 IS_HARD_ACCESS_COMPLETE = 1,
247 IS_AUTONEG = (1 << 1),
248 IS_RX_COMPLETE = (1 << 2),
249 IS_RX_REJECT = (1 << 3),
250 IS_TX_COMPLETE = (1 << 5),
251 IS_RX_DCM_LOCK = (1 << 6),
252 IS_MGM_RDY = (1 << 7),
253 IS_PHY_RST_DONE = (1 << 8),
254};
255
256#define R_IP (0x010 / 4)
257#define R_IE (0x014 / 4)
258#define R_UAWL (0x020 / 4)
259#define R_UAWU (0x024 / 4)
260#define R_PPST (0x030 / 4)
261enum {
262 PPST_LINKSTATUS = (1 << 0),
263 PPST_PHY_LINKSTATUS = (1 << 7),
264};
265
266#define R_STATS_RX_BYTESL (0x200 / 4)
267#define R_STATS_RX_BYTESH (0x204 / 4)
268#define R_STATS_TX_BYTESL (0x208 / 4)
269#define R_STATS_TX_BYTESH (0x20C / 4)
270#define R_STATS_RXL (0x290 / 4)
271#define R_STATS_RXH (0x294 / 4)
272#define R_STATS_RX_BCASTL (0x2a0 / 4)
273#define R_STATS_RX_BCASTH (0x2a4 / 4)
274#define R_STATS_RX_MCASTL (0x2a8 / 4)
275#define R_STATS_RX_MCASTH (0x2ac / 4)
276
277#define R_RCW0 (0x400 / 4)
278#define R_RCW1 (0x404 / 4)
279enum {
280 RCW1_VLAN = (1 << 27),
281 RCW1_RX = (1 << 28),
282 RCW1_FCS = (1 << 29),
283 RCW1_JUM = (1 << 30),
284 RCW1_RST = (1 << 31),
285};
286
287#define R_TC (0x408 / 4)
288enum {
289 TC_VLAN = (1 << 27),
290 TC_TX = (1 << 28),
291 TC_FCS = (1 << 29),
292 TC_JUM = (1 << 30),
293 TC_RST = (1 << 31),
294};
295
296#define R_EMMC (0x410 / 4)
297enum {
298 EMMC_LINKSPEED_10MB = (0 << 30),
299 EMMC_LINKSPEED_100MB = (1 << 30),
300 EMMC_LINKSPEED_1000MB = (2 << 30),
301};
302
303#define R_PHYC (0x414 / 4)
304
305#define R_MC (0x500 / 4)
306#define MC_EN (1 << 6)
307
308#define R_MCR (0x504 / 4)
309#define R_MWD (0x508 / 4)
310#define R_MRD (0x50c / 4)
311#define R_MIS (0x600 / 4)
312#define R_MIP (0x620 / 4)
313#define R_MIE (0x640 / 4)
314#define R_MIC (0x640 / 4)
315
316#define R_UAW0 (0x700 / 4)
317#define R_UAW1 (0x704 / 4)
318#define R_FMI (0x708 / 4)
319#define R_AF0 (0x710 / 4)
320#define R_AF1 (0x714 / 4)
321#define R_MAX (0x34 / 4)
322
323
324struct TEMAC {
325 struct MDIOBus mdio_bus;
326 struct PHY phy;
327
328 void *parent;
329};
330
331typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave;
332typedef struct XilinxAXIEnet XilinxAXIEnet;
333
334struct XilinxAXIEnetStreamSlave {
335 Object parent;
336
337 struct XilinxAXIEnet *enet;
338} ;
339
340struct XilinxAXIEnet {
341 SysBusDevice busdev;
342 MemoryRegion iomem;
343 qemu_irq irq;
344 StreamSlave *tx_data_dev;
345 StreamSlave *tx_control_dev;
346 XilinxAXIEnetStreamSlave rx_data_dev;
347 XilinxAXIEnetStreamSlave rx_control_dev;
348 NICState *nic;
349 NICConf conf;
350
351
352 uint32_t c_rxmem;
353 uint32_t c_txmem;
354 uint32_t c_phyaddr;
355
356 struct TEMAC TEMAC;
357
358
359 union {
360 uint32_t regs[4];
361 struct {
362 uint32_t mc;
363 uint32_t mcr;
364 uint32_t mwd;
365 uint32_t mrd;
366 };
367 } mii;
368
369 struct {
370 uint64_t rx_bytes;
371 uint64_t tx_bytes;
372
373 uint64_t rx;
374 uint64_t rx_bcast;
375 uint64_t rx_mcast;
376 } stats;
377
378
379 uint32_t rcw[2];
380
381 uint32_t tc;
382 uint32_t emmc;
383 uint32_t phyc;
384
385
386 uint32_t uaw[2];
387
388 uint32_t ext_uaw[2];
389 uint32_t fmi;
390
391 uint32_t regs[R_MAX];
392
393
394 uint32_t maddr[4][2];
395
396 uint32_t ext_mtable[1024];
397
398 uint32_t hdr[CONTROL_PAYLOAD_WORDS];
399
400 uint8_t *rxmem;
401 uint32_t rxsize;
402 uint32_t rxpos;
403
404 uint8_t rxapp[CONTROL_PAYLOAD_SIZE];
405 uint32_t rxappsize;
406
407
408 bool need_flush;
409};
410
411static void axienet_rx_reset(XilinxAXIEnet *s)
412{
413 s->rcw[1] = RCW1_JUM | RCW1_FCS | RCW1_RX | RCW1_VLAN;
414}
415
416static void axienet_tx_reset(XilinxAXIEnet *s)
417{
418 s->tc = TC_JUM | TC_TX | TC_VLAN;
419}
420
421static inline int axienet_rx_resetting(XilinxAXIEnet *s)
422{
423 return s->rcw[1] & RCW1_RST;
424}
425
426static inline int axienet_rx_enabled(XilinxAXIEnet *s)
427{
428 return s->rcw[1] & RCW1_RX;
429}
430
431static inline int axienet_extmcf_enabled(XilinxAXIEnet *s)
432{
433 return !!(s->regs[R_RAF] & RAF_EMCF_EN);
434}
435
436static inline int axienet_newfunc_enabled(XilinxAXIEnet *s)
437{
438 return !!(s->regs[R_RAF] & RAF_NEWFUNC_EN);
439}
440
441static void xilinx_axienet_reset(DeviceState *d)
442{
443 XilinxAXIEnet *s = XILINX_AXI_ENET(d);
444
445 axienet_rx_reset(s);
446 axienet_tx_reset(s);
447
448 s->regs[R_PPST] = PPST_LINKSTATUS | PPST_PHY_LINKSTATUS;
449 s->regs[R_IS] = IS_AUTONEG | IS_RX_DCM_LOCK | IS_MGM_RDY | IS_PHY_RST_DONE;
450
451 s->emmc = EMMC_LINKSPEED_100MB;
452}
453
454static void enet_update_irq(XilinxAXIEnet *s)
455{
456 s->regs[R_IP] = s->regs[R_IS] & s->regs[R_IE];
457 qemu_set_irq(s->irq, !!s->regs[R_IP]);
458}
459
460static uint64_t enet_read(void *opaque, hwaddr addr, unsigned size)
461{
462 XilinxAXIEnet *s = opaque;
463 uint32_t r = 0;
464 addr >>= 2;
465
466 switch (addr) {
467 case R_RCW0:
468 case R_RCW1:
469 r = s->rcw[addr & 1];
470 break;
471
472 case R_TC:
473 r = s->tc;
474 break;
475
476 case R_EMMC:
477 r = s->emmc;
478 break;
479
480 case R_PHYC:
481 r = s->phyc;
482 break;
483
484 case R_MCR:
485 r = s->mii.regs[addr & 3] | (1 << 7);
486 break;
487
488 case R_STATS_RX_BYTESL:
489 case R_STATS_RX_BYTESH:
490 r = s->stats.rx_bytes >> (32 * (addr & 1));
491 break;
492
493 case R_STATS_TX_BYTESL:
494 case R_STATS_TX_BYTESH:
495 r = s->stats.tx_bytes >> (32 * (addr & 1));
496 break;
497
498 case R_STATS_RXL:
499 case R_STATS_RXH:
500 r = s->stats.rx >> (32 * (addr & 1));
501 break;
502 case R_STATS_RX_BCASTL:
503 case R_STATS_RX_BCASTH:
504 r = s->stats.rx_bcast >> (32 * (addr & 1));
505 break;
506 case R_STATS_RX_MCASTL:
507 case R_STATS_RX_MCASTH:
508 r = s->stats.rx_mcast >> (32 * (addr & 1));
509 break;
510
511 case R_MC:
512 case R_MWD:
513 case R_MRD:
514 r = s->mii.regs[addr & 3];
515 break;
516
517 case R_UAW0:
518 case R_UAW1:
519 r = s->uaw[addr & 1];
520 break;
521
522 case R_UAWU:
523 case R_UAWL:
524 r = s->ext_uaw[addr & 1];
525 break;
526
527 case R_FMI:
528 r = s->fmi;
529 break;
530
531 case R_AF0:
532 case R_AF1:
533 r = s->maddr[s->fmi & 3][addr & 1];
534 break;
535
536 case 0x8000 ... 0x83ff:
537 r = s->ext_mtable[addr - 0x8000];
538 break;
539
540 default:
541 if (addr < ARRAY_SIZE(s->regs)) {
542 r = s->regs[addr];
543 }
544 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
545 __func__, addr * 4, r));
546 break;
547 }
548 return r;
549}
550
551static void enet_write(void *opaque, hwaddr addr,
552 uint64_t value, unsigned size)
553{
554 XilinxAXIEnet *s = opaque;
555 struct TEMAC *t = &s->TEMAC;
556
557 addr >>= 2;
558 switch (addr) {
559 case R_RCW0:
560 case R_RCW1:
561 s->rcw[addr & 1] = value;
562 if ((addr & 1) && value & RCW1_RST) {
563 axienet_rx_reset(s);
564 } else {
565 qemu_flush_queued_packets(qemu_get_queue(s->nic));
566 }
567 break;
568
569 case R_TC:
570 s->tc = value;
571 if (value & TC_RST) {
572 axienet_tx_reset(s);
573 }
574 break;
575
576 case R_EMMC:
577 s->emmc = value;
578 break;
579
580 case R_PHYC:
581 s->phyc = value;
582 break;
583
584 case R_MC:
585 value &= ((1 << 7) - 1);
586
587
588 if (value & MC_EN) {
589 unsigned int miiclkdiv = value & ((1 << 6) - 1);
590 if (!miiclkdiv) {
591 qemu_log("AXIENET: MDIO enabled but MDIOCLK is zero!\n");
592 }
593 }
594 s->mii.mc = value;
595 break;
596
597 case R_MCR: {
598 unsigned int phyaddr = (value >> 24) & 0x1f;
599 unsigned int regaddr = (value >> 16) & 0x1f;
600 unsigned int op = (value >> 14) & 3;
601 unsigned int initiate = (value >> 11) & 1;
602
603 if (initiate) {
604 if (op == 1) {
605 mdio_write_req(&t->mdio_bus, phyaddr, regaddr, s->mii.mwd);
606 } else if (op == 2) {
607 s->mii.mrd = mdio_read_req(&t->mdio_bus, phyaddr, regaddr);
608 } else {
609 qemu_log("AXIENET: invalid MDIOBus OP=%d\n", op);
610 }
611 }
612 s->mii.mcr = value;
613 break;
614 }
615
616 case R_MWD:
617 case R_MRD:
618 s->mii.regs[addr & 3] = value;
619 break;
620
621
622 case R_UAW0:
623 case R_UAW1:
624 s->uaw[addr & 1] = value;
625 break;
626
627 case R_UAWL:
628 case R_UAWU:
629 s->ext_uaw[addr & 1] = value;
630 break;
631
632 case R_FMI:
633 s->fmi = value;
634 break;
635
636 case R_AF0:
637 case R_AF1:
638 s->maddr[s->fmi & 3][addr & 1] = value;
639 break;
640
641 case R_IS:
642 s->regs[addr] &= ~value;
643 break;
644
645 case 0x8000 ... 0x83ff:
646 s->ext_mtable[addr - 0x8000] = value;
647 break;
648
649 default:
650 DENET(qemu_log("%s addr=" TARGET_FMT_plx " v=%x\n",
651 __func__, addr * 4, (unsigned)value));
652 if (addr < ARRAY_SIZE(s->regs)) {
653 s->regs[addr] = value;
654 }
655 break;
656 }
657 enet_update_irq(s);
658}
659
660static const MemoryRegionOps enet_ops = {
661 .read = enet_read,
662 .write = enet_write,
663 .endianness = DEVICE_LITTLE_ENDIAN,
664};
665
666static int eth_can_rx(XilinxAXIEnet *s)
667{
668
669 return !s->rxsize && !axienet_rx_resetting(s) && axienet_rx_enabled(s);
670}
671
672static int enet_match_addr(const uint8_t *buf, uint32_t f0, uint32_t f1)
673{
674 int match = 1;
675
676 if (memcmp(buf, &f0, 4)) {
677 match = 0;
678 }
679
680 if (buf[4] != (f1 & 0xff) || buf[5] != ((f1 >> 8) & 0xff)) {
681 match = 0;
682 }
683
684 return match;
685}
686
687static void axienet_eth_rx_notify(void *opaque)
688{
689 XilinxAXIEnet *s = XILINX_AXI_ENET(opaque);
690
691 while (s->rxappsize && stream_can_push(s->tx_control_dev,
692 axienet_eth_rx_notify, s)) {
693 size_t ret = stream_push(s->tx_control_dev,
694 (void *)s->rxapp + CONTROL_PAYLOAD_SIZE
695 - s->rxappsize, s->rxappsize,
696 STREAM_ATTR_EOP);
697 s->rxappsize -= ret;
698 }
699
700 while (s->rxsize && stream_can_push(s->tx_data_dev,
701 axienet_eth_rx_notify, s)) {
702 size_t ret = stream_push(s->tx_data_dev, (void *)s->rxmem + s->rxpos,
703 s->rxsize, STREAM_ATTR_EOP);
704 s->rxsize -= ret;
705 s->rxpos += ret;
706 if (!s->rxsize) {
707 s->regs[R_IS] |= IS_RX_COMPLETE;
708 if (s->need_flush) {
709 s->need_flush = false;
710 qemu_flush_queued_packets(qemu_get_queue(s->nic));
711 }
712 }
713 }
714 enet_update_irq(s);
715}
716
717static ssize_t eth_rx(NetClientState *nc, const uint8_t *buf, size_t size)
718{
719 XilinxAXIEnet *s = qemu_get_nic_opaque(nc);
720 static const unsigned char sa_bcast[6] = {0xff, 0xff, 0xff,
721 0xff, 0xff, 0xff};
722 static const unsigned char sa_ipmcast[3] = {0x01, 0x00, 0x52};
723 uint32_t app[CONTROL_PAYLOAD_WORDS] = {0};
724 int promisc = s->fmi & (1 << 31);
725 int unicast, broadcast, multicast, ip_multicast = 0;
726 uint32_t csum32;
727 uint16_t csum16;
728 int i;
729
730 DENET(qemu_log("%s: %zd bytes\n", __func__, size));
731
732 if (!eth_can_rx(s)) {
733 s->need_flush = true;
734 return 0;
735 }
736
737 unicast = ~buf[0] & 0x1;
738 broadcast = memcmp(buf, sa_bcast, 6) == 0;
739 multicast = !unicast && !broadcast;
740 if (multicast && (memcmp(sa_ipmcast, buf, sizeof sa_ipmcast) == 0)) {
741 ip_multicast = 1;
742 }
743
744
745 if (!(s->rcw[1] & RCW1_JUM)) {
746 if (size > 1518 && size <= 1522 && !(s->rcw[1] & RCW1_VLAN)) {
747 return size;
748 }
749 }
750
751
752
753
754 if (!promisc) {
755 if (unicast) {
756 if (!enet_match_addr(buf, s->uaw[0], s->uaw[1])) {
757 return size;
758 }
759 } else {
760 if (broadcast) {
761
762 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
763 return size;
764 }
765 } else {
766 int drop = 1;
767
768
769 if (s->regs[R_RAF] & RAF_MCAST_REJ) {
770 return size;
771 }
772
773 for (i = 0; i < 4; i++) {
774 if (enet_match_addr(buf, s->maddr[i][0], s->maddr[i][1])) {
775 drop = 0;
776 break;
777 }
778 }
779
780 if (drop) {
781 return size;
782 }
783 }
784 }
785 }
786
787
788 if (axienet_newfunc_enabled(s) && axienet_extmcf_enabled(s)) {
789 if (unicast) {
790 if (!enet_match_addr(buf, s->ext_uaw[0], s->ext_uaw[1])) {
791 return size;
792 }
793 } else {
794 if (broadcast) {
795
796 if (s->regs[R_RAF] & RAF_BCAST_REJ) {
797 return size;
798 }
799 } else {
800 int idx, bit;
801
802
803 if (!memcmp(buf, sa_ipmcast, 3)) {
804 return size;
805 }
806
807 idx = (buf[4] & 0x7f) << 8;
808 idx |= buf[5];
809
810 bit = 1 << (idx & 0x1f);
811 idx >>= 5;
812
813 if (!(s->ext_mtable[idx] & bit)) {
814 return size;
815 }
816 }
817 }
818 }
819
820 if (size < 12) {
821 s->regs[R_IS] |= IS_RX_REJECT;
822 enet_update_irq(s);
823 return -1;
824 }
825
826 if (size > (s->c_rxmem - 4)) {
827 size = s->c_rxmem - 4;
828 }
829
830 memcpy(s->rxmem, buf, size);
831 memset(s->rxmem + size, 0, 4);
832
833 if (s->rcw[1] & RCW1_FCS) {
834 size += 4;
835 }
836
837 app[0] = 5 << 28;
838 csum32 = net_checksum_add(size - 14, (uint8_t *)s->rxmem + 14);
839
840 csum32 = (csum32 & 0xffff) + (csum32 >> 16);
841
842 csum16 = (csum32 & 0xffff) + (csum32 >> 16);
843 app[3] = csum16;
844 app[4] = size & 0xffff;
845
846 s->stats.rx_bytes += size;
847 s->stats.rx++;
848 if (multicast) {
849 s->stats.rx_mcast++;
850 app[2] |= 1 | (ip_multicast << 1);
851 } else if (broadcast) {
852 s->stats.rx_bcast++;
853 app[2] |= 1 << 3;
854 }
855
856
857 app[2] |= 1 << 6;
858
859 s->rxsize = size;
860 s->rxpos = 0;
861 for (i = 0; i < ARRAY_SIZE(app); ++i) {
862 app[i] = cpu_to_le32(app[i]);
863 }
864 s->rxappsize = CONTROL_PAYLOAD_SIZE;
865 memcpy(s->rxapp, app, s->rxappsize);
866 axienet_eth_rx_notify(s);
867
868 enet_update_irq(s);
869 return size;
870}
871
872static size_t
873xilinx_axienet_control_stream_push(StreamSlave *obj, uint8_t *buf, size_t len,
874 uint32_t attr)
875{
876 int i;
877 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
878 XilinxAXIEnet *s = cs->enet;
879
880 if (len != CONTROL_PAYLOAD_SIZE) {
881 hw_error("AXI Enet requires %d byte control stream payload\n",
882 (int)CONTROL_PAYLOAD_SIZE);
883 }
884
885 memcpy(s->hdr, buf, len);
886
887 for (i = 0; i < ARRAY_SIZE(s->hdr); ++i) {
888 s->hdr[i] = le32_to_cpu(s->hdr[i]);
889 }
890 return len;
891}
892
893static size_t
894xilinx_axienet_data_stream_push(StreamSlave *obj, uint8_t *buf, size_t size,
895 uint32_t attr)
896{
897 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
898 XilinxAXIEnet *s = ds->enet;
899
900
901
902 if (!stream_attr_has_eop(attr)) {
903 hw_error("No EOP.\n");
904 }
905
906
907 if (!(s->tc & TC_TX)) {
908 return size;
909 }
910
911
912 if (!(s->tc & TC_JUM)) {
913 if (size > 1518 && size <= 1522 && !(s->tc & TC_VLAN)) {
914 return size;
915 }
916 }
917
918 if (s->hdr[0] & 1) {
919 unsigned int start_off = s->hdr[1] >> 16;
920 unsigned int write_off = s->hdr[1] & 0xffff;
921 uint32_t tmp_csum;
922 uint16_t csum;
923
924 tmp_csum = net_checksum_add(size - start_off,
925 (uint8_t *)buf + start_off);
926
927 tmp_csum += s->hdr[2] & 0xffff;
928
929
930 csum = net_checksum_finish(tmp_csum);
931
932
933 buf[write_off] = csum >> 8;
934 buf[write_off + 1] = csum & 0xff;
935 }
936
937 qemu_send_packet(qemu_get_queue(s->nic), buf, size);
938
939 s->stats.tx_bytes += size;
940 s->regs[R_IS] |= IS_TX_COMPLETE;
941 enet_update_irq(s);
942
943 return size;
944}
945
946static NetClientInfo net_xilinx_enet_info = {
947 .type = NET_CLIENT_OPTIONS_KIND_NIC,
948 .size = sizeof(NICState),
949 .receive = eth_rx,
950};
951
952static void xilinx_enet_realize(DeviceState *dev, Error **errp)
953{
954 XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
955 XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
956 XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(
957 &s->rx_control_dev);
958 Error *local_err = NULL;
959
960 object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
961 (Object **) &ds->enet,
962 object_property_allow_set_link,
963 OBJ_PROP_LINK_UNREF_ON_RELEASE,
964 &local_err);
965 object_property_add_link(OBJECT(cs), "enet", "xlnx.axi-ethernet",
966 (Object **) &cs->enet,
967 object_property_allow_set_link,
968 OBJ_PROP_LINK_UNREF_ON_RELEASE,
969 &local_err);
970 if (local_err) {
971 goto xilinx_enet_realize_fail;
972 }
973 object_property_set_link(OBJECT(ds), OBJECT(s), "enet", &local_err);
974 object_property_set_link(OBJECT(cs), OBJECT(s), "enet", &local_err);
975 if (local_err) {
976 goto xilinx_enet_realize_fail;
977 }
978
979 qemu_macaddr_default_if_unset(&s->conf.macaddr);
980 s->nic = qemu_new_nic(&net_xilinx_enet_info, &s->conf,
981 object_get_typename(OBJECT(dev)), dev->id, s);
982 qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a);
983
984 tdk_init(&s->TEMAC.phy);
985 mdio_attach(&s->TEMAC.mdio_bus, &s->TEMAC.phy, s->c_phyaddr);
986
987 s->TEMAC.parent = s;
988
989 s->rxmem = g_malloc(s->c_rxmem);
990 return;
991
992xilinx_enet_realize_fail:
993 if (!*errp) {
994 *errp = local_err;
995 }
996}
997
998static void xilinx_enet_init(Object *obj)
999{
1000 XilinxAXIEnet *s = XILINX_AXI_ENET(obj);
1001 SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1002
1003 object_property_add_link(obj, "axistream-connected", TYPE_STREAM_SLAVE,
1004 (Object **) &s->tx_data_dev,
1005 qdev_prop_allow_set_link_before_realize,
1006 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1007 &error_abort);
1008 object_property_add_link(obj, "axistream-control-connected",
1009 TYPE_STREAM_SLAVE,
1010 (Object **) &s->tx_control_dev,
1011 qdev_prop_allow_set_link_before_realize,
1012 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1013 &error_abort);
1014
1015 object_initialize(&s->rx_data_dev, sizeof(s->rx_data_dev),
1016 TYPE_XILINX_AXI_ENET_DATA_STREAM);
1017 object_initialize(&s->rx_control_dev, sizeof(s->rx_control_dev),
1018 TYPE_XILINX_AXI_ENET_CONTROL_STREAM);
1019 object_property_add_child(OBJECT(s), "axistream-connected-target",
1020 (Object *)&s->rx_data_dev, &error_abort);
1021 object_property_add_child(OBJECT(s), "axistream-control-connected-target",
1022 (Object *)&s->rx_control_dev, &error_abort);
1023
1024 sysbus_init_irq(sbd, &s->irq);
1025
1026 memory_region_init_io(&s->iomem, OBJECT(s), &enet_ops, s, "enet", 0x40000);
1027 sysbus_init_mmio(sbd, &s->iomem);
1028}
1029
1030static Property xilinx_enet_properties[] = {
1031 DEFINE_PROP_UINT32("phyaddr", XilinxAXIEnet, c_phyaddr, 7),
1032 DEFINE_PROP_UINT32("rxmem", XilinxAXIEnet, c_rxmem, 0x1000),
1033 DEFINE_PROP_UINT32("txmem", XilinxAXIEnet, c_txmem, 0x1000),
1034 DEFINE_NIC_PROPERTIES(XilinxAXIEnet, conf),
1035 DEFINE_PROP_END_OF_LIST(),
1036};
1037
1038static void xilinx_enet_class_init(ObjectClass *klass, void *data)
1039{
1040 DeviceClass *dc = DEVICE_CLASS(klass);
1041
1042 dc->realize = xilinx_enet_realize;
1043 dc->props = xilinx_enet_properties;
1044 dc->reset = xilinx_axienet_reset;
1045}
1046
1047static void xilinx_enet_stream_class_init(ObjectClass *klass, void *data)
1048{
1049 StreamSlaveClass *ssc = STREAM_SLAVE_CLASS(klass);
1050
1051 ssc->push = data;
1052}
1053
1054static const TypeInfo xilinx_enet_info = {
1055 .name = TYPE_XILINX_AXI_ENET,
1056 .parent = TYPE_SYS_BUS_DEVICE,
1057 .instance_size = sizeof(XilinxAXIEnet),
1058 .class_init = xilinx_enet_class_init,
1059 .instance_init = xilinx_enet_init,
1060};
1061
1062static const TypeInfo xilinx_enet_data_stream_info = {
1063 .name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
1064 .parent = TYPE_OBJECT,
1065 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1066 .class_init = xilinx_enet_stream_class_init,
1067 .class_data = xilinx_axienet_data_stream_push,
1068 .interfaces = (InterfaceInfo[]) {
1069 { TYPE_STREAM_SLAVE },
1070 { }
1071 }
1072};
1073
1074static const TypeInfo xilinx_enet_control_stream_info = {
1075 .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
1076 .parent = TYPE_OBJECT,
1077 .instance_size = sizeof(struct XilinxAXIEnetStreamSlave),
1078 .class_init = xilinx_enet_stream_class_init,
1079 .class_data = xilinx_axienet_control_stream_push,
1080 .interfaces = (InterfaceInfo[]) {
1081 { TYPE_STREAM_SLAVE },
1082 { }
1083 }
1084};
1085
1086static void xilinx_enet_register_types(void)
1087{
1088 type_register_static(&xilinx_enet_info);
1089 type_register_static(&xilinx_enet_data_stream_info);
1090 type_register_static(&xilinx_enet_control_stream_info);
1091}
1092
1093type_init(xilinx_enet_register_types)
1094