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25#include "qemu/osdep.h"
26#include "hw/hw.h"
27#include "hw/sh4/sh.h"
28#include "sysemu/sysemu.h"
29#include "sh7750_regs.h"
30#include "sh7750_regnames.h"
31#include "hw/sh4/sh_intc.h"
32#include "cpu.h"
33#include "exec/exec-all.h"
34#include "exec/address-spaces.h"
35
36#define NB_DEVICES 4
37
38typedef struct SH7750State {
39 MemoryRegion iomem;
40 MemoryRegion iomem_1f0;
41 MemoryRegion iomem_ff0;
42 MemoryRegion iomem_1f8;
43 MemoryRegion iomem_ff8;
44 MemoryRegion iomem_1fc;
45 MemoryRegion iomem_ffc;
46 MemoryRegion mmct_iomem;
47
48 SuperHCPU *cpu;
49
50 uint32_t periph_freq;
51
52 uint32_t bcr1;
53 uint16_t bcr2;
54 uint16_t bcr3;
55 uint32_t bcr4;
56 uint16_t rfcr;
57
58 uint16_t pcr;
59
60 uint16_t gpioic;
61 uint32_t pctra;
62 uint32_t pctrb;
63 uint16_t portdira;
64 uint16_t portpullupa;
65 uint16_t portdirb;
66 uint16_t portpullupb;
67 uint16_t pdtra;
68 uint16_t pdtrb;
69 uint16_t periph_pdtra;
70 uint16_t periph_portdira;
71 uint16_t periph_pdtrb;
72 uint16_t periph_portdirb;
73 sh7750_io_device *devices[NB_DEVICES];
74
75
76 uint32_t ccr;
77
78 struct intc_desc intc;
79} SH7750State;
80
81static inline int has_bcr3_and_bcr4(SH7750State * s)
82{
83 return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
84}
85
86
87
88
89int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
90{
91 int i;
92
93 for (i = 0; i < NB_DEVICES; i++) {
94 if (s->devices[i] == NULL) {
95 s->devices[i] = device;
96 return 0;
97 }
98 }
99 return -1;
100}
101
102static uint16_t portdir(uint32_t v)
103{
104#define EVENPORTMASK(n) ((v & (1<<((n)<<1))) >> (n))
105 return
106 EVENPORTMASK(15) | EVENPORTMASK(14) | EVENPORTMASK(13) |
107 EVENPORTMASK(12) | EVENPORTMASK(11) | EVENPORTMASK(10) |
108 EVENPORTMASK(9) | EVENPORTMASK(8) | EVENPORTMASK(7) |
109 EVENPORTMASK(6) | EVENPORTMASK(5) | EVENPORTMASK(4) |
110 EVENPORTMASK(3) | EVENPORTMASK(2) | EVENPORTMASK(1) |
111 EVENPORTMASK(0);
112}
113
114static uint16_t portpullup(uint32_t v)
115{
116#define ODDPORTMASK(n) ((v & (1<<(((n)<<1)+1))) >> (n))
117 return
118 ODDPORTMASK(15) | ODDPORTMASK(14) | ODDPORTMASK(13) |
119 ODDPORTMASK(12) | ODDPORTMASK(11) | ODDPORTMASK(10) |
120 ODDPORTMASK(9) | ODDPORTMASK(8) | ODDPORTMASK(7) | ODDPORTMASK(6) |
121 ODDPORTMASK(5) | ODDPORTMASK(4) | ODDPORTMASK(3) | ODDPORTMASK(2) |
122 ODDPORTMASK(1) | ODDPORTMASK(0);
123}
124
125static uint16_t porta_lines(SH7750State * s)
126{
127 return (s->portdira & s->pdtra) |
128 (s->periph_portdira & s->periph_pdtra) |
129 (~(s->portdira | s->periph_portdira) & s->portpullupa);
130}
131
132static uint16_t portb_lines(SH7750State * s)
133{
134 return (s->portdirb & s->pdtrb) |
135 (s->periph_portdirb & s->periph_pdtrb) |
136 (~(s->portdirb | s->periph_portdirb) & s->portpullupb);
137}
138
139static void gen_port_interrupts(SH7750State * s)
140{
141
142}
143
144static void porta_changed(SH7750State * s, uint16_t prev)
145{
146 uint16_t currenta, changes;
147 int i, r = 0;
148
149#if 0
150 fprintf(stderr, "porta changed from 0x%04x to 0x%04x\n",
151 prev, porta_lines(s));
152 fprintf(stderr, "pdtra=0x%04x, pctra=0x%08x\n", s->pdtra, s->pctra);
153#endif
154 currenta = porta_lines(s);
155 if (currenta == prev)
156 return;
157 changes = currenta ^ prev;
158
159 for (i = 0; i < NB_DEVICES; i++) {
160 if (s->devices[i] && (s->devices[i]->portamask_trigger & changes)) {
161 r |= s->devices[i]->port_change_cb(currenta, portb_lines(s),
162 &s->periph_pdtra,
163 &s->periph_portdira,
164 &s->periph_pdtrb,
165 &s->periph_portdirb);
166 }
167 }
168
169 if (r)
170 gen_port_interrupts(s);
171}
172
173static void portb_changed(SH7750State * s, uint16_t prev)
174{
175 uint16_t currentb, changes;
176 int i, r = 0;
177
178 currentb = portb_lines(s);
179 if (currentb == prev)
180 return;
181 changes = currentb ^ prev;
182
183 for (i = 0; i < NB_DEVICES; i++) {
184 if (s->devices[i] && (s->devices[i]->portbmask_trigger & changes)) {
185 r |= s->devices[i]->port_change_cb(portb_lines(s), currentb,
186 &s->periph_pdtra,
187 &s->periph_portdira,
188 &s->periph_pdtrb,
189 &s->periph_portdirb);
190 }
191 }
192
193 if (r)
194 gen_port_interrupts(s);
195}
196
197
198
199
200
201static void error_access(const char *kind, hwaddr addr)
202{
203 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") not supported\n",
204 kind, regname(addr), addr);
205}
206
207static void ignore_access(const char *kind, hwaddr addr)
208{
209 fprintf(stderr, "%s to %s (0x" TARGET_FMT_plx ") ignored\n",
210 kind, regname(addr), addr);
211}
212
213static uint32_t sh7750_mem_readb(void *opaque, hwaddr addr)
214{
215 switch (addr) {
216 default:
217 error_access("byte read", addr);
218 abort();
219 }
220}
221
222static uint32_t sh7750_mem_readw(void *opaque, hwaddr addr)
223{
224 SH7750State *s = opaque;
225
226 switch (addr) {
227 case SH7750_BCR2_A7:
228 return s->bcr2;
229 case SH7750_BCR3_A7:
230 if(!has_bcr3_and_bcr4(s))
231 error_access("word read", addr);
232 return s->bcr3;
233 case SH7750_FRQCR_A7:
234 return 0;
235 case SH7750_PCR_A7:
236 return s->pcr;
237 case SH7750_RFCR_A7:
238 fprintf(stderr,
239 "Read access to refresh count register, incrementing\n");
240 return s->rfcr++;
241 case SH7750_PDTRA_A7:
242 return porta_lines(s);
243 case SH7750_PDTRB_A7:
244 return portb_lines(s);
245 case SH7750_RTCOR_A7:
246 case SH7750_RTCNT_A7:
247 case SH7750_RTCSR_A7:
248 ignore_access("word read", addr);
249 return 0;
250 default:
251 error_access("word read", addr);
252 abort();
253 }
254}
255
256static uint32_t sh7750_mem_readl(void *opaque, hwaddr addr)
257{
258 SH7750State *s = opaque;
259 SuperHCPUClass *scc;
260
261 switch (addr) {
262 case SH7750_BCR1_A7:
263 return s->bcr1;
264 case SH7750_BCR4_A7:
265 if(!has_bcr3_and_bcr4(s))
266 error_access("long read", addr);
267 return s->bcr4;
268 case SH7750_WCR1_A7:
269 case SH7750_WCR2_A7:
270 case SH7750_WCR3_A7:
271 case SH7750_MCR_A7:
272 ignore_access("long read", addr);
273 return 0;
274 case SH7750_MMUCR_A7:
275 return s->cpu->env.mmucr;
276 case SH7750_PTEH_A7:
277 return s->cpu->env.pteh;
278 case SH7750_PTEL_A7:
279 return s->cpu->env.ptel;
280 case SH7750_TTB_A7:
281 return s->cpu->env.ttb;
282 case SH7750_TEA_A7:
283 return s->cpu->env.tea;
284 case SH7750_TRA_A7:
285 return s->cpu->env.tra;
286 case SH7750_EXPEVT_A7:
287 return s->cpu->env.expevt;
288 case SH7750_INTEVT_A7:
289 return s->cpu->env.intevt;
290 case SH7750_CCR_A7:
291 return s->ccr;
292 case 0x1f000030:
293 scc = SUPERH_CPU_GET_CLASS(s->cpu);
294 return scc->pvr;
295 case 0x1f000040:
296 scc = SUPERH_CPU_GET_CLASS(s->cpu);
297 return scc->cvr;
298 case 0x1f000044:
299 scc = SUPERH_CPU_GET_CLASS(s->cpu);
300 return scc->prr;
301 default:
302 error_access("long read", addr);
303 abort();
304 }
305}
306
307#define is_in_sdrmx(a, x) (a >= SH7750_SDMR ## x ## _A7 \
308 && a <= (SH7750_SDMR ## x ## _A7 + SH7750_SDMR ## x ## _REGNB))
309static void sh7750_mem_writeb(void *opaque, hwaddr addr,
310 uint32_t mem_value)
311{
312
313 if (is_in_sdrmx(addr, 2) || is_in_sdrmx(addr, 3)) {
314 ignore_access("byte write", addr);
315 return;
316 }
317
318 error_access("byte write", addr);
319 abort();
320}
321
322static void sh7750_mem_writew(void *opaque, hwaddr addr,
323 uint32_t mem_value)
324{
325 SH7750State *s = opaque;
326 uint16_t temp;
327
328 switch (addr) {
329
330 case SH7750_BCR2_A7:
331 s->bcr2 = mem_value;
332 return;
333 case SH7750_BCR3_A7:
334 if(!has_bcr3_and_bcr4(s))
335 error_access("word write", addr);
336 s->bcr3 = mem_value;
337 return;
338 case SH7750_PCR_A7:
339 s->pcr = mem_value;
340 return;
341 case SH7750_RTCNT_A7:
342 case SH7750_RTCOR_A7:
343 case SH7750_RTCSR_A7:
344 ignore_access("word write", addr);
345 return;
346
347 case SH7750_PDTRA_A7:
348 temp = porta_lines(s);
349 s->pdtra = mem_value;
350 porta_changed(s, temp);
351 return;
352 case SH7750_PDTRB_A7:
353 temp = portb_lines(s);
354 s->pdtrb = mem_value;
355 portb_changed(s, temp);
356 return;
357 case SH7750_RFCR_A7:
358 fprintf(stderr, "Write access to refresh count register\n");
359 s->rfcr = mem_value;
360 return;
361 case SH7750_GPIOIC_A7:
362 s->gpioic = mem_value;
363 if (mem_value != 0) {
364 fprintf(stderr, "I/O interrupts not implemented\n");
365 abort();
366 }
367 return;
368 default:
369 error_access("word write", addr);
370 abort();
371 }
372}
373
374static void sh7750_mem_writel(void *opaque, hwaddr addr,
375 uint32_t mem_value)
376{
377 SH7750State *s = opaque;
378 uint16_t temp;
379
380 switch (addr) {
381
382 case SH7750_BCR1_A7:
383 s->bcr1 = mem_value;
384 return;
385 case SH7750_BCR4_A7:
386 if(!has_bcr3_and_bcr4(s))
387 error_access("long write", addr);
388 s->bcr4 = mem_value;
389 return;
390 case SH7750_WCR1_A7:
391 case SH7750_WCR2_A7:
392 case SH7750_WCR3_A7:
393 case SH7750_MCR_A7:
394 ignore_access("long write", addr);
395 return;
396
397 case SH7750_PCTRA_A7:
398 temp = porta_lines(s);
399 s->pctra = mem_value;
400 s->portdira = portdir(mem_value);
401 s->portpullupa = portpullup(mem_value);
402 porta_changed(s, temp);
403 return;
404 case SH7750_PCTRB_A7:
405 temp = portb_lines(s);
406 s->pctrb = mem_value;
407 s->portdirb = portdir(mem_value);
408 s->portpullupb = portpullup(mem_value);
409 portb_changed(s, temp);
410 return;
411 case SH7750_MMUCR_A7:
412 if (mem_value & MMUCR_TI) {
413 cpu_sh4_invalidate_tlb(&s->cpu->env);
414 }
415 s->cpu->env.mmucr = mem_value & ~MMUCR_TI;
416 return;
417 case SH7750_PTEH_A7:
418
419 if ((s->cpu->env.pteh & 0xff) != (mem_value & 0xff)) {
420 tlb_flush(CPU(s->cpu), 1);
421 }
422 s->cpu->env.pteh = mem_value;
423 return;
424 case SH7750_PTEL_A7:
425 s->cpu->env.ptel = mem_value;
426 return;
427 case SH7750_PTEA_A7:
428 s->cpu->env.ptea = mem_value & 0x0000000f;
429 return;
430 case SH7750_TTB_A7:
431 s->cpu->env.ttb = mem_value;
432 return;
433 case SH7750_TEA_A7:
434 s->cpu->env.tea = mem_value;
435 return;
436 case SH7750_TRA_A7:
437 s->cpu->env.tra = mem_value & 0x000007ff;
438 return;
439 case SH7750_EXPEVT_A7:
440 s->cpu->env.expevt = mem_value & 0x000007ff;
441 return;
442 case SH7750_INTEVT_A7:
443 s->cpu->env.intevt = mem_value & 0x000007ff;
444 return;
445 case SH7750_CCR_A7:
446 s->ccr = mem_value;
447 return;
448 default:
449 error_access("long write", addr);
450 abort();
451 }
452}
453
454static const MemoryRegionOps sh7750_mem_ops = {
455 .old_mmio = {
456 .read = {sh7750_mem_readb,
457 sh7750_mem_readw,
458 sh7750_mem_readl },
459 .write = {sh7750_mem_writeb,
460 sh7750_mem_writew,
461 sh7750_mem_writel },
462 },
463 .endianness = DEVICE_NATIVE_ENDIAN,
464};
465
466
467
468
469
470enum {
471 UNUSED = 0,
472
473
474 IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6, IRL_7,
475 IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E,
476 IRL0, IRL1, IRL2, IRL3,
477 HUDI, GPIOI,
478 DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2, DMAC_DMTE3,
479 DMAC_DMTE4, DMAC_DMTE5, DMAC_DMTE6, DMAC_DMTE7,
480 DMAC_DMAE,
481 PCIC0_PCISERR, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
482 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3,
483 TMU3, TMU4, TMU0, TMU1, TMU2_TUNI, TMU2_TICPI,
484 RTC_ATI, RTC_PRI, RTC_CUI,
485 SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI,
486 SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI,
487 WDT,
488 REF_RCMI, REF_ROVI,
489
490
491 DMAC, PCIC1, TMU2, RTC, SCI1, SCIF, REF,
492
493 IRL,
494
495 NR_SOURCES,
496};
497
498static struct intc_vect vectors[] = {
499 INTC_VECT(HUDI, 0x600), INTC_VECT(GPIOI, 0x620),
500 INTC_VECT(TMU0, 0x400), INTC_VECT(TMU1, 0x420),
501 INTC_VECT(TMU2_TUNI, 0x440), INTC_VECT(TMU2_TICPI, 0x460),
502 INTC_VECT(RTC_ATI, 0x480), INTC_VECT(RTC_PRI, 0x4a0),
503 INTC_VECT(RTC_CUI, 0x4c0),
504 INTC_VECT(SCI1_ERI, 0x4e0), INTC_VECT(SCI1_RXI, 0x500),
505 INTC_VECT(SCI1_TXI, 0x520), INTC_VECT(SCI1_TEI, 0x540),
506 INTC_VECT(SCIF_ERI, 0x700), INTC_VECT(SCIF_RXI, 0x720),
507 INTC_VECT(SCIF_BRI, 0x740), INTC_VECT(SCIF_TXI, 0x760),
508 INTC_VECT(WDT, 0x560),
509 INTC_VECT(REF_RCMI, 0x580), INTC_VECT(REF_ROVI, 0x5a0),
510};
511
512static struct intc_group groups[] = {
513 INTC_GROUP(TMU2, TMU2_TUNI, TMU2_TICPI),
514 INTC_GROUP(RTC, RTC_ATI, RTC_PRI, RTC_CUI),
515 INTC_GROUP(SCI1, SCI1_ERI, SCI1_RXI, SCI1_TXI, SCI1_TEI),
516 INTC_GROUP(SCIF, SCIF_ERI, SCIF_RXI, SCIF_BRI, SCIF_TXI),
517 INTC_GROUP(REF, REF_RCMI, REF_ROVI),
518};
519
520static struct intc_prio_reg prio_registers[] = {
521 { 0xffd00004, 0, 16, 4, { TMU0, TMU1, TMU2, RTC } },
522 { 0xffd00008, 0, 16, 4, { WDT, REF, SCI1, 0 } },
523 { 0xffd0000c, 0, 16, 4, { GPIOI, DMAC, SCIF, HUDI } },
524 { 0xffd00010, 0, 16, 4, { IRL0, IRL1, IRL2, IRL3 } },
525 { 0xfe080000, 0, 32, 4, { 0, 0, 0, 0,
526 TMU4, TMU3,
527 PCIC1, PCIC0_PCISERR } },
528};
529
530
531
532static struct intc_vect vectors_dma4[] = {
533 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
534 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
535 INTC_VECT(DMAC_DMAE, 0x6c0),
536};
537
538static struct intc_group groups_dma4[] = {
539 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
540 DMAC_DMTE3, DMAC_DMAE),
541};
542
543
544
545static struct intc_vect vectors_dma8[] = {
546 INTC_VECT(DMAC_DMTE0, 0x640), INTC_VECT(DMAC_DMTE1, 0x660),
547 INTC_VECT(DMAC_DMTE2, 0x680), INTC_VECT(DMAC_DMTE3, 0x6a0),
548 INTC_VECT(DMAC_DMTE4, 0x780), INTC_VECT(DMAC_DMTE5, 0x7a0),
549 INTC_VECT(DMAC_DMTE6, 0x7c0), INTC_VECT(DMAC_DMTE7, 0x7e0),
550 INTC_VECT(DMAC_DMAE, 0x6c0),
551};
552
553static struct intc_group groups_dma8[] = {
554 INTC_GROUP(DMAC, DMAC_DMTE0, DMAC_DMTE1, DMAC_DMTE2,
555 DMAC_DMTE3, DMAC_DMTE4, DMAC_DMTE5,
556 DMAC_DMTE6, DMAC_DMTE7, DMAC_DMAE),
557};
558
559
560
561static struct intc_vect vectors_tmu34[] = {
562 INTC_VECT(TMU3, 0xb00), INTC_VECT(TMU4, 0xb80),
563};
564
565static struct intc_mask_reg mask_registers[] = {
566 { 0xfe080040, 0xfe080060, 32,
567 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
568 0, 0, 0, 0, 0, 0, TMU4, TMU3,
569 PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
570 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2,
571 PCIC1_PCIDMA3, PCIC0_PCISERR } },
572};
573
574
575
576static struct intc_vect vectors_irlm[] = {
577 INTC_VECT(IRL0, 0x240), INTC_VECT(IRL1, 0x2a0),
578 INTC_VECT(IRL2, 0x300), INTC_VECT(IRL3, 0x360),
579};
580
581
582
583static struct intc_vect vectors_pci[] = {
584 INTC_VECT(PCIC0_PCISERR, 0xa00), INTC_VECT(PCIC1_PCIERR, 0xae0),
585 INTC_VECT(PCIC1_PCIPWDWN, 0xac0), INTC_VECT(PCIC1_PCIPWON, 0xaa0),
586 INTC_VECT(PCIC1_PCIDMA0, 0xa80), INTC_VECT(PCIC1_PCIDMA1, 0xa60),
587 INTC_VECT(PCIC1_PCIDMA2, 0xa40), INTC_VECT(PCIC1_PCIDMA3, 0xa20),
588};
589
590static struct intc_group groups_pci[] = {
591 INTC_GROUP(PCIC1, PCIC1_PCIERR, PCIC1_PCIPWDWN, PCIC1_PCIPWON,
592 PCIC1_PCIDMA0, PCIC1_PCIDMA1, PCIC1_PCIDMA2, PCIC1_PCIDMA3),
593};
594
595static struct intc_vect vectors_irl[] = {
596 INTC_VECT(IRL_0, 0x200),
597 INTC_VECT(IRL_1, 0x220),
598 INTC_VECT(IRL_2, 0x240),
599 INTC_VECT(IRL_3, 0x260),
600 INTC_VECT(IRL_4, 0x280),
601 INTC_VECT(IRL_5, 0x2a0),
602 INTC_VECT(IRL_6, 0x2c0),
603 INTC_VECT(IRL_7, 0x2e0),
604 INTC_VECT(IRL_8, 0x300),
605 INTC_VECT(IRL_9, 0x320),
606 INTC_VECT(IRL_A, 0x340),
607 INTC_VECT(IRL_B, 0x360),
608 INTC_VECT(IRL_C, 0x380),
609 INTC_VECT(IRL_D, 0x3a0),
610 INTC_VECT(IRL_E, 0x3c0),
611};
612
613static struct intc_group groups_irl[] = {
614 INTC_GROUP(IRL, IRL_0, IRL_1, IRL_2, IRL_3, IRL_4, IRL_5, IRL_6,
615 IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
616};
617
618
619
620
621
622#define MM_REGION_MASK 0x07000000
623#define MM_ICACHE_ADDR (0)
624#define MM_ICACHE_DATA (1)
625#define MM_ITLB_ADDR (2)
626#define MM_ITLB_DATA (3)
627#define MM_OCACHE_ADDR (4)
628#define MM_OCACHE_DATA (5)
629#define MM_UTLB_ADDR (6)
630#define MM_UTLB_DATA (7)
631#define MM_REGION_TYPE(addr) ((addr & MM_REGION_MASK) >> 24)
632
633static uint64_t invalid_read(void *opaque, hwaddr addr)
634{
635 abort();
636
637 return 0;
638}
639
640static uint64_t sh7750_mmct_read(void *opaque, hwaddr addr,
641 unsigned size)
642{
643 SH7750State *s = opaque;
644 uint32_t ret = 0;
645
646 if (size != 4) {
647 return invalid_read(opaque, addr);
648 }
649
650 switch (MM_REGION_TYPE(addr)) {
651 case MM_ICACHE_ADDR:
652 case MM_ICACHE_DATA:
653
654 break;
655 case MM_ITLB_ADDR:
656 ret = cpu_sh4_read_mmaped_itlb_addr(&s->cpu->env, addr);
657 break;
658 case MM_ITLB_DATA:
659 ret = cpu_sh4_read_mmaped_itlb_data(&s->cpu->env, addr);
660 break;
661 case MM_OCACHE_ADDR:
662 case MM_OCACHE_DATA:
663
664 break;
665 case MM_UTLB_ADDR:
666 ret = cpu_sh4_read_mmaped_utlb_addr(&s->cpu->env, addr);
667 break;
668 case MM_UTLB_DATA:
669 ret = cpu_sh4_read_mmaped_utlb_data(&s->cpu->env, addr);
670 break;
671 default:
672 abort();
673 }
674
675 return ret;
676}
677
678static void invalid_write(void *opaque, hwaddr addr,
679 uint64_t mem_value)
680{
681 abort();
682}
683
684static void sh7750_mmct_write(void *opaque, hwaddr addr,
685 uint64_t mem_value, unsigned size)
686{
687 SH7750State *s = opaque;
688
689 if (size != 4) {
690 invalid_write(opaque, addr, mem_value);
691 }
692
693 switch (MM_REGION_TYPE(addr)) {
694 case MM_ICACHE_ADDR:
695 case MM_ICACHE_DATA:
696
697 break;
698 case MM_ITLB_ADDR:
699 cpu_sh4_write_mmaped_itlb_addr(&s->cpu->env, addr, mem_value);
700 break;
701 case MM_ITLB_DATA:
702 cpu_sh4_write_mmaped_itlb_data(&s->cpu->env, addr, mem_value);
703 abort();
704 break;
705 case MM_OCACHE_ADDR:
706 case MM_OCACHE_DATA:
707
708 break;
709 case MM_UTLB_ADDR:
710 cpu_sh4_write_mmaped_utlb_addr(&s->cpu->env, addr, mem_value);
711 break;
712 case MM_UTLB_DATA:
713 cpu_sh4_write_mmaped_utlb_data(&s->cpu->env, addr, mem_value);
714 break;
715 default:
716 abort();
717 break;
718 }
719}
720
721static const MemoryRegionOps sh7750_mmct_ops = {
722 .read = sh7750_mmct_read,
723 .write = sh7750_mmct_write,
724 .endianness = DEVICE_NATIVE_ENDIAN,
725};
726
727SH7750State *sh7750_init(SuperHCPU *cpu, MemoryRegion *sysmem)
728{
729 SH7750State *s;
730
731 s = g_malloc0(sizeof(SH7750State));
732 s->cpu = cpu;
733 s->periph_freq = 60000000;
734 memory_region_init_io(&s->iomem, NULL, &sh7750_mem_ops, s,
735 "memory", 0x1fc01000);
736
737 memory_region_init_alias(&s->iomem_1f0, NULL, "memory-1f0",
738 &s->iomem, 0x1f000000, 0x1000);
739 memory_region_add_subregion(sysmem, 0x1f000000, &s->iomem_1f0);
740
741 memory_region_init_alias(&s->iomem_ff0, NULL, "memory-ff0",
742 &s->iomem, 0x1f000000, 0x1000);
743 memory_region_add_subregion(sysmem, 0xff000000, &s->iomem_ff0);
744
745 memory_region_init_alias(&s->iomem_1f8, NULL, "memory-1f8",
746 &s->iomem, 0x1f800000, 0x1000);
747 memory_region_add_subregion(sysmem, 0x1f800000, &s->iomem_1f8);
748
749 memory_region_init_alias(&s->iomem_ff8, NULL, "memory-ff8",
750 &s->iomem, 0x1f800000, 0x1000);
751 memory_region_add_subregion(sysmem, 0xff800000, &s->iomem_ff8);
752
753 memory_region_init_alias(&s->iomem_1fc, NULL, "memory-1fc",
754 &s->iomem, 0x1fc00000, 0x1000);
755 memory_region_add_subregion(sysmem, 0x1fc00000, &s->iomem_1fc);
756
757 memory_region_init_alias(&s->iomem_ffc, NULL, "memory-ffc",
758 &s->iomem, 0x1fc00000, 0x1000);
759 memory_region_add_subregion(sysmem, 0xffc00000, &s->iomem_ffc);
760
761 memory_region_init_io(&s->mmct_iomem, NULL, &sh7750_mmct_ops, s,
762 "cache-and-tlb", 0x08000000);
763 memory_region_add_subregion(sysmem, 0xf0000000, &s->mmct_iomem);
764
765 sh_intc_init(sysmem, &s->intc, NR_SOURCES,
766 _INTC_ARRAY(mask_registers),
767 _INTC_ARRAY(prio_registers));
768
769 sh_intc_register_sources(&s->intc,
770 _INTC_ARRAY(vectors),
771 _INTC_ARRAY(groups));
772
773 cpu->env.intc_handle = &s->intc;
774
775 sh_serial_init(sysmem, 0x1fe00000,
776 0, s->periph_freq, serial_hds[0],
777 s->intc.irqs[SCI1_ERI],
778 s->intc.irqs[SCI1_RXI],
779 s->intc.irqs[SCI1_TXI],
780 s->intc.irqs[SCI1_TEI],
781 NULL);
782 sh_serial_init(sysmem, 0x1fe80000,
783 SH_SERIAL_FEAT_SCIF,
784 s->periph_freq, serial_hds[1],
785 s->intc.irqs[SCIF_ERI],
786 s->intc.irqs[SCIF_RXI],
787 s->intc.irqs[SCIF_TXI],
788 NULL,
789 s->intc.irqs[SCIF_BRI]);
790
791 tmu012_init(sysmem, 0x1fd80000,
792 TMU012_FEAT_TOCR | TMU012_FEAT_3CHAN | TMU012_FEAT_EXTCLK,
793 s->periph_freq,
794 s->intc.irqs[TMU0],
795 s->intc.irqs[TMU1],
796 s->intc.irqs[TMU2_TUNI],
797 s->intc.irqs[TMU2_TICPI]);
798
799 if (cpu->env.id & (SH_CPU_SH7750 | SH_CPU_SH7750S | SH_CPU_SH7751)) {
800 sh_intc_register_sources(&s->intc,
801 _INTC_ARRAY(vectors_dma4),
802 _INTC_ARRAY(groups_dma4));
803 }
804
805 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751R)) {
806 sh_intc_register_sources(&s->intc,
807 _INTC_ARRAY(vectors_dma8),
808 _INTC_ARRAY(groups_dma8));
809 }
810
811 if (cpu->env.id & (SH_CPU_SH7750R | SH_CPU_SH7751 | SH_CPU_SH7751R)) {
812 sh_intc_register_sources(&s->intc,
813 _INTC_ARRAY(vectors_tmu34),
814 NULL, 0);
815 tmu012_init(sysmem, 0x1e100000, 0, s->periph_freq,
816 s->intc.irqs[TMU3],
817 s->intc.irqs[TMU4],
818 NULL, NULL);
819 }
820
821 if (cpu->env.id & (SH_CPU_SH7751_ALL)) {
822 sh_intc_register_sources(&s->intc,
823 _INTC_ARRAY(vectors_pci),
824 _INTC_ARRAY(groups_pci));
825 }
826
827 if (cpu->env.id & (SH_CPU_SH7750S | SH_CPU_SH7750R | SH_CPU_SH7751_ALL)) {
828 sh_intc_register_sources(&s->intc,
829 _INTC_ARRAY(vectors_irlm),
830 NULL, 0);
831 }
832
833 sh_intc_register_sources(&s->intc,
834 _INTC_ARRAY(vectors_irl),
835 _INTC_ARRAY(groups_irl));
836 return s;
837}
838
839qemu_irq sh7750_irl(SH7750State *s)
840{
841 sh_intc_toggle_source(sh_intc_source(&s->intc, IRL), 1, 0);
842 return qemu_allocate_irq(sh_intc_set_irl, sh_intc_source(&s->intc, IRL), 0);
843}
844
