LXR qemu/target-i386/int

   1/*
   2 *  x86 integer helpers
   3 *
   4 *  Copyright (c) 2003 Fabrice Bellard
   5 *
   6 * This library is free software; you can redistribute it and/or
   7 * modify it under the terms of the GNU Lesser General Public
   8 * License as published by the Free Software Foundation; either
   9 * version 2 of the License, or (at your option) any later version.
  10 *
  11 * This library is distributed in the hope that it will be useful,
  12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14 * Lesser General Public License for more details.
  15 *
  16 * You should have received a copy of the GNU Lesser General Public
  17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18 */
  19
  20#include "qemu/osdep.h"
  21#include "cpu.h"
  22#include "qemu/host-utils.h"
  23#include "exec/helper-proto.h"
  24
  25//#define DEBUG_MULDIV
  26
  27/* modulo 9 table */
  28static const uint8_t rclb_table[32] = {
  29    0, 1, 2, 3, 4, 5, 6, 7,
  30    8, 0, 1, 2, 3, 4, 5, 6,
  31    7, 8, 0, 1, 2, 3, 4, 5,
  32    6, 7, 8, 0, 1, 2, 3, 4,
  33};
  34
  35/* modulo 17 table */
  36static const uint8_t rclw_table[32] = {
  37    0, 1, 2, 3, 4, 5, 6, 7,
  38    8, 9, 10, 11, 12, 13, 14, 15,
  39    16, 0, 1, 2, 3, 4, 5, 6,
  40    7, 8, 9, 10, 11, 12, 13, 14,
  41};
  42
  43/* division, flags are undefined */
  44
  45void helper_divb_AL(CPUX86State *env, target_ulong t0)
  46{
  47    unsigned int num, den, q, r;
  48
  49    num = (env->regs[R_EAX] & 0xffff);
  50    den = (t0 & 0xff);
  51    if (den == 0) {
  52        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
  53    }
  54    q = (num / den);
  55    if (q > 0xff) {
  56        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
  57    }
  58    q &= 0xff;
  59    r = (num % den) & 0xff;
  60    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
  61}
  62
  63void helper_idivb_AL(CPUX86State *env, target_ulong t0)
  64{
  65    int num, den, q, r;
  66
  67    num = (int16_t)env->regs[R_EAX];
  68    den = (int8_t)t0;
  69    if (den == 0) {
  70        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
  71    }
  72    q = (num / den);
  73    if (q != (int8_t)q) {
  74        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
  75    }
  76    q &= 0xff;
  77    r = (num % den) & 0xff;
  78    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | (r << 8) | q;
  79}
  80
  81void helper_divw_AX(CPUX86State *env, target_ulong t0)
  82{
  83    unsigned int num, den, q, r;
  84
  85    num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
  86    den = (t0 & 0xffff);
  87    if (den == 0) {
  88        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
  89    }
  90    q = (num / den);
  91    if (q > 0xffff) {
  92        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
  93    }
  94    q &= 0xffff;
  95    r = (num % den) & 0xffff;
  96    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
  97    env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
  98}
  99
 100void helper_idivw_AX(CPUX86State *env, target_ulong t0)
 101{
 102    int num, den, q, r;
 103
 104    num = (env->regs[R_EAX] & 0xffff) | ((env->regs[R_EDX] & 0xffff) << 16);
 105    den = (int16_t)t0;
 106    if (den == 0) {
 107        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 108    }
 109    q = (num / den);
 110    if (q != (int16_t)q) {
 111        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 112    }
 113    q &= 0xffff;
 114    r = (num % den) & 0xffff;
 115    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | q;
 116    env->regs[R_EDX] = (env->regs[R_EDX] & ~0xffff) | r;
 117}
 118
 119void helper_divl_EAX(CPUX86State *env, target_ulong t0)
 120{
 121    unsigned int den, r;
 122    uint64_t num, q;
 123
 124    num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
 125    den = t0;
 126    if (den == 0) {
 127        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 128    }
 129    q = (num / den);
 130    r = (num % den);
 131    if (q > 0xffffffff) {
 132        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 133    }
 134    env->regs[R_EAX] = (uint32_t)q;
 135    env->regs[R_EDX] = (uint32_t)r;
 136}
 137
 138void helper_idivl_EAX(CPUX86State *env, target_ulong t0)
 139{
 140    int den, r;
 141    int64_t num, q;
 142
 143    num = ((uint32_t)env->regs[R_EAX]) | ((uint64_t)((uint32_t)env->regs[R_EDX]) << 32);
 144    den = t0;
 145    if (den == 0) {
 146        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 147    }
 148    q = (num / den);
 149    r = (num % den);
 150    if (q != (int32_t)q) {
 151        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 152    }
 153    env->regs[R_EAX] = (uint32_t)q;
 154    env->regs[R_EDX] = (uint32_t)r;
 155}
 156
 157/* bcd */
 158
 159/* XXX: exception */
 160void helper_aam(CPUX86State *env, int base)
 161{
 162    int al, ah;
 163
 164    al = env->regs[R_EAX] & 0xff;
 165    ah = al / base;
 166    al = al % base;
 167    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
 168    CC_DST = al;
 169}
 170
 171void helper_aad(CPUX86State *env, int base)
 172{
 173    int al, ah;
 174
 175    al = env->regs[R_EAX] & 0xff;
 176    ah = (env->regs[R_EAX] >> 8) & 0xff;
 177    al = ((ah * base) + al) & 0xff;
 178    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al;
 179    CC_DST = al;
 180}
 181
 182void helper_aaa(CPUX86State *env)
 183{
 184    int icarry;
 185    int al, ah, af;
 186    int eflags;
 187
 188    eflags = cpu_cc_compute_all(env, CC_OP);
 189    af = eflags & CC_A;
 190    al = env->regs[R_EAX] & 0xff;
 191    ah = (env->regs[R_EAX] >> 8) & 0xff;
 192
 193    icarry = (al > 0xf9);
 194    if (((al & 0x0f) > 9) || af) {
 195        al = (al + 6) & 0x0f;
 196        ah = (ah + 1 + icarry) & 0xff;
 197        eflags |= CC_C | CC_A;
 198    } else {
 199        eflags &= ~(CC_C | CC_A);
 200        al &= 0x0f;
 201    }
 202    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
 203    CC_SRC = eflags;
 204}
 205
 206void helper_aas(CPUX86State *env)
 207{
 208    int icarry;
 209    int al, ah, af;
 210    int eflags;
 211
 212    eflags = cpu_cc_compute_all(env, CC_OP);
 213    af = eflags & CC_A;
 214    al = env->regs[R_EAX] & 0xff;
 215    ah = (env->regs[R_EAX] >> 8) & 0xff;
 216
 217    icarry = (al < 6);
 218    if (((al & 0x0f) > 9) || af) {
 219        al = (al - 6) & 0x0f;
 220        ah = (ah - 1 - icarry) & 0xff;
 221        eflags |= CC_C | CC_A;
 222    } else {
 223        eflags &= ~(CC_C | CC_A);
 224        al &= 0x0f;
 225    }
 226    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xffff) | al | (ah << 8);
 227    CC_SRC = eflags;
 228}
 229
 230void helper_daa(CPUX86State *env)
 231{
 232    int old_al, al, af, cf;
 233    int eflags;
 234
 235    eflags = cpu_cc_compute_all(env, CC_OP);
 236    cf = eflags & CC_C;
 237    af = eflags & CC_A;
 238    old_al = al = env->regs[R_EAX] & 0xff;
 239
 240    eflags = 0;
 241    if (((al & 0x0f) > 9) || af) {
 242        al = (al + 6) & 0xff;
 243        eflags |= CC_A;
 244    }
 245    if ((old_al > 0x99) || cf) {
 246        al = (al + 0x60) & 0xff;
 247        eflags |= CC_C;
 248    }
 249    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
 250    /* well, speed is not an issue here, so we compute the flags by hand */
 251    eflags |= (al == 0) << 6; /* zf */
 252    eflags |= parity_table[al]; /* pf */
 253    eflags |= (al & 0x80); /* sf */
 254    CC_SRC = eflags;
 255}
 256
 257void helper_das(CPUX86State *env)
 258{
 259    int al, al1, af, cf;
 260    int eflags;
 261
 262    eflags = cpu_cc_compute_all(env, CC_OP);
 263    cf = eflags & CC_C;
 264    af = eflags & CC_A;
 265    al = env->regs[R_EAX] & 0xff;
 266
 267    eflags = 0;
 268    al1 = al;
 269    if (((al & 0x0f) > 9) || af) {
 270        eflags |= CC_A;
 271        if (al < 6 || cf) {
 272            eflags |= CC_C;
 273        }
 274        al = (al - 6) & 0xff;
 275    }
 276    if ((al1 > 0x99) || cf) {
 277        al = (al - 0x60) & 0xff;
 278        eflags |= CC_C;
 279    }
 280    env->regs[R_EAX] = (env->regs[R_EAX] & ~0xff) | al;
 281    /* well, speed is not an issue here, so we compute the flags by hand */
 282    eflags |= (al == 0) << 6; /* zf */
 283    eflags |= parity_table[al]; /* pf */
 284    eflags |= (al & 0x80); /* sf */
 285    CC_SRC = eflags;
 286}
 287
 288#ifdef TARGET_X86_64
 289static void add128(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b)
 290{
 291    *plow += a;
 292    /* carry test */
 293    if (*plow < a) {
 294        (*phigh)++;
 295    }
 296    *phigh += b;
 297}
 298
 299static void neg128(uint64_t *plow, uint64_t *phigh)
 300{
 301    *plow = ~*plow;
 302    *phigh = ~*phigh;
 303    add128(plow, phigh, 1, 0);
 304}
 305
 306/* return TRUE if overflow */
 307static int div64(uint64_t *plow, uint64_t *phigh, uint64_t b)
 308{
 309    uint64_t q, r, a1, a0;
 310    int i, qb, ab;
 311
 312    a0 = *plow;
 313    a1 = *phigh;
 314    if (a1 == 0) {
 315        q = a0 / b;
 316        r = a0 % b;
 317        *plow = q;
 318        *phigh = r;
 319    } else {
 320        if (a1 >= b) {
 321            return 1;
 322        }
 323        /* XXX: use a better algorithm */
 324        for (i = 0; i < 64; i++) {
 325            ab = a1 >> 63;
 326            a1 = (a1 << 1) | (a0 >> 63);
 327            if (ab || a1 >= b) {
 328                a1 -= b;
 329                qb = 1;
 330            } else {
 331                qb = 0;
 332            }
 333            a0 = (a0 << 1) | qb;
 334        }
 335#if defined(DEBUG_MULDIV)
 336        printf("div: 0x%016" PRIx64 "%016" PRIx64 " / 0x%016" PRIx64
 337               ": q=0x%016" PRIx64 " r=0x%016" PRIx64 "\n",
 338               *phigh, *plow, b, a0, a1);
 339#endif
 340        *plow = a0;
 341        *phigh = a1;
 342    }
 343    return 0;
 344}
 345
 346/* return TRUE if overflow */
 347static int idiv64(uint64_t *plow, uint64_t *phigh, int64_t b)
 348{
 349    int sa, sb;
 350
 351    sa = ((int64_t)*phigh < 0);
 352    if (sa) {
 353        neg128(plow, phigh);
 354    }
 355    sb = (b < 0);
 356    if (sb) {
 357        b = -b;
 358    }
 359    if (div64(plow, phigh, b) != 0) {
 360        return 1;
 361    }
 362    if (sa ^ sb) {
 363        if (*plow > (1ULL << 63)) {
 364            return 1;
 365        }
 366        *plow = -*plow;
 367    } else {
 368        if (*plow >= (1ULL << 63)) {
 369            return 1;
 370        }
 371    }
 372    if (sa) {
 373        *phigh = -*phigh;
 374    }
 375    return 0;
 376}
 377
 378void helper_divq_EAX(CPUX86State *env, target_ulong t0)
 379{
 380    uint64_t r0, r1;
 381
 382    if (t0 == 0) {
 383        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 384    }
 385    r0 = env->regs[R_EAX];
 386    r1 = env->regs[R_EDX];
 387    if (div64(&r0, &r1, t0)) {
 388        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 389    }
 390    env->regs[R_EAX] = r0;
 391    env->regs[R_EDX] = r1;
 392}
 393
 394void helper_idivq_EAX(CPUX86State *env, target_ulong t0)
 395{
 396    uint64_t r0, r1;
 397
 398    if (t0 == 0) {
 399        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 400    }
 401    r0 = env->regs[R_EAX];
 402    r1 = env->regs[R_EDX];
 403    if (idiv64(&r0, &r1, t0)) {
 404        raise_exception_ra(env, EXCP00_DIVZ, GETPC());
 405    }
 406    env->regs[R_EAX] = r0;
 407    env->regs[R_EDX] = r1;
 408}
 409#endif
 410
 411#if TARGET_LONG_BITS == 32
 412# define ctztl  ctz32
 413# define clztl  clz32
 414#else
 415# define ctztl  ctz64
 416# define clztl  clz64
 417#endif
 418
 419/* bit operations */
 420target_ulong helper_ctz(target_ulong t0)
 421{
 422    return ctztl(t0);
 423}
 424
 425target_ulong helper_clz(target_ulong t0)
 426{
 427    return clztl(t0);
 428}
 429
 430target_ulong helper_pdep(target_ulong src, target_ulong mask)
 431{
 432    target_ulong dest = 0;
 433    int i, o;
 434
 435    for (i = 0; mask != 0; i++) {
 436        o = ctztl(mask);
 437        mask &= mask - 1;
 438        dest |= ((src >> i) & 1) << o;
 439    }
 440    return dest;
 441}
 442
 443target_ulong helper_pext(target_ulong src, target_ulong mask)
 444{
 445    target_ulong dest = 0;
 446    int i, o;
 447
 448    for (o = 0; mask != 0; o++) {
 449        i = ctztl(mask);
 450        mask &= mask - 1;
 451        dest |= ((src >> i) & 1) << o;
 452    }
 453    return dest;
 454}
 455
 456#define SHIFT 0
 457#include "shift_helper_template.h"
 458#undef SHIFT
 459
 460#define SHIFT 1
 461#include "shift_helper_template.h"
 462#undef SHIFT
 463
 464#define SHIFT 2
 465#include "shift_helper_template.h"
 466#undef SHIFT
 467
 468#ifdef TARGET_X86_64
 469#define SHIFT 3
 470#include "shift_helper_template.h"
 471#undef SHIFT
 472#endif
 473
 474/* Test that BIT is enabled in CR4.  If not, raise an illegal opcode
 475   exception.  This reduces the requirements for rare CR4 bits being
 476   mapped into HFLAGS.  */
 477void helper_cr4_testbit(CPUX86State *env, uint32_t bit)
 478{
 479    if (unlikely((env->cr[4] & bit) == 0)) {
 480        raise_exception_ra(env, EXCP06_ILLOP, GETPC());
 481    }
 482}
 483