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19#if !defined (__CPU_PPC_H__)
20#define __CPU_PPC_H__
21
22#include "qemu-common.h"
23
24
25
26#if defined (TARGET_PPC64)
27
28#define TARGET_LONG_BITS 64
29#define TARGET_PAGE_BITS 12
30
31#define TARGET_IS_BIENDIAN 1
32
33
34
35
36#define TARGET_PHYS_ADDR_SPACE_BITS 62
37
38
39
40
41#ifdef TARGET_ABI32
42# define TARGET_VIRT_ADDR_SPACE_BITS 32
43#else
44# define TARGET_VIRT_ADDR_SPACE_BITS 64
45#endif
46
47#define TARGET_PAGE_BITS_64K 16
48#define TARGET_PAGE_BITS_16M 24
49
50#else
51
52#define TARGET_LONG_BITS 32
53
54#if defined(TARGET_PPCEMB)
55
56
57#if defined(CONFIG_USER_ONLY)
58
59
60
61#define TARGET_PAGE_BITS 12
62#else
63
64#define TARGET_PAGE_BITS 10
65#endif
66#else
67
68#define TARGET_PAGE_BITS 12
69#endif
70
71#define TARGET_PHYS_ADDR_SPACE_BITS 36
72#define TARGET_VIRT_ADDR_SPACE_BITS 32
73
74#endif
75
76#define CPUArchState struct CPUPPCState
77
78#include "exec/cpu-defs.h"
79
80#include "fpu/softfloat.h"
81
82#if defined (TARGET_PPC64)
83#define PPC_ELF_MACHINE EM_PPC64
84#else
85#define PPC_ELF_MACHINE EM_PPC
86#endif
87
88
89
90typedef enum powerpc_mmu_t powerpc_mmu_t;
91enum powerpc_mmu_t {
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93
94 POWERPC_MMU_32B = 0x00000001,
95
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103
104 POWERPC_MMU_REAL = 0x00000006,
105
106 POWERPC_MMU_MPC8xx = 0x00000007,
107
108 POWERPC_MMU_BOOKE = 0x00000008,
109
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111
112 POWERPC_MMU_601 = 0x0000000A,
113#if defined(TARGET_PPC64)
114#define POWERPC_MMU_64 0x00010000
115#define POWERPC_MMU_1TSEG 0x00020000
116#define POWERPC_MMU_AMR 0x00040000
117
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119
120 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
121
122 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
123 | POWERPC_MMU_AMR | 0x00000003,
124
125 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
126 | 0x00000003,
127
128 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
129 | POWERPC_MMU_AMR | 0x00000004,
130
131 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
132 | 0x00000004,
133#endif
134};
135
136
137
138typedef enum powerpc_excp_t powerpc_excp_t;
139enum powerpc_excp_t {
140 POWERPC_EXCP_UNKNOWN = 0,
141
142 POWERPC_EXCP_STD,
143
144 POWERPC_EXCP_40x,
145
146 POWERPC_EXCP_601,
147
148 POWERPC_EXCP_602,
149
150 POWERPC_EXCP_603,
151
152 POWERPC_EXCP_603E,
153
154 POWERPC_EXCP_G2,
155
156 POWERPC_EXCP_604,
157
158 POWERPC_EXCP_7x0,
159
160 POWERPC_EXCP_7x5,
161
162 POWERPC_EXCP_74xx,
163
164 POWERPC_EXCP_BOOKE,
165#if defined(TARGET_PPC64)
166
167 POWERPC_EXCP_970,
168
169 POWERPC_EXCP_POWER7,
170
171 POWERPC_EXCP_POWER8,
172#endif
173};
174
175
176
177enum {
178 POWERPC_EXCP_NONE = -1,
179
180 POWERPC_EXCP_CRITICAL = 0,
181 POWERPC_EXCP_MCHECK = 1,
182 POWERPC_EXCP_DSI = 2,
183 POWERPC_EXCP_ISI = 3,
184 POWERPC_EXCP_EXTERNAL = 4,
185 POWERPC_EXCP_ALIGN = 5,
186 POWERPC_EXCP_PROGRAM = 6,
187 POWERPC_EXCP_FPU = 7,
188 POWERPC_EXCP_SYSCALL = 8,
189 POWERPC_EXCP_APU = 9,
190 POWERPC_EXCP_DECR = 10,
191 POWERPC_EXCP_FIT = 11,
192 POWERPC_EXCP_WDT = 12,
193 POWERPC_EXCP_DTLB = 13,
194 POWERPC_EXCP_ITLB = 14,
195 POWERPC_EXCP_DEBUG = 15,
196
197 POWERPC_EXCP_SPEU = 32,
198 POWERPC_EXCP_EFPDI = 33,
199 POWERPC_EXCP_EFPRI = 34,
200 POWERPC_EXCP_EPERFM = 35,
201 POWERPC_EXCP_DOORI = 36,
202 POWERPC_EXCP_DOORCI = 37,
203 POWERPC_EXCP_GDOORI = 38,
204 POWERPC_EXCP_GDOORCI = 39,
205 POWERPC_EXCP_HYPPRIV = 41,
206
207
208 POWERPC_EXCP_RESET = 64,
209 POWERPC_EXCP_DSEG = 65,
210 POWERPC_EXCP_ISEG = 66,
211 POWERPC_EXCP_HDECR = 67,
212 POWERPC_EXCP_TRACE = 68,
213 POWERPC_EXCP_HDSI = 69,
214 POWERPC_EXCP_HISI = 70,
215 POWERPC_EXCP_HDSEG = 71,
216 POWERPC_EXCP_HISEG = 72,
217 POWERPC_EXCP_VPU = 73,
218
219 POWERPC_EXCP_PIT = 74,
220
221 POWERPC_EXCP_IO = 75,
222 POWERPC_EXCP_RUNM = 76,
223
224 POWERPC_EXCP_EMUL = 77,
225
226 POWERPC_EXCP_IFTLB = 78,
227 POWERPC_EXCP_DLTLB = 79,
228 POWERPC_EXCP_DSTLB = 80,
229
230 POWERPC_EXCP_FPA = 81,
231 POWERPC_EXCP_DABR = 82,
232 POWERPC_EXCP_IABR = 83,
233 POWERPC_EXCP_SMI = 84,
234 POWERPC_EXCP_PERFM = 85,
235
236 POWERPC_EXCP_THERM = 86,
237
238 POWERPC_EXCP_VPUA = 87,
239
240 POWERPC_EXCP_SOFTP = 88,
241 POWERPC_EXCP_MAINT = 89,
242
243 POWERPC_EXCP_MEXTBR = 90,
244 POWERPC_EXCP_NMEXTBR = 91,
245 POWERPC_EXCP_ITLBE = 92,
246 POWERPC_EXCP_DTLBE = 93,
247
248 POWERPC_EXCP_VSXU = 94,
249 POWERPC_EXCP_FU = 95,
250
251 POWERPC_EXCP_NB = 96,
252
253 POWERPC_EXCP_STOP = 0x200,
254 POWERPC_EXCP_BRANCH = 0x201,
255
256 POWERPC_EXCP_SYNC = 0x202,
257 POWERPC_EXCP_SYSCALL_USER = 0x203,
258 POWERPC_EXCP_STCX = 0x204
259};
260
261
262enum {
263
264 POWERPC_EXCP_ALIGN_FP = 0x01,
265 POWERPC_EXCP_ALIGN_LST = 0x02,
266 POWERPC_EXCP_ALIGN_LE = 0x03,
267 POWERPC_EXCP_ALIGN_PROT = 0x04,
268 POWERPC_EXCP_ALIGN_BAT = 0x05,
269 POWERPC_EXCP_ALIGN_CACHE = 0x06,
270
271
272 POWERPC_EXCP_FP = 0x10,
273 POWERPC_EXCP_FP_OX = 0x01,
274 POWERPC_EXCP_FP_UX = 0x02,
275 POWERPC_EXCP_FP_ZX = 0x03,
276 POWERPC_EXCP_FP_XX = 0x04,
277 POWERPC_EXCP_FP_VXSNAN = 0x05,
278 POWERPC_EXCP_FP_VXISI = 0x06,
279 POWERPC_EXCP_FP_VXIDI = 0x07,
280 POWERPC_EXCP_FP_VXZDZ = 0x08,
281 POWERPC_EXCP_FP_VXIMZ = 0x09,
282 POWERPC_EXCP_FP_VXVC = 0x0A,
283 POWERPC_EXCP_FP_VXSOFT = 0x0B,
284 POWERPC_EXCP_FP_VXSQRT = 0x0C,
285 POWERPC_EXCP_FP_VXCVI = 0x0D,
286
287 POWERPC_EXCP_INVAL = 0x20,
288 POWERPC_EXCP_INVAL_INVAL = 0x01,
289 POWERPC_EXCP_INVAL_LSWX = 0x02,
290 POWERPC_EXCP_INVAL_SPR = 0x03,
291 POWERPC_EXCP_INVAL_FP = 0x04,
292
293 POWERPC_EXCP_PRIV = 0x30,
294 POWERPC_EXCP_PRIV_OPC = 0x01,
295 POWERPC_EXCP_PRIV_REG = 0x02,
296
297 POWERPC_EXCP_TRAP = 0x40,
298};
299
300
301
302typedef enum powerpc_input_t powerpc_input_t;
303enum powerpc_input_t {
304 PPC_FLAGS_INPUT_UNKNOWN = 0,
305
306 PPC_FLAGS_INPUT_6xx,
307
308 PPC_FLAGS_INPUT_BookE,
309
310 PPC_FLAGS_INPUT_405,
311
312 PPC_FLAGS_INPUT_970,
313
314 PPC_FLAGS_INPUT_POWER7,
315
316 PPC_FLAGS_INPUT_401,
317
318 PPC_FLAGS_INPUT_RCPU,
319};
320
321#define PPC_INPUT(env) (env->bus_model)
322
323
324typedef struct opc_handler_t opc_handler_t;
325
326
327
328typedef struct CPUPPCState CPUPPCState;
329typedef struct DisasContext DisasContext;
330typedef struct ppc_tb_t ppc_tb_t;
331typedef struct ppc_spr_t ppc_spr_t;
332typedef struct ppc_dcr_t ppc_dcr_t;
333typedef union ppc_avr_t ppc_avr_t;
334typedef union ppc_tlb_t ppc_tlb_t;
335
336
337struct ppc_spr_t {
338 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
339 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
340#if !defined(CONFIG_USER_ONLY)
341 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
342 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
343 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
344 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
345#endif
346 const char *name;
347 target_ulong default_value;
348#ifdef CONFIG_KVM
349
350
351
352 uint64_t one_reg_id;
353#endif
354};
355
356
357union ppc_avr_t {
358 float32 f[4];
359 uint8_t u8[16];
360 uint16_t u16[8];
361 uint32_t u32[4];
362 int8_t s8[16];
363 int16_t s16[8];
364 int32_t s32[4];
365 uint64_t u64[2];
366 int64_t s64[2];
367#ifdef CONFIG_INT128
368 __uint128_t u128;
369#endif
370};
371
372#if !defined(CONFIG_USER_ONLY)
373
374typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
375struct ppc6xx_tlb_t {
376 target_ulong pte0;
377 target_ulong pte1;
378 target_ulong EPN;
379};
380
381typedef struct ppcemb_tlb_t ppcemb_tlb_t;
382struct ppcemb_tlb_t {
383 uint64_t RPN;
384 target_ulong EPN;
385 target_ulong PID;
386 target_ulong size;
387 uint32_t prot;
388 uint32_t attr;
389};
390
391typedef struct ppcmas_tlb_t {
392 uint32_t mas8;
393 uint32_t mas1;
394 uint64_t mas2;
395 uint64_t mas7_3;
396} ppcmas_tlb_t;
397
398union ppc_tlb_t {
399 ppc6xx_tlb_t *tlb6;
400 ppcemb_tlb_t *tlbe;
401 ppcmas_tlb_t *tlbm;
402};
403
404
405#define TLB_NONE 0
406#define TLB_6XX 1
407#define TLB_EMB 2
408#define TLB_MAS 3
409#endif
410
411#define SDR_32_HTABORG 0xFFFF0000UL
412#define SDR_32_HTABMASK 0x000001FFUL
413
414#if defined(TARGET_PPC64)
415#define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
416#define SDR_64_HTABSIZE 0x000000000000001FULL
417#endif
418
419typedef struct ppc_slb_t ppc_slb_t;
420struct ppc_slb_t {
421 uint64_t esid;
422 uint64_t vsid;
423 const struct ppc_one_seg_page_size *sps;
424};
425
426#define MAX_SLB_ENTRIES 64
427#define SEGMENT_SHIFT_256M 28
428#define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
429
430#define SEGMENT_SHIFT_1T 40
431#define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
432
433
434
435
436#define MSR_SF 63
437#define MSR_TAG 62
438#define MSR_ISF 61
439#define MSR_SHV 60
440#define MSR_TS0 34
441#define MSR_TS1 33
442#define MSR_TM 32
443#define MSR_CM 31
444#define MSR_ICM 30
445#define MSR_THV 29
446#define MSR_GS 28
447#define MSR_UCLE 26
448#define MSR_VR 25
449#define MSR_SPE 25
450#define MSR_AP 23
451#define MSR_VSX 23
452#define MSR_SA 22
453#define MSR_KEY 19
454#define MSR_POW 18
455#define MSR_TGPR 17
456#define MSR_CE 17
457#define MSR_ILE 16
458#define MSR_EE 15
459#define MSR_PR 14
460#define MSR_FP 13
461#define MSR_ME 12
462#define MSR_FE0 11
463#define MSR_SE 10
464#define MSR_DWE 10
465#define MSR_UBLE 10
466#define MSR_BE 9
467#define MSR_DE 9
468#define MSR_FE1 8
469#define MSR_AL 7
470#define MSR_EP 6
471#define MSR_IR 5
472#define MSR_DR 4
473#define MSR_PE 3
474#define MSR_PX 2
475#define MSR_PMM 2
476#define MSR_RI 1
477#define MSR_LE 0
478
479
480#define LPCR_VPM0 (1ull << (63 - 0))
481#define LPCR_VPM1 (1ull << (63 - 1))
482#define LPCR_ISL (1ull << (63 - 2))
483#define LPCR_KBV (1ull << (63 - 3))
484#define LPCR_ILE (1ull << (63 - 38))
485#define LPCR_MER (1ull << (63 - 52))
486#define LPCR_LPES0 (1ull << (63 - 60))
487#define LPCR_LPES1 (1ull << (63 - 61))
488#define LPCR_AIL_SHIFT (63 - 40)
489#define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
490
491#define msr_sf ((env->msr >> MSR_SF) & 1)
492#define msr_isf ((env->msr >> MSR_ISF) & 1)
493#define msr_shv ((env->msr >> MSR_SHV) & 1)
494#define msr_cm ((env->msr >> MSR_CM) & 1)
495#define msr_icm ((env->msr >> MSR_ICM) & 1)
496#define msr_thv ((env->msr >> MSR_THV) & 1)
497#define msr_gs ((env->msr >> MSR_GS) & 1)
498#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
499#define msr_vr ((env->msr >> MSR_VR) & 1)
500#define msr_spe ((env->msr >> MSR_SPE) & 1)
501#define msr_ap ((env->msr >> MSR_AP) & 1)
502#define msr_vsx ((env->msr >> MSR_VSX) & 1)
503#define msr_sa ((env->msr >> MSR_SA) & 1)
504#define msr_key ((env->msr >> MSR_KEY) & 1)
505#define msr_pow ((env->msr >> MSR_POW) & 1)
506#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
507#define msr_ce ((env->msr >> MSR_CE) & 1)
508#define msr_ile ((env->msr >> MSR_ILE) & 1)
509#define msr_ee ((env->msr >> MSR_EE) & 1)
510#define msr_pr ((env->msr >> MSR_PR) & 1)
511#define msr_fp ((env->msr >> MSR_FP) & 1)
512#define msr_me ((env->msr >> MSR_ME) & 1)
513#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
514#define msr_se ((env->msr >> MSR_SE) & 1)
515#define msr_dwe ((env->msr >> MSR_DWE) & 1)
516#define msr_uble ((env->msr >> MSR_UBLE) & 1)
517#define msr_be ((env->msr >> MSR_BE) & 1)
518#define msr_de ((env->msr >> MSR_DE) & 1)
519#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
520#define msr_al ((env->msr >> MSR_AL) & 1)
521#define msr_ep ((env->msr >> MSR_EP) & 1)
522#define msr_ir ((env->msr >> MSR_IR) & 1)
523#define msr_dr ((env->msr >> MSR_DR) & 1)
524#define msr_pe ((env->msr >> MSR_PE) & 1)
525#define msr_px ((env->msr >> MSR_PX) & 1)
526#define msr_pmm ((env->msr >> MSR_PMM) & 1)
527#define msr_ri ((env->msr >> MSR_RI) & 1)
528#define msr_le ((env->msr >> MSR_LE) & 1)
529#define msr_ts ((env->msr >> MSR_TS1) & 3)
530#define msr_tm ((env->msr >> MSR_TM) & 1)
531
532
533#if defined(TARGET_PPC64)
534#define MSR_HVB (1ULL << MSR_SHV)
535#define msr_hv msr_shv
536#else
537#if defined(PPC_EMULATE_32BITS_HYPV)
538#define MSR_HVB (1ULL << MSR_THV)
539#define msr_hv msr_thv
540#else
541#define MSR_HVB (0ULL)
542#define msr_hv (0)
543#endif
544#endif
545
546
547#define FSCR_EBB (63 - 56)
548#define FSCR_TAR (63 - 55)
549
550#define FSCR_IC_MASK (0xFFULL)
551#define FSCR_IC_POS (63 - 7)
552#define FSCR_IC_DSCR_SPR3 2
553#define FSCR_IC_PMU 3
554#define FSCR_IC_BHRB 4
555#define FSCR_IC_TM 5
556#define FSCR_IC_EBB 7
557#define FSCR_IC_TAR 8
558
559
560#define ESR_PIL (1 << (63 - 36))
561#define ESR_PPR (1 << (63 - 37))
562#define ESR_PTR (1 << (63 - 38))
563#define ESR_FP (1 << (63 - 39))
564#define ESR_ST (1 << (63 - 40))
565#define ESR_AP (1 << (63 - 44))
566#define ESR_PUO (1 << (63 - 45))
567#define ESR_BO (1 << (63 - 46))
568#define ESR_PIE (1 << (63 - 47))
569#define ESR_DATA (1 << (63 - 53))
570#define ESR_TLBI (1 << (63 - 54))
571#define ESR_PT (1 << (63 - 55))
572#define ESR_SPV (1 << (63 - 56))
573#define ESR_EPID (1 << (63 - 57))
574#define ESR_VLEMI (1 << (63 - 58))
575#define ESR_MIF (1 << (63 - 62))
576
577
578#define TEXASR_FAILURE_PERSISTENT (63 - 7)
579#define TEXASR_DISALLOWED (63 - 8)
580#define TEXASR_NESTING_OVERFLOW (63 - 9)
581#define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
582#define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
583#define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
584#define TEXASR_TRANSACTION_CONFLICT (63 - 13)
585#define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
586#define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
587#define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
588#define TEXASR_ABORT (63 - 31)
589#define TEXASR_SUSPENDED (63 - 32)
590#define TEXASR_PRIVILEGE_HV (63 - 34)
591#define TEXASR_PRIVILEGE_PR (63 - 35)
592#define TEXASR_FAILURE_SUMMARY (63 - 36)
593#define TEXASR_TFIAR_EXACT (63 - 37)
594#define TEXASR_ROT (63 - 38)
595#define TEXASR_TRANSACTION_LEVEL (63 - 52)
596
597enum {
598 POWERPC_FLAG_NONE = 0x00000000,
599
600 POWERPC_FLAG_SPE = 0x00000001,
601 POWERPC_FLAG_VRE = 0x00000002,
602
603 POWERPC_FLAG_TGPR = 0x00000004,
604 POWERPC_FLAG_CE = 0x00000008,
605
606 POWERPC_FLAG_SE = 0x00000010,
607 POWERPC_FLAG_DWE = 0x00000020,
608 POWERPC_FLAG_UBLE = 0x00000040,
609
610 POWERPC_FLAG_BE = 0x00000080,
611 POWERPC_FLAG_DE = 0x00000100,
612
613 POWERPC_FLAG_PX = 0x00000200,
614 POWERPC_FLAG_PMM = 0x00000400,
615
616
617 POWERPC_FLAG_RTC_CLK = 0x00010000,
618 POWERPC_FLAG_BUS_CLK = 0x00020000,
619
620 POWERPC_FLAG_CFAR = 0x00040000,
621
622 POWERPC_FLAG_VSX = 0x00080000,
623
624 POWERPC_FLAG_TM = 0x00100000,
625};
626
627
628
629#define FPSCR_FX 31
630#define FPSCR_FEX 30
631#define FPSCR_VX 29
632#define FPSCR_OX 28
633#define FPSCR_UX 27
634#define FPSCR_ZX 26
635#define FPSCR_XX 25
636#define FPSCR_VXSNAN 24
637#define FPSCR_VXISI 23
638#define FPSCR_VXIDI 22
639#define FPSCR_VXZDZ 21
640#define FPSCR_VXIMZ 20
641#define FPSCR_VXVC 19
642#define FPSCR_FR 18
643#define FPSCR_FI 17
644#define FPSCR_C 16
645#define FPSCR_FL 15
646#define FPSCR_FG 14
647#define FPSCR_FE 13
648#define FPSCR_FU 12
649#define FPSCR_FPCC 12
650#define FPSCR_FPRF 12
651#define FPSCR_VXSOFT 10
652#define FPSCR_VXSQRT 9
653#define FPSCR_VXCVI 8
654#define FPSCR_VE 7
655#define FPSCR_OE 6
656#define FPSCR_UE 5
657#define FPSCR_ZE 4
658#define FPSCR_XE 3
659#define FPSCR_NI 2
660#define FPSCR_RN1 1
661#define FPSCR_RN 0
662#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
663#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
664#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
665#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
666#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
667#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
668#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
669#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
670#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
671#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
672#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
673#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
674#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
675#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
676#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
677#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
678#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
679#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
680#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
681#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
682#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
683#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
684#define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
685
686#define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
687 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
688 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
689 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
690 (1 << FPSCR_VXCVI)))
691
692#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
693
694#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
695 0x1F)
696
697#define FP_FX (1ull << FPSCR_FX)
698#define FP_FEX (1ull << FPSCR_FEX)
699#define FP_VX (1ull << FPSCR_VX)
700#define FP_OX (1ull << FPSCR_OX)
701#define FP_UX (1ull << FPSCR_UX)
702#define FP_ZX (1ull << FPSCR_ZX)
703#define FP_XX (1ull << FPSCR_XX)
704#define FP_VXSNAN (1ull << FPSCR_VXSNAN)
705#define FP_VXISI (1ull << FPSCR_VXISI)
706#define FP_VXIDI (1ull << FPSCR_VXIDI)
707#define FP_VXZDZ (1ull << FPSCR_VXZDZ)
708#define FP_VXIMZ (1ull << FPSCR_VXIMZ)
709#define FP_VXVC (1ull << FPSCR_VXVC)
710#define FP_FR (1ull << FSPCR_FR)
711#define FP_FI (1ull << FPSCR_FI)
712#define FP_C (1ull << FPSCR_C)
713#define FP_FL (1ull << FPSCR_FL)
714#define FP_FG (1ull << FPSCR_FG)
715#define FP_FE (1ull << FPSCR_FE)
716#define FP_FU (1ull << FPSCR_FU)
717#define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
718#define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
719#define FP_VXSOFT (1ull << FPSCR_VXSOFT)
720#define FP_VXSQRT (1ull << FPSCR_VXSQRT)
721#define FP_VXCVI (1ull << FPSCR_VXCVI)
722#define FP_VE (1ull << FPSCR_VE)
723#define FP_OE (1ull << FPSCR_OE)
724#define FP_UE (1ull << FPSCR_UE)
725#define FP_ZE (1ull << FPSCR_ZE)
726#define FP_XE (1ull << FPSCR_XE)
727#define FP_NI (1ull << FPSCR_NI)
728#define FP_RN1 (1ull << FPSCR_RN1)
729#define FP_RN (1ull << FPSCR_RN)
730
731
732#define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
733 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
734 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
735 FP_VXSQRT | FP_VXCVI)
736
737
738
739#define VSCR_NJ 16
740#define VSCR_SAT 0
741#define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
742#define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
743
744
745
746
747#define MAS0_NV_SHIFT 0
748#define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
749
750#define MAS0_WQ_SHIFT 12
751#define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
752
753#define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
754
755#define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
756
757#define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
758
759#define MAS0_HES_SHIFT 14
760#define MAS0_HES (1 << MAS0_HES_SHIFT)
761
762#define MAS0_ESEL_SHIFT 16
763#define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
764
765#define MAS0_TLBSEL_SHIFT 28
766#define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
767#define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
768#define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
769#define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
770#define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
771
772#define MAS0_ATSEL_SHIFT 31
773#define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
774#define MAS0_ATSEL_TLB 0
775#define MAS0_ATSEL_LRAT MAS0_ATSEL
776
777#define MAS1_TSIZE_SHIFT 7
778#define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
779
780#define MAS1_TS_SHIFT 12
781#define MAS1_TS (1 << MAS1_TS_SHIFT)
782
783#define MAS1_IND_SHIFT 13
784#define MAS1_IND (1 << MAS1_IND_SHIFT)
785
786#define MAS1_TID_SHIFT 16
787#define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
788
789#define MAS1_IPROT_SHIFT 30
790#define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
791
792#define MAS1_VALID_SHIFT 31
793#define MAS1_VALID 0x80000000
794
795#define MAS2_EPN_SHIFT 12
796#define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
797
798#define MAS2_ACM_SHIFT 6
799#define MAS2_ACM (1 << MAS2_ACM_SHIFT)
800
801#define MAS2_VLE_SHIFT 5
802#define MAS2_VLE (1 << MAS2_VLE_SHIFT)
803
804#define MAS2_W_SHIFT 4
805#define MAS2_W (1 << MAS2_W_SHIFT)
806
807#define MAS2_I_SHIFT 3
808#define MAS2_I (1 << MAS2_I_SHIFT)
809
810#define MAS2_M_SHIFT 2
811#define MAS2_M (1 << MAS2_M_SHIFT)
812
813#define MAS2_G_SHIFT 1
814#define MAS2_G (1 << MAS2_G_SHIFT)
815
816#define MAS2_E_SHIFT 0
817#define MAS2_E (1 << MAS2_E_SHIFT)
818
819#define MAS3_RPN_SHIFT 12
820#define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
821
822#define MAS3_U0 0x00000200
823#define MAS3_U1 0x00000100
824#define MAS3_U2 0x00000080
825#define MAS3_U3 0x00000040
826#define MAS3_UX 0x00000020
827#define MAS3_SX 0x00000010
828#define MAS3_UW 0x00000008
829#define MAS3_SW 0x00000004
830#define MAS3_UR 0x00000002
831#define MAS3_SR 0x00000001
832#define MAS3_SPSIZE_SHIFT 1
833#define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
834
835#define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
836#define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
837#define MAS4_TIDSELD_MASK 0x00030000
838#define MAS4_TIDSELD_PID0 0x00000000
839#define MAS4_TIDSELD_PID1 0x00010000
840#define MAS4_TIDSELD_PID2 0x00020000
841#define MAS4_TIDSELD_PIDZ 0x00030000
842#define MAS4_INDD 0x00008000
843#define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
844#define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
845#define MAS4_ACMD 0x00000040
846#define MAS4_VLED 0x00000020
847#define MAS4_WD 0x00000010
848#define MAS4_ID 0x00000008
849#define MAS4_MD 0x00000004
850#define MAS4_GD 0x00000002
851#define MAS4_ED 0x00000001
852#define MAS4_WIMGED_MASK 0x0000001f
853#define MAS4_WIMGED_SHIFT 0
854
855#define MAS5_SGS 0x80000000
856#define MAS5_SLPID_MASK 0x00000fff
857
858#define MAS6_SPID0 0x3fff0000
859#define MAS6_SPID1 0x00007ffe
860#define MAS6_ISIZE(x) MAS1_TSIZE(x)
861#define MAS6_SAS 0x00000001
862#define MAS6_SPID MAS6_SPID0
863#define MAS6_SIND 0x00000002
864#define MAS6_SIND_SHIFT 1
865#define MAS6_SPID_MASK 0x3fff0000
866#define MAS6_SPID_SHIFT 16
867#define MAS6_ISIZE_MASK 0x00000f80
868#define MAS6_ISIZE_SHIFT 7
869
870#define MAS7_RPN 0xffffffff
871
872#define MAS8_TGS 0x80000000
873#define MAS8_VF 0x40000000
874#define MAS8_TLBPID 0x00000fff
875
876
877#define MMUCFG_MAVN 0x00000003
878#define MMUCFG_MAVN_V1 0x00000000
879#define MMUCFG_MAVN_V2 0x00000001
880#define MMUCFG_NTLBS 0x0000000c
881#define MMUCFG_PIDSIZE 0x000007c0
882#define MMUCFG_TWC 0x00008000
883#define MMUCFG_LRAT 0x00010000
884#define MMUCFG_RASIZE 0x00fe0000
885#define MMUCFG_LPIDSIZE 0x0f000000
886
887
888#define MMUCSR0_TLB1FI 0x00000002
889#define MMUCSR0_TLB0FI 0x00000004
890#define MMUCSR0_TLB2FI 0x00000040
891#define MMUCSR0_TLB3FI 0x00000020
892#define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
893 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
894#define MMUCSR0_TLB0PS 0x00000780
895#define MMUCSR0_TLB1PS 0x00007800
896#define MMUCSR0_TLB2PS 0x00078000
897#define MMUCSR0_TLB3PS 0x00780000
898
899
900#define TLBnCFG_N_ENTRY 0x00000fff
901#define TLBnCFG_HES 0x00002000
902#define TLBnCFG_AVAIL 0x00004000
903#define TLBnCFG_IPROT 0x00008000
904#define TLBnCFG_GTWE 0x00010000
905#define TLBnCFG_IND 0x00020000
906#define TLBnCFG_PT 0x00040000
907#define TLBnCFG_MINSIZE 0x00f00000
908#define TLBnCFG_MINSIZE_SHIFT 20
909#define TLBnCFG_MAXSIZE 0x000f0000
910#define TLBnCFG_MAXSIZE_SHIFT 16
911#define TLBnCFG_ASSOC 0xff000000
912#define TLBnCFG_ASSOC_SHIFT 24
913
914
915#define TLBnPS_4K 0x00000004
916#define TLBnPS_8K 0x00000008
917#define TLBnPS_16K 0x00000010
918#define TLBnPS_32K 0x00000020
919#define TLBnPS_64K 0x00000040
920#define TLBnPS_128K 0x00000080
921#define TLBnPS_256K 0x00000100
922#define TLBnPS_512K 0x00000200
923#define TLBnPS_1M 0x00000400
924#define TLBnPS_2M 0x00000800
925#define TLBnPS_4M 0x00001000
926#define TLBnPS_8M 0x00002000
927#define TLBnPS_16M 0x00004000
928#define TLBnPS_32M 0x00008000
929#define TLBnPS_64M 0x00010000
930#define TLBnPS_128M 0x00020000
931#define TLBnPS_256M 0x00040000
932#define TLBnPS_512M 0x00080000
933#define TLBnPS_1G 0x00100000
934#define TLBnPS_2G 0x00200000
935#define TLBnPS_4G 0x00400000
936#define TLBnPS_8G 0x00800000
937#define TLBnPS_16G 0x01000000
938#define TLBnPS_32G 0x02000000
939#define TLBnPS_64G 0x04000000
940#define TLBnPS_128G 0x08000000
941#define TLBnPS_256G 0x10000000
942
943
944#define TLBILX_T_ALL 0
945#define TLBILX_T_TID 1
946#define TLBILX_T_FULLMATCH 3
947#define TLBILX_T_CLASS0 4
948#define TLBILX_T_CLASS1 5
949#define TLBILX_T_CLASS2 6
950#define TLBILX_T_CLASS3 7
951
952
953
954#define BOOKE206_FLUSH_TLB0 (1 << 0)
955#define BOOKE206_FLUSH_TLB1 (1 << 1)
956#define BOOKE206_FLUSH_TLB2 (1 << 2)
957#define BOOKE206_FLUSH_TLB3 (1 << 3)
958
959
960#define BOOKE206_MAX_TLBN 4
961
962
963
964
965#define DBELL_TYPE_SHIFT 27
966#define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
967#define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
968#define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
969#define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
970#define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
971#define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
972
973#define DBELL_BRDCAST (1 << 26)
974#define DBELL_LPIDTAG_SHIFT 14
975#define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
976#define DBELL_PIRTAG_MASK 0x3fff
977
978
979
980
981
982
983#define PPC_PAGE_SIZES_MAX_SZ 8
984
985struct ppc_one_page_size {
986 uint32_t page_shift;
987 uint32_t pte_enc;
988};
989
990struct ppc_one_seg_page_size {
991 uint32_t page_shift;
992 uint32_t slb_enc;
993 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
994};
995
996struct ppc_segment_page_sizes {
997 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
998};
999
1000
1001
1002
1003#define NB_MMU_MODES 3
1004
1005#define PPC_CPU_OPCODES_LEN 0x40
1006#define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1007
1008struct CPUPPCState {
1009
1010
1011
1012
1013 target_ulong gpr[32];
1014
1015 target_ulong gprh[32];
1016
1017 target_ulong lr;
1018
1019 target_ulong ctr;
1020
1021 uint32_t crf[8];
1022#if defined(TARGET_PPC64)
1023
1024 target_ulong cfar;
1025#endif
1026
1027 target_ulong xer;
1028 target_ulong so;
1029 target_ulong ov;
1030 target_ulong ca;
1031
1032 target_ulong reserve_addr;
1033
1034 target_ulong reserve_val;
1035 target_ulong reserve_val2;
1036
1037 target_ulong reserve_ea;
1038
1039 target_ulong reserve_info;
1040
1041
1042
1043 target_ulong msr;
1044
1045 target_ulong tgpr[4];
1046
1047
1048 float_status fp_status;
1049
1050 float64 fpr[32];
1051
1052 target_ulong fpscr;
1053
1054
1055 target_ulong nip;
1056
1057 int access_type;
1058
1059
1060 CPU_COMMON
1061
1062
1063#if !defined(CONFIG_USER_ONLY)
1064#if defined(TARGET_PPC64)
1065
1066 ppc_slb_t slb[MAX_SLB_ENTRIES];
1067 int32_t slb_nr;
1068#endif
1069
1070 hwaddr htab_base;
1071
1072 hwaddr htab_mask;
1073 target_ulong sr[32];
1074
1075 uint8_t *external_htab;
1076
1077 uint32_t nb_BATs;
1078 target_ulong DBAT[2][8];
1079 target_ulong IBAT[2][8];
1080
1081 int32_t nb_tlb;
1082 int tlb_per_way;
1083 int nb_ways;
1084 int last_way;
1085 int id_tlbs;
1086 int nb_pids;
1087 int tlb_type;
1088 ppc_tlb_t tlb;
1089
1090 target_ulong pb[4];
1091 bool tlb_dirty;
1092 bool kvm_sw_tlb;
1093#endif
1094
1095
1096
1097 target_ulong spr[1024];
1098 ppc_spr_t spr_cb[1024];
1099
1100 ppc_avr_t avr[32];
1101 uint32_t vscr;
1102
1103 uint64_t vsr[32];
1104
1105 uint64_t spe_acc;
1106 uint32_t spe_fscr;
1107
1108
1109 float_status vec_status;
1110
1111
1112
1113 ppc_tb_t *tb_env;
1114
1115 ppc_dcr_t *dcr_env;
1116
1117 int dcache_line_size;
1118 int icache_line_size;
1119
1120
1121
1122 target_ulong msr_mask;
1123 powerpc_mmu_t mmu_model;
1124 powerpc_excp_t excp_model;
1125 powerpc_input_t bus_model;
1126 int bfd_mach;
1127 uint32_t flags;
1128 uint64_t insns_flags;
1129 uint64_t insns_flags2;
1130#if defined(TARGET_PPC64)
1131 struct ppc_segment_page_sizes sps;
1132 bool ci_large_pages;
1133#endif
1134
1135#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1136 uint64_t vpa_addr;
1137 uint64_t slb_shadow_addr, slb_shadow_size;
1138 uint64_t dtl_addr, dtl_size;
1139#endif
1140
1141 int error_code;
1142 uint32_t pending_interrupts;
1143#if !defined(CONFIG_USER_ONLY)
1144
1145
1146
1147 uint32_t irq_input_state;
1148 void **irq_inputs;
1149
1150 target_ulong excp_vectors[POWERPC_EXCP_NB];
1151 target_ulong excp_prefix;
1152 target_ulong ivor_mask;
1153 target_ulong ivpr_mask;
1154 target_ulong hreset_vector;
1155 hwaddr mpic_iack;
1156
1157 bool mpic_proxy;
1158#endif
1159
1160
1161
1162 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1163
1164
1165 target_ulong hflags;
1166 target_ulong hflags_nmsr;
1167 int mmu_idx;
1168
1169
1170 int (*check_pow)(CPUPPCState *env);
1171
1172#if !defined(CONFIG_USER_ONLY)
1173 void *load_info;
1174#endif
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184 uint8_t fit_period[4];
1185 uint8_t wdt_period[4];
1186
1187
1188 target_ulong tm_gpr[32];
1189 ppc_avr_t tm_vsr[64];
1190 uint64_t tm_cr;
1191 uint64_t tm_lr;
1192 uint64_t tm_ctr;
1193 uint64_t tm_fpscr;
1194 uint64_t tm_amr;
1195 uint64_t tm_ppr;
1196 uint64_t tm_vrsave;
1197 uint32_t tm_vscr;
1198 uint64_t tm_dscr;
1199 uint64_t tm_tar;
1200};
1201
1202#define SET_FIT_PERIOD(a_, b_, c_, d_) \
1203do { \
1204 env->fit_period[0] = (a_); \
1205 env->fit_period[1] = (b_); \
1206 env->fit_period[2] = (c_); \
1207 env->fit_period[3] = (d_); \
1208 } while (0)
1209
1210#define SET_WDT_PERIOD(a_, b_, c_, d_) \
1211do { \
1212 env->wdt_period[0] = (a_); \
1213 env->wdt_period[1] = (b_); \
1214 env->wdt_period[2] = (c_); \
1215 env->wdt_period[3] = (d_); \
1216 } while (0)
1217
1218#include "cpu-qom.h"
1219
1220
1221PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1222void ppc_translate_init(void);
1223void gen_update_current_nip(void *opaque);
1224int cpu_ppc_exec (CPUState *s);
1225
1226
1227
1228int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1229 void *puc);
1230#if defined(CONFIG_USER_ONLY)
1231int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1232 int mmu_idx);
1233#endif
1234
1235#if !defined(CONFIG_USER_ONLY)
1236void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1237#endif
1238void ppc_store_msr (CPUPPCState *env, target_ulong value);
1239
1240void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1241int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1242void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
1243
1244
1245#ifndef NO_CPU_IO_DEFS
1246uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1247uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1248void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1249void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1250uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1251uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1252void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1253void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1254bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1255uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1256void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1257uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1258void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1259uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1260uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1261uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1262#if !defined(CONFIG_USER_ONLY)
1263void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1264void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1265target_ulong load_40x_pit (CPUPPCState *env);
1266void store_40x_pit (CPUPPCState *env, target_ulong val);
1267void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1268void store_40x_sler (CPUPPCState *env, uint32_t val);
1269void store_booke_tcr (CPUPPCState *env, target_ulong val);
1270void store_booke_tsr (CPUPPCState *env, target_ulong val);
1271void ppc_tlb_invalidate_all (CPUPPCState *env);
1272void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1273void cpu_ppc_set_papr(PowerPCCPU *cpu);
1274#endif
1275#endif
1276
1277void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1278
1279static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1280{
1281 uint64_t gprv;
1282
1283 gprv = env->gpr[gprn];
1284 if (env->flags & POWERPC_FLAG_SPE) {
1285
1286
1287
1288 gprv &= 0xFFFFFFFFULL;
1289 gprv |= (uint64_t)env->gprh[gprn] << 32;
1290 }
1291
1292 return gprv;
1293}
1294
1295
1296int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1297int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1298
1299#define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1300
1301#define cpu_exec cpu_ppc_exec
1302#define cpu_signal_handler cpu_ppc_signal_handler
1303#define cpu_list ppc_cpu_list
1304
1305
1306#define MMU_MODE0_SUFFIX _user
1307#define MMU_MODE1_SUFFIX _kernel
1308#define MMU_MODE2_SUFFIX _hypv
1309#define MMU_USER_IDX 0
1310static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1311{
1312 return env->mmu_idx;
1313}
1314
1315#include "exec/cpu-all.h"
1316
1317
1318
1319#define CRF_LT 3
1320#define CRF_GT 2
1321#define CRF_EQ 1
1322#define CRF_SO 0
1323#define CRF_CH (1 << CRF_LT)
1324#define CRF_CL (1 << CRF_GT)
1325#define CRF_CH_OR_CL (1 << CRF_EQ)
1326#define CRF_CH_AND_CL (1 << CRF_SO)
1327
1328
1329#define XER_SO 31
1330#define XER_OV 30
1331#define XER_CA 29
1332#define XER_CMP 8
1333#define XER_BC 0
1334#define xer_so (env->so)
1335#define xer_ov (env->ov)
1336#define xer_ca (env->ca)
1337#define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1338#define xer_bc ((env->xer >> XER_BC) & 0x7F)
1339
1340
1341#define SPR_MQ (0x000)
1342#define SPR_XER (0x001)
1343#define SPR_601_VRTCU (0x004)
1344#define SPR_601_VRTCL (0x005)
1345#define SPR_601_UDECR (0x006)
1346#define SPR_LR (0x008)
1347#define SPR_CTR (0x009)
1348#define SPR_UAMR (0x00C)
1349#define SPR_DSCR (0x011)
1350#define SPR_DSISR (0x012)
1351#define SPR_DAR (0x013)
1352#define SPR_601_RTCU (0x014)
1353#define SPR_601_RTCL (0x015)
1354#define SPR_DECR (0x016)
1355#define SPR_SDR1 (0x019)
1356#define SPR_SRR0 (0x01A)
1357#define SPR_SRR1 (0x01B)
1358#define SPR_CFAR (0x01C)
1359#define SPR_AMR (0x01D)
1360#define SPR_ACOP (0x01F)
1361#define SPR_BOOKE_PID (0x030)
1362#define SPR_BOOKS_PID (0x030)
1363#define SPR_BOOKE_DECAR (0x036)
1364#define SPR_BOOKE_CSRR0 (0x03A)
1365#define SPR_BOOKE_CSRR1 (0x03B)
1366#define SPR_BOOKE_DEAR (0x03D)
1367#define SPR_IAMR (0x03D)
1368#define SPR_BOOKE_ESR (0x03E)
1369#define SPR_BOOKE_IVPR (0x03F)
1370#define SPR_MPC_EIE (0x050)
1371#define SPR_MPC_EID (0x051)
1372#define SPR_MPC_NRI (0x052)
1373#define SPR_TFHAR (0x080)
1374#define SPR_TFIAR (0x081)
1375#define SPR_TEXASR (0x082)
1376#define SPR_TEXASRU (0x083)
1377#define SPR_UCTRL (0x088)
1378#define SPR_MPC_CMPA (0x090)
1379#define SPR_MPC_CMPB (0x091)
1380#define SPR_MPC_CMPC (0x092)
1381#define SPR_MPC_CMPD (0x093)
1382#define SPR_MPC_ECR (0x094)
1383#define SPR_MPC_DER (0x095)
1384#define SPR_MPC_COUNTA (0x096)
1385#define SPR_MPC_COUNTB (0x097)
1386#define SPR_CTRL (0x098)
1387#define SPR_MPC_CMPE (0x098)
1388#define SPR_MPC_CMPF (0x099)
1389#define SPR_FSCR (0x099)
1390#define SPR_MPC_CMPG (0x09A)
1391#define SPR_MPC_CMPH (0x09B)
1392#define SPR_MPC_LCTRL1 (0x09C)
1393#define SPR_MPC_LCTRL2 (0x09D)
1394#define SPR_UAMOR (0x09D)
1395#define SPR_MPC_ICTRL (0x09E)
1396#define SPR_MPC_BAR (0x09F)
1397#define SPR_PSPB (0x09F)
1398#define SPR_DAWR (0x0B4)
1399#define SPR_RPR (0x0BA)
1400#define SPR_CIABR (0x0BB)
1401#define SPR_DAWRX (0x0BC)
1402#define SPR_HFSCR (0x0BE)
1403#define SPR_VRSAVE (0x100)
1404#define SPR_USPRG0 (0x100)
1405#define SPR_USPRG1 (0x101)
1406#define SPR_USPRG2 (0x102)
1407#define SPR_USPRG3 (0x103)
1408#define SPR_USPRG4 (0x104)
1409#define SPR_USPRG5 (0x105)
1410#define SPR_USPRG6 (0x106)
1411#define SPR_USPRG7 (0x107)
1412#define SPR_VTBL (0x10C)
1413#define SPR_VTBU (0x10D)
1414#define SPR_SPRG0 (0x110)
1415#define SPR_SPRG1 (0x111)
1416#define SPR_SPRG2 (0x112)
1417#define SPR_SPRG3 (0x113)
1418#define SPR_SPRG4 (0x114)
1419#define SPR_SCOMC (0x114)
1420#define SPR_SPRG5 (0x115)
1421#define SPR_SCOMD (0x115)
1422#define SPR_SPRG6 (0x116)
1423#define SPR_SPRG7 (0x117)
1424#define SPR_ASR (0x118)
1425#define SPR_EAR (0x11A)
1426#define SPR_TBL (0x11C)
1427#define SPR_TBU (0x11D)
1428#define SPR_TBU40 (0x11E)
1429#define SPR_SVR (0x11E)
1430#define SPR_BOOKE_PIR (0x11E)
1431#define SPR_PVR (0x11F)
1432#define SPR_HSPRG0 (0x130)
1433#define SPR_BOOKE_DBSR (0x130)
1434#define SPR_HSPRG1 (0x131)
1435#define SPR_HDSISR (0x132)
1436#define SPR_HDAR (0x133)
1437#define SPR_BOOKE_EPCR (0x133)
1438#define SPR_SPURR (0x134)
1439#define SPR_BOOKE_DBCR0 (0x134)
1440#define SPR_IBCR (0x135)
1441#define SPR_PURR (0x135)
1442#define SPR_BOOKE_DBCR1 (0x135)
1443#define SPR_DBCR (0x136)
1444#define SPR_HDEC (0x136)
1445#define SPR_BOOKE_DBCR2 (0x136)
1446#define SPR_HIOR (0x137)
1447#define SPR_MBAR (0x137)
1448#define SPR_RMOR (0x138)
1449#define SPR_BOOKE_IAC1 (0x138)
1450#define SPR_HRMOR (0x139)
1451#define SPR_BOOKE_IAC2 (0x139)
1452#define SPR_HSRR0 (0x13A)
1453#define SPR_BOOKE_IAC3 (0x13A)
1454#define SPR_HSRR1 (0x13B)
1455#define SPR_BOOKE_IAC4 (0x13B)
1456#define SPR_BOOKE_DAC1 (0x13C)
1457#define SPR_MMCRH (0x13C)
1458#define SPR_DABR2 (0x13D)
1459#define SPR_BOOKE_DAC2 (0x13D)
1460#define SPR_TFMR (0x13D)
1461#define SPR_BOOKE_DVC1 (0x13E)
1462#define SPR_LPCR (0x13E)
1463#define SPR_BOOKE_DVC2 (0x13F)
1464#define SPR_LPIDR (0x13F)
1465#define SPR_BOOKE_TSR (0x150)
1466#define SPR_HMER (0x150)
1467#define SPR_HMEER (0x151)
1468#define SPR_PCR (0x152)
1469#define SPR_BOOKE_LPIDR (0x152)
1470#define SPR_BOOKE_TCR (0x154)
1471#define SPR_BOOKE_TLB0PS (0x158)
1472#define SPR_BOOKE_TLB1PS (0x159)
1473#define SPR_BOOKE_TLB2PS (0x15A)
1474#define SPR_BOOKE_TLB3PS (0x15B)
1475#define SPR_AMOR (0x15D)
1476#define SPR_BOOKE_MAS7_MAS3 (0x174)
1477#define SPR_BOOKE_IVOR0 (0x190)
1478#define SPR_BOOKE_IVOR1 (0x191)
1479#define SPR_BOOKE_IVOR2 (0x192)
1480#define SPR_BOOKE_IVOR3 (0x193)
1481#define SPR_BOOKE_IVOR4 (0x194)
1482#define SPR_BOOKE_IVOR5 (0x195)
1483#define SPR_BOOKE_IVOR6 (0x196)
1484#define SPR_BOOKE_IVOR7 (0x197)
1485#define SPR_BOOKE_IVOR8 (0x198)
1486#define SPR_BOOKE_IVOR9 (0x199)
1487#define SPR_BOOKE_IVOR10 (0x19A)
1488#define SPR_BOOKE_IVOR11 (0x19B)
1489#define SPR_BOOKE_IVOR12 (0x19C)
1490#define SPR_BOOKE_IVOR13 (0x19D)
1491#define SPR_BOOKE_IVOR14 (0x19E)
1492#define SPR_BOOKE_IVOR15 (0x19F)
1493#define SPR_BOOKE_IVOR38 (0x1B0)
1494#define SPR_BOOKE_IVOR39 (0x1B1)
1495#define SPR_BOOKE_IVOR40 (0x1B2)
1496#define SPR_BOOKE_IVOR41 (0x1B3)
1497#define SPR_BOOKE_IVOR42 (0x1B4)
1498#define SPR_BOOKE_GIVOR2 (0x1B8)
1499#define SPR_BOOKE_GIVOR3 (0x1B9)
1500#define SPR_BOOKE_GIVOR4 (0x1BA)
1501#define SPR_BOOKE_GIVOR8 (0x1BB)
1502#define SPR_BOOKE_GIVOR13 (0x1BC)
1503#define SPR_BOOKE_GIVOR14 (0x1BD)
1504#define SPR_TIR (0x1BE)
1505#define SPR_BOOKE_SPEFSCR (0x200)
1506#define SPR_Exxx_BBEAR (0x201)
1507#define SPR_Exxx_BBTAR (0x202)
1508#define SPR_Exxx_L1CFG0 (0x203)
1509#define SPR_Exxx_L1CFG1 (0x204)
1510#define SPR_Exxx_NPIDR (0x205)
1511#define SPR_ATBL (0x20E)
1512#define SPR_ATBU (0x20F)
1513#define SPR_IBAT0U (0x210)
1514#define SPR_BOOKE_IVOR32 (0x210)
1515#define SPR_RCPU_MI_GRA (0x210)
1516#define SPR_IBAT0L (0x211)
1517#define SPR_BOOKE_IVOR33 (0x211)
1518#define SPR_IBAT1U (0x212)
1519#define SPR_BOOKE_IVOR34 (0x212)
1520#define SPR_IBAT1L (0x213)
1521#define SPR_BOOKE_IVOR35 (0x213)
1522#define SPR_IBAT2U (0x214)
1523#define SPR_BOOKE_IVOR36 (0x214)
1524#define SPR_IBAT2L (0x215)
1525#define SPR_BOOKE_IVOR37 (0x215)
1526#define SPR_IBAT3U (0x216)
1527#define SPR_IBAT3L (0x217)
1528#define SPR_DBAT0U (0x218)
1529#define SPR_RCPU_L2U_GRA (0x218)
1530#define SPR_DBAT0L (0x219)
1531#define SPR_DBAT1U (0x21A)
1532#define SPR_DBAT1L (0x21B)
1533#define SPR_DBAT2U (0x21C)
1534#define SPR_DBAT2L (0x21D)
1535#define SPR_DBAT3U (0x21E)
1536#define SPR_DBAT3L (0x21F)
1537#define SPR_IBAT4U (0x230)
1538#define SPR_RPCU_BBCMCR (0x230)
1539#define SPR_MPC_IC_CST (0x230)
1540#define SPR_Exxx_CTXCR (0x230)
1541#define SPR_IBAT4L (0x231)
1542#define SPR_MPC_IC_ADR (0x231)
1543#define SPR_Exxx_DBCR3 (0x231)
1544#define SPR_IBAT5U (0x232)
1545#define SPR_MPC_IC_DAT (0x232)
1546#define SPR_Exxx_DBCNT (0x232)
1547#define SPR_IBAT5L (0x233)
1548#define SPR_IBAT6U (0x234)
1549#define SPR_IBAT6L (0x235)
1550#define SPR_IBAT7U (0x236)
1551#define SPR_IBAT7L (0x237)
1552#define SPR_DBAT4U (0x238)
1553#define SPR_RCPU_L2U_MCR (0x238)
1554#define SPR_MPC_DC_CST (0x238)
1555#define SPR_Exxx_ALTCTXCR (0x238)
1556#define SPR_DBAT4L (0x239)
1557#define SPR_MPC_DC_ADR (0x239)
1558#define SPR_DBAT5U (0x23A)
1559#define SPR_BOOKE_MCSRR0 (0x23A)
1560#define SPR_MPC_DC_DAT (0x23A)
1561#define SPR_DBAT5L (0x23B)
1562#define SPR_BOOKE_MCSRR1 (0x23B)
1563#define SPR_DBAT6U (0x23C)
1564#define SPR_BOOKE_MCSR (0x23C)
1565#define SPR_DBAT6L (0x23D)
1566#define SPR_Exxx_MCAR (0x23D)
1567#define SPR_DBAT7U (0x23E)
1568#define SPR_BOOKE_DSRR0 (0x23E)
1569#define SPR_DBAT7L (0x23F)
1570#define SPR_BOOKE_DSRR1 (0x23F)
1571#define SPR_BOOKE_SPRG8 (0x25C)
1572#define SPR_BOOKE_SPRG9 (0x25D)
1573#define SPR_BOOKE_MAS0 (0x270)
1574#define SPR_BOOKE_MAS1 (0x271)
1575#define SPR_BOOKE_MAS2 (0x272)
1576#define SPR_BOOKE_MAS3 (0x273)
1577#define SPR_BOOKE_MAS4 (0x274)
1578#define SPR_BOOKE_MAS5 (0x275)
1579#define SPR_BOOKE_MAS6 (0x276)
1580#define SPR_BOOKE_PID1 (0x279)
1581#define SPR_BOOKE_PID2 (0x27A)
1582#define SPR_MPC_DPDR (0x280)
1583#define SPR_MPC_IMMR (0x288)
1584#define SPR_BOOKE_TLB0CFG (0x2B0)
1585#define SPR_BOOKE_TLB1CFG (0x2B1)
1586#define SPR_BOOKE_TLB2CFG (0x2B2)
1587#define SPR_BOOKE_TLB3CFG (0x2B3)
1588#define SPR_BOOKE_EPR (0x2BE)
1589#define SPR_PERF0 (0x300)
1590#define SPR_RCPU_MI_RBA0 (0x300)
1591#define SPR_MPC_MI_CTR (0x300)
1592#define SPR_POWER_USIER (0x300)
1593#define SPR_PERF1 (0x301)
1594#define SPR_RCPU_MI_RBA1 (0x301)
1595#define SPR_POWER_UMMCR2 (0x301)
1596#define SPR_PERF2 (0x302)
1597#define SPR_RCPU_MI_RBA2 (0x302)
1598#define SPR_MPC_MI_AP (0x302)
1599#define SPR_POWER_UMMCRA (0x302)
1600#define SPR_PERF3 (0x303)
1601#define SPR_RCPU_MI_RBA3 (0x303)
1602#define SPR_MPC_MI_EPN (0x303)
1603#define SPR_POWER_UPMC1 (0x303)
1604#define SPR_PERF4 (0x304)
1605#define SPR_POWER_UPMC2 (0x304)
1606#define SPR_PERF5 (0x305)
1607#define SPR_MPC_MI_TWC (0x305)
1608#define SPR_POWER_UPMC3 (0x305)
1609#define SPR_PERF6 (0x306)
1610#define SPR_MPC_MI_RPN (0x306)
1611#define SPR_POWER_UPMC4 (0x306)
1612#define SPR_PERF7 (0x307)
1613#define SPR_POWER_UPMC5 (0x307)
1614#define SPR_PERF8 (0x308)
1615#define SPR_RCPU_L2U_RBA0 (0x308)
1616#define SPR_MPC_MD_CTR (0x308)
1617#define SPR_POWER_UPMC6 (0x308)
1618#define SPR_PERF9 (0x309)
1619#define SPR_RCPU_L2U_RBA1 (0x309)
1620#define SPR_MPC_MD_CASID (0x309)
1621#define SPR_970_UPMC7 (0X309)
1622#define SPR_PERFA (0x30A)
1623#define SPR_RCPU_L2U_RBA2 (0x30A)
1624#define SPR_MPC_MD_AP (0x30A)
1625#define SPR_970_UPMC8 (0X30A)
1626#define SPR_PERFB (0x30B)
1627#define SPR_RCPU_L2U_RBA3 (0x30B)
1628#define SPR_MPC_MD_EPN (0x30B)
1629#define SPR_POWER_UMMCR0 (0X30B)
1630#define SPR_PERFC (0x30C)
1631#define SPR_MPC_MD_TWB (0x30C)
1632#define SPR_POWER_USIAR (0X30C)
1633#define SPR_PERFD (0x30D)
1634#define SPR_MPC_MD_TWC (0x30D)
1635#define SPR_POWER_USDAR (0X30D)
1636#define SPR_PERFE (0x30E)
1637#define SPR_MPC_MD_RPN (0x30E)
1638#define SPR_POWER_UMMCR1 (0X30E)
1639#define SPR_PERFF (0x30F)
1640#define SPR_MPC_MD_TW (0x30F)
1641#define SPR_UPERF0 (0x310)
1642#define SPR_POWER_SIER (0x310)
1643#define SPR_UPERF1 (0x311)
1644#define SPR_POWER_MMCR2 (0x311)
1645#define SPR_UPERF2 (0x312)
1646#define SPR_POWER_MMCRA (0X312)
1647#define SPR_UPERF3 (0x313)
1648#define SPR_POWER_PMC1 (0X313)
1649#define SPR_UPERF4 (0x314)
1650#define SPR_POWER_PMC2 (0X314)
1651#define SPR_UPERF5 (0x315)
1652#define SPR_POWER_PMC3 (0X315)
1653#define SPR_UPERF6 (0x316)
1654#define SPR_POWER_PMC4 (0X316)
1655#define SPR_UPERF7 (0x317)
1656#define SPR_POWER_PMC5 (0X317)
1657#define SPR_UPERF8 (0x318)
1658#define SPR_POWER_PMC6 (0X318)
1659#define SPR_UPERF9 (0x319)
1660#define SPR_970_PMC7 (0X319)
1661#define SPR_UPERFA (0x31A)
1662#define SPR_970_PMC8 (0X31A)
1663#define SPR_UPERFB (0x31B)
1664#define SPR_POWER_MMCR0 (0X31B)
1665#define SPR_UPERFC (0x31C)
1666#define SPR_POWER_SIAR (0X31C)
1667#define SPR_UPERFD (0x31D)
1668#define SPR_POWER_SDAR (0X31D)
1669#define SPR_UPERFE (0x31E)
1670#define SPR_POWER_MMCR1 (0X31E)
1671#define SPR_UPERFF (0x31F)
1672#define SPR_RCPU_MI_RA0 (0x320)
1673#define SPR_MPC_MI_DBCAM (0x320)
1674#define SPR_BESCRS (0x320)
1675#define SPR_RCPU_MI_RA1 (0x321)
1676#define SPR_MPC_MI_DBRAM0 (0x321)
1677#define SPR_BESCRSU (0x321)
1678#define SPR_RCPU_MI_RA2 (0x322)
1679#define SPR_MPC_MI_DBRAM1 (0x322)
1680#define SPR_BESCRR (0x322)
1681#define SPR_RCPU_MI_RA3 (0x323)
1682#define SPR_BESCRRU (0x323)
1683#define SPR_EBBHR (0x324)
1684#define SPR_EBBRR (0x325)
1685#define SPR_BESCR (0x326)
1686#define SPR_RCPU_L2U_RA0 (0x328)
1687#define SPR_MPC_MD_DBCAM (0x328)
1688#define SPR_RCPU_L2U_RA1 (0x329)
1689#define SPR_MPC_MD_DBRAM0 (0x329)
1690#define SPR_RCPU_L2U_RA2 (0x32A)
1691#define SPR_MPC_MD_DBRAM1 (0x32A)
1692#define SPR_RCPU_L2U_RA3 (0x32B)
1693#define SPR_TAR (0x32F)
1694#define SPR_IC (0x350)
1695#define SPR_VTB (0x351)
1696#define SPR_MMCRC (0x353)
1697#define SPR_440_INV0 (0x370)
1698#define SPR_440_INV1 (0x371)
1699#define SPR_440_INV2 (0x372)
1700#define SPR_440_INV3 (0x373)
1701#define SPR_440_ITV0 (0x374)
1702#define SPR_440_ITV1 (0x375)
1703#define SPR_440_ITV2 (0x376)
1704#define SPR_440_ITV3 (0x377)
1705#define SPR_440_CCR1 (0x378)
1706#define SPR_TACR (0x378)
1707#define SPR_TCSCR (0x379)
1708#define SPR_CSIGR (0x37a)
1709#define SPR_DCRIPR (0x37B)
1710#define SPR_POWER_SPMC1 (0x37C)
1711#define SPR_POWER_SPMC2 (0x37D)
1712#define SPR_POWER_MMCRS (0x37E)
1713#define SPR_WORT (0x37F)
1714#define SPR_PPR (0x380)
1715#define SPR_750_GQR0 (0x390)
1716#define SPR_440_DNV0 (0x390)
1717#define SPR_750_GQR1 (0x391)
1718#define SPR_440_DNV1 (0x391)
1719#define SPR_750_GQR2 (0x392)
1720#define SPR_440_DNV2 (0x392)
1721#define SPR_750_GQR3 (0x393)
1722#define SPR_440_DNV3 (0x393)
1723#define SPR_750_GQR4 (0x394)
1724#define SPR_440_DTV0 (0x394)
1725#define SPR_750_GQR5 (0x395)
1726#define SPR_440_DTV1 (0x395)
1727#define SPR_750_GQR6 (0x396)
1728#define SPR_440_DTV2 (0x396)
1729#define SPR_750_GQR7 (0x397)
1730#define SPR_440_DTV3 (0x397)
1731#define SPR_750_THRM4 (0x398)
1732#define SPR_750CL_HID2 (0x398)
1733#define SPR_440_DVLIM (0x398)
1734#define SPR_750_WPAR (0x399)
1735#define SPR_440_IVLIM (0x399)
1736#define SPR_TSCR (0x399)
1737#define SPR_750_DMAU (0x39A)
1738#define SPR_750_DMAL (0x39B)
1739#define SPR_440_RSTCFG (0x39B)
1740#define SPR_BOOKE_DCDBTRL (0x39C)
1741#define SPR_BOOKE_DCDBTRH (0x39D)
1742#define SPR_BOOKE_ICDBTRL (0x39E)
1743#define SPR_BOOKE_ICDBTRH (0x39F)
1744#define SPR_74XX_UMMCR2 (0x3A0)
1745#define SPR_7XX_UPMC5 (0x3A1)
1746#define SPR_7XX_UPMC6 (0x3A2)
1747#define SPR_UBAMR (0x3A7)
1748#define SPR_7XX_UMMCR0 (0x3A8)
1749#define SPR_7XX_UPMC1 (0x3A9)
1750#define SPR_7XX_UPMC2 (0x3AA)
1751#define SPR_7XX_USIAR (0x3AB)
1752#define SPR_7XX_UMMCR1 (0x3AC)
1753#define SPR_7XX_UPMC3 (0x3AD)
1754#define SPR_7XX_UPMC4 (0x3AE)
1755#define SPR_USDA (0x3AF)
1756#define SPR_40x_ZPR (0x3B0)
1757#define SPR_BOOKE_MAS7 (0x3B0)
1758#define SPR_74XX_MMCR2 (0x3B0)
1759#define SPR_7XX_PMC5 (0x3B1)
1760#define SPR_40x_PID (0x3B1)
1761#define SPR_7XX_PMC6 (0x3B2)
1762#define SPR_440_MMUCR (0x3B2)
1763#define SPR_4xx_CCR0 (0x3B3)
1764#define SPR_BOOKE_EPLC (0x3B3)
1765#define SPR_405_IAC3 (0x3B4)
1766#define SPR_BOOKE_EPSC (0x3B4)
1767#define SPR_405_IAC4 (0x3B5)
1768#define SPR_405_DVC1 (0x3B6)
1769#define SPR_405_DVC2 (0x3B7)
1770#define SPR_BAMR (0x3B7)
1771#define SPR_7XX_MMCR0 (0x3B8)
1772#define SPR_7XX_PMC1 (0x3B9)
1773#define SPR_40x_SGR (0x3B9)
1774#define SPR_7XX_PMC2 (0x3BA)
1775#define SPR_40x_DCWR (0x3BA)
1776#define SPR_7XX_SIAR (0x3BB)
1777#define SPR_405_SLER (0x3BB)
1778#define SPR_7XX_MMCR1 (0x3BC)
1779#define SPR_405_SU0R (0x3BC)
1780#define SPR_401_SKR (0x3BC)
1781#define SPR_7XX_PMC3 (0x3BD)
1782#define SPR_405_DBCR1 (0x3BD)
1783#define SPR_7XX_PMC4 (0x3BE)
1784#define SPR_SDA (0x3BF)
1785#define SPR_403_VTBL (0x3CC)
1786#define SPR_403_VTBU (0x3CD)
1787#define SPR_DMISS (0x3D0)
1788#define SPR_DCMP (0x3D1)
1789#define SPR_HASH1 (0x3D2)
1790#define SPR_HASH2 (0x3D3)
1791#define SPR_BOOKE_ICDBDR (0x3D3)
1792#define SPR_TLBMISS (0x3D4)
1793#define SPR_IMISS (0x3D4)
1794#define SPR_40x_ESR (0x3D4)
1795#define SPR_PTEHI (0x3D5)
1796#define SPR_ICMP (0x3D5)
1797#define SPR_40x_DEAR (0x3D5)
1798#define SPR_PTELO (0x3D6)
1799#define SPR_RPA (0x3D6)
1800#define SPR_40x_EVPR (0x3D6)
1801#define SPR_L3PM (0x3D7)
1802#define SPR_403_CDBCR (0x3D7)
1803#define SPR_L3ITCR0 (0x3D8)
1804#define SPR_TCR (0x3D8)
1805#define SPR_40x_TSR (0x3D8)
1806#define SPR_IBR (0x3DA)
1807#define SPR_40x_TCR (0x3DA)
1808#define SPR_ESASRR (0x3DB)
1809#define SPR_40x_PIT (0x3DB)
1810#define SPR_403_TBL (0x3DC)
1811#define SPR_403_TBU (0x3DD)
1812#define SPR_SEBR (0x3DE)
1813#define SPR_40x_SRR2 (0x3DE)
1814#define SPR_SER (0x3DF)
1815#define SPR_40x_SRR3 (0x3DF)
1816#define SPR_L3OHCR (0x3E8)
1817#define SPR_L3ITCR1 (0x3E9)
1818#define SPR_L3ITCR2 (0x3EA)
1819#define SPR_L3ITCR3 (0x3EB)
1820#define SPR_HID0 (0x3F0)
1821#define SPR_40x_DBSR (0x3F0)
1822#define SPR_HID1 (0x3F1)
1823#define SPR_IABR (0x3F2)
1824#define SPR_40x_DBCR0 (0x3F2)
1825#define SPR_601_HID2 (0x3F2)
1826#define SPR_Exxx_L1CSR0 (0x3F2)
1827#define SPR_ICTRL (0x3F3)
1828#define SPR_HID2 (0x3F3)
1829#define SPR_750CL_HID4 (0x3F3)
1830#define SPR_Exxx_L1CSR1 (0x3F3)
1831#define SPR_440_DBDR (0x3F3)
1832#define SPR_LDSTDB (0x3F4)
1833#define SPR_750_TDCL (0x3F4)
1834#define SPR_40x_IAC1 (0x3F4)
1835#define SPR_MMUCSR0 (0x3F4)
1836#define SPR_970_HID4 (0x3F4)
1837#define SPR_DABR (0x3F5)
1838#define DABR_MASK (~(target_ulong)0x7)
1839#define SPR_Exxx_BUCSR (0x3F5)
1840#define SPR_40x_IAC2 (0x3F5)
1841#define SPR_601_HID5 (0x3F5)
1842#define SPR_40x_DAC1 (0x3F6)
1843#define SPR_MSSCR0 (0x3F6)
1844#define SPR_970_HID5 (0x3F6)
1845#define SPR_MSSSR0 (0x3F7)
1846#define SPR_MSSCR1 (0x3F7)
1847#define SPR_DABRX (0x3F7)
1848#define SPR_40x_DAC2 (0x3F7)
1849#define SPR_MMUCFG (0x3F7)
1850#define SPR_LDSTCR (0x3F8)
1851#define SPR_L2PMCR (0x3F8)
1852#define SPR_750FX_HID2 (0x3F8)
1853#define SPR_Exxx_L1FINV0 (0x3F8)
1854#define SPR_L2CR (0x3F9)
1855#define SPR_L3CR (0x3FA)
1856#define SPR_750_TDCH (0x3FA)
1857#define SPR_IABR2 (0x3FA)
1858#define SPR_40x_DCCR (0x3FA)
1859#define SPR_ICTC (0x3FB)
1860#define SPR_40x_ICCR (0x3FB)
1861#define SPR_THRM1 (0x3FC)
1862#define SPR_403_PBL1 (0x3FC)
1863#define SPR_SP (0x3FD)
1864#define SPR_THRM2 (0x3FD)
1865#define SPR_403_PBU1 (0x3FD)
1866#define SPR_604_HID13 (0x3FD)
1867#define SPR_LT (0x3FE)
1868#define SPR_THRM3 (0x3FE)
1869#define SPR_RCPU_FPECR (0x3FE)
1870#define SPR_403_PBL2 (0x3FE)
1871#define SPR_PIR (0x3FF)
1872#define SPR_403_PBU2 (0x3FF)
1873#define SPR_601_HID15 (0x3FF)
1874#define SPR_604_HID15 (0x3FF)
1875#define SPR_E500_SVR (0x3FF)
1876
1877
1878#define EPCR_DMIUH (1 << 22)
1879
1880#define EPCR_DGTMI (1 << 23)
1881
1882#define EPCR_GICM (1 << 24)
1883
1884#define EPCR_ICM (1 << 25)
1885
1886#define EPCR_DUVD (1 << 26)
1887
1888#define EPCR_ISIGS (1 << 27)
1889
1890#define EPCR_DSIGS (1 << 28)
1891
1892#define EPCR_ITLBGS (1 << 29)
1893
1894#define EPCR_DTLBGS (1 << 30)
1895
1896#define EPCR_EXTGS (1 << 31)
1897
1898#define L1CSR0_CPE 0x00010000
1899#define L1CSR0_CUL 0x00000400
1900#define L1CSR0_DCLFR 0x00000100
1901#define L1CSR0_DCFI 0x00000002
1902#define L1CSR0_DCE 0x00000001
1903
1904#define L1CSR1_CPE 0x00010000
1905#define L1CSR1_ICUL 0x00000400
1906#define L1CSR1_ICLFR 0x00000100
1907#define L1CSR1_ICFI 0x00000002
1908#define L1CSR1_ICE 0x00000001
1909
1910
1911#define HID0_DEEPNAP (1 << 24)
1912#define HID0_DOZE (1 << 23)
1913#define HID0_NAP (1 << 22)
1914#define HID0_HILE (1ull << (63 - 19))
1915
1916
1917
1918enum {
1919 PPC_NONE = 0x0000000000000000ULL,
1920
1921 PPC_INSNS_BASE = 0x0000000000000001ULL,
1922
1923#define PPC_INTEGER PPC_INSNS_BASE
1924
1925#define PPC_FLOW PPC_INSNS_BASE
1926
1927#define PPC_MEM PPC_INSNS_BASE
1928
1929#define PPC_RES PPC_INSNS_BASE
1930
1931#define PPC_MISC PPC_INSNS_BASE
1932
1933
1934 PPC_POWER = 0x0000000000000002ULL,
1935
1936 PPC_POWER2 = 0x0000000000000004ULL,
1937
1938 PPC_POWER_RTC = 0x0000000000000008ULL,
1939
1940 PPC_POWER_BR = 0x0000000000000010ULL,
1941
1942 PPC_64B = 0x0000000000000020ULL,
1943
1944 PPC_64BX = 0x0000000000000040ULL,
1945
1946 PPC_64H = 0x0000000000000080ULL,
1947
1948 PPC_WAIT = 0x0000000000000100ULL,
1949
1950 PPC_MFTB = 0x0000000000000200ULL,
1951
1952
1953
1954 PPC_602_SPEC = 0x0000000000000400ULL,
1955
1956 PPC_ISEL = 0x0000000000000800ULL,
1957
1958 PPC_POPCNTB = 0x0000000000001000ULL,
1959
1960 PPC_STRING = 0x0000000000002000ULL,
1961
1962
1963
1964 PPC_FLOAT = 0x0000000000010000ULL,
1965
1966 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1967 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1968 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1969 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1970 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1971 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1972 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1973
1974
1975
1976 PPC_ALTIVEC = 0x0000000001000000ULL,
1977
1978 PPC_SPE = 0x0000000002000000ULL,
1979
1980 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1981
1982 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1983
1984
1985 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1986 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1987 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1988
1989 PPC_MEM_SYNC = 0x0000000080000000ULL,
1990
1991 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1992
1993
1994 PPC_CACHE = 0x0000000200000000ULL,
1995
1996 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1997
1998 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1999
2000 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2001
2002 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2003
2004
2005
2006 PPC_EXTERN = 0x0000010000000000ULL,
2007
2008 PPC_SEGMENT = 0x0000020000000000ULL,
2009
2010 PPC_6xx_TLB = 0x0000040000000000ULL,
2011
2012 PPC_74xx_TLB = 0x0000080000000000ULL,
2013
2014 PPC_40x_TLB = 0x0000100000000000ULL,
2015
2016 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2017
2018 PPC_SLBI = 0x0000400000000000ULL,
2019
2020
2021 PPC_WRTEE = 0x0001000000000000ULL,
2022
2023 PPC_40x_EXCP = 0x0002000000000000ULL,
2024
2025 PPC_405_MAC = 0x0004000000000000ULL,
2026
2027 PPC_440_SPEC = 0x0008000000000000ULL,
2028
2029 PPC_BOOKE = 0x0010000000000000ULL,
2030
2031 PPC_MFAPIDI = 0x0020000000000000ULL,
2032
2033 PPC_TLBIVA = 0x0040000000000000ULL,
2034
2035 PPC_TLBIVAX = 0x0080000000000000ULL,
2036
2037 PPC_4xx_COMMON = 0x0100000000000000ULL,
2038
2039 PPC_40x_ICBT = 0x0200000000000000ULL,
2040
2041 PPC_RFMCI = 0x0400000000000000ULL,
2042
2043 PPC_RFDI = 0x0800000000000000ULL,
2044
2045 PPC_DCR = 0x1000000000000000ULL,
2046
2047 PPC_DCRX = 0x2000000000000000ULL,
2048
2049 PPC_DCRUX = 0x4000000000000000ULL,
2050
2051 PPC_POPCNTWD = 0x8000000000000000ULL,
2052
2053#define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2054 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2055 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2056 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2057 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2058 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2059 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2060 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2061 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2062 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2063 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2064 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2065 | PPC_CACHE | PPC_CACHE_ICBI \
2066 | PPC_CACHE_DCBZ \
2067 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2068 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2069 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2070 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2071 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2072 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2073 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2074 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2075 | PPC_POPCNTWD)
2076
2077
2078
2079
2080 PPC2_BOOKE206 = 0x0000000000000001ULL,
2081
2082 PPC2_VSX = 0x0000000000000002ULL,
2083
2084 PPC2_DFP = 0x0000000000000004ULL,
2085
2086 PPC2_PRCNTL = 0x0000000000000008ULL,
2087
2088 PPC2_DBRX = 0x0000000000000010ULL,
2089
2090 PPC2_ISA205 = 0x0000000000000020ULL,
2091
2092 PPC2_VSX207 = 0x0000000000000040ULL,
2093
2094 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2095
2096 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2097
2098 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2099
2100 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2101
2102 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2103
2104 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2105
2106 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2107
2108 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2109
2110 PPC2_ISA207S = 0x0000000000008000ULL,
2111
2112 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2113
2114 PPC2_TM = 0x0000000000020000ULL,
2115
2116#define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2117 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2118 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2119 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2120 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2121 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2122 PPC2_FP_CVT_S64 | PPC2_TM)
2123};
2124
2125
2126
2127
2128
2129enum {
2130
2131 ACCESS_USER = 0x00,
2132 ACCESS_SUPER = 0x01,
2133
2134 ACCESS_CODE = 0x10,
2135 ACCESS_INT = 0x20,
2136 ACCESS_FLOAT = 0x30,
2137 ACCESS_RES = 0x40,
2138 ACCESS_EXT = 0x50,
2139 ACCESS_CACHE = 0x60,
2140};
2141
2142
2143
2144
2145
2146enum {
2147
2148 PPC6xx_INPUT_HRESET = 0,
2149 PPC6xx_INPUT_SRESET = 1,
2150 PPC6xx_INPUT_CKSTP_IN = 2,
2151 PPC6xx_INPUT_MCP = 3,
2152 PPC6xx_INPUT_SMI = 4,
2153 PPC6xx_INPUT_INT = 5,
2154 PPC6xx_INPUT_TBEN = 6,
2155 PPC6xx_INPUT_WAKEUP = 7,
2156 PPC6xx_INPUT_NB,
2157};
2158
2159enum {
2160
2161 PPCBookE_INPUT_HRESET = 0,
2162 PPCBookE_INPUT_SRESET = 1,
2163 PPCBookE_INPUT_CKSTP_IN = 2,
2164 PPCBookE_INPUT_MCP = 3,
2165 PPCBookE_INPUT_SMI = 4,
2166 PPCBookE_INPUT_INT = 5,
2167 PPCBookE_INPUT_CINT = 6,
2168 PPCBookE_INPUT_NB,
2169};
2170
2171enum {
2172
2173 PPCE500_INPUT_RESET_CORE = 0,
2174 PPCE500_INPUT_MCK = 1,
2175 PPCE500_INPUT_CINT = 3,
2176 PPCE500_INPUT_INT = 4,
2177 PPCE500_INPUT_DEBUG = 6,
2178 PPCE500_INPUT_NB,
2179};
2180
2181enum {
2182
2183 PPC40x_INPUT_RESET_CORE = 0,
2184 PPC40x_INPUT_RESET_CHIP = 1,
2185 PPC40x_INPUT_RESET_SYS = 2,
2186 PPC40x_INPUT_CINT = 3,
2187 PPC40x_INPUT_INT = 4,
2188 PPC40x_INPUT_HALT = 5,
2189 PPC40x_INPUT_DEBUG = 6,
2190 PPC40x_INPUT_NB,
2191};
2192
2193enum {
2194
2195 PPCRCPU_INPUT_PORESET = 0,
2196 PPCRCPU_INPUT_HRESET = 1,
2197 PPCRCPU_INPUT_SRESET = 2,
2198 PPCRCPU_INPUT_IRQ0 = 3,
2199 PPCRCPU_INPUT_IRQ1 = 4,
2200 PPCRCPU_INPUT_IRQ2 = 5,
2201 PPCRCPU_INPUT_IRQ3 = 6,
2202 PPCRCPU_INPUT_IRQ4 = 7,
2203 PPCRCPU_INPUT_IRQ5 = 8,
2204 PPCRCPU_INPUT_IRQ6 = 9,
2205 PPCRCPU_INPUT_IRQ7 = 10,
2206 PPCRCPU_INPUT_NB,
2207};
2208
2209#if defined(TARGET_PPC64)
2210enum {
2211
2212 PPC970_INPUT_HRESET = 0,
2213 PPC970_INPUT_SRESET = 1,
2214 PPC970_INPUT_CKSTP = 2,
2215 PPC970_INPUT_TBEN = 3,
2216 PPC970_INPUT_MCP = 4,
2217 PPC970_INPUT_INT = 5,
2218 PPC970_INPUT_THINT = 6,
2219 PPC970_INPUT_NB,
2220};
2221
2222enum {
2223
2224 POWER7_INPUT_INT = 0,
2225
2226
2227
2228 POWER7_INPUT_NB,
2229};
2230#endif
2231
2232
2233enum {
2234
2235 PPC_INTERRUPT_RESET = 0,
2236 PPC_INTERRUPT_WAKEUP,
2237 PPC_INTERRUPT_MCK,
2238 PPC_INTERRUPT_EXT,
2239 PPC_INTERRUPT_SMI,
2240 PPC_INTERRUPT_CEXT,
2241 PPC_INTERRUPT_DEBUG,
2242 PPC_INTERRUPT_THERM,
2243
2244 PPC_INTERRUPT_DECR,
2245 PPC_INTERRUPT_HDECR,
2246 PPC_INTERRUPT_PIT,
2247 PPC_INTERRUPT_FIT,
2248 PPC_INTERRUPT_WDT,
2249 PPC_INTERRUPT_CDOORBELL,
2250 PPC_INTERRUPT_DOORBELL,
2251 PPC_INTERRUPT_PERFM,
2252};
2253
2254
2255enum {
2256 PCR_COMPAT_2_05 = 1ull << (63-62),
2257 PCR_COMPAT_2_06 = 1ull << (63-61),
2258 PCR_VEC_DIS = 1ull << (63-0),
2259 PCR_VSX_DIS = 1ull << (63-1),
2260 PCR_TM_DIS = 1ull << (63-2),
2261};
2262
2263
2264enum {
2265 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2266 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2267 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2268 HMER_TFAC_ERROR = 1ull << (63 - 4),
2269 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2270 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2271 HMER_XSCOM_DONE = 1ull << (63 - 9),
2272 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2273 HMER_WARN_RISE = 1ull << (63 - 14),
2274 HMER_WARN_FALL = 1ull << (63 - 15),
2275 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2276 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2277 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2278 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2279 HMER_XSCOM_STATUS_LSH = (63 - 23),
2280};
2281
2282
2283enum {
2284 AIL_NONE = 0,
2285 AIL_RESERVED = 1,
2286 AIL_0001_8000 = 2,
2287 AIL_C000_0000_0000_4000 = 3,
2288};
2289
2290
2291
2292static inline target_ulong cpu_read_xer(CPUPPCState *env)
2293{
2294 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2295}
2296
2297static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2298{
2299 env->so = (xer >> XER_SO) & 1;
2300 env->ov = (xer >> XER_OV) & 1;
2301 env->ca = (xer >> XER_CA) & 1;
2302 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2303}
2304
2305static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2306 target_ulong *cs_base, int *flags)
2307{
2308 *pc = env->nip;
2309 *cs_base = 0;
2310 *flags = env->hflags;
2311}
2312
2313#if !defined(CONFIG_USER_ONLY)
2314static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2315{
2316 uintptr_t tlbml = (uintptr_t)tlbm;
2317 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2318
2319 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2320}
2321
2322static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2323{
2324 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2325 int r = tlbncfg & TLBnCFG_N_ENTRY;
2326 return r;
2327}
2328
2329static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2330{
2331 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2332 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2333 return r;
2334}
2335
2336static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2337{
2338 int id = booke206_tlbm_id(env, tlbm);
2339 int end = 0;
2340 int i;
2341
2342 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2343 end += booke206_tlb_size(env, i);
2344 if (id < end) {
2345 return i;
2346 }
2347 }
2348
2349 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2350 return 0;
2351}
2352
2353static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2354{
2355 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2356 int tlbid = booke206_tlbm_id(env, tlb);
2357 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2358}
2359
2360static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2361 target_ulong ea, int way)
2362{
2363 int r;
2364 uint32_t ways = booke206_tlb_ways(env, tlbn);
2365 int ways_bits = ctz32(ways);
2366 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2367 int i;
2368
2369 way &= ways - 1;
2370 ea >>= MAS2_EPN_SHIFT;
2371 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2372 r = (ea << ways_bits) | way;
2373
2374 if (r >= booke206_tlb_size(env, tlbn)) {
2375 return NULL;
2376 }
2377
2378
2379 for (i = 0; i < tlbn; i++) {
2380 r += booke206_tlb_size(env, i);
2381 }
2382
2383 return &env->tlb.tlbm[r];
2384}
2385
2386
2387static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2388{
2389 bool mav2 = false;
2390 uint32_t ret = 0;
2391
2392 if (mav2) {
2393 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2394 } else {
2395 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2396 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2397 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2398 int i;
2399 for (i = min; i <= max; i++) {
2400 ret |= (1 << (i << 1));
2401 }
2402 }
2403
2404 return ret;
2405}
2406
2407#endif
2408
2409static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2410{
2411 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2412 return msr & (1ULL << MSR_CM);
2413 }
2414
2415 return msr & (1ULL << MSR_SF);
2416}
2417
2418
2419
2420
2421
2422static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2423{
2424 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2425 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2426}
2427
2428extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2429
2430#include "exec/exec-all.h"
2431
2432void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2433
2434
2435
2436
2437
2438
2439
2440int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2441
2442
2443
2444
2445
2446
2447
2448
2449
2450PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2451
2452void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2453#endif
2454