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28#include "qemu/osdep.h"
29#include "qapi/error.h"
30#include "qemu-common.h"
31#include "cpu.h"
32#include "hw/hw.h"
33#include "trace.h"
34#include "sysemu/kvm.h"
35#include "hw/ppc/spapr.h"
36#include "hw/ppc/xics.h"
37#include "kvm_ppc.h"
38#include "qemu/config-file.h"
39#include "qemu/error-report.h"
40
41#include <sys/ioctl.h>
42
43typedef struct KVMXICSState {
44 XICSState parent_obj;
45
46 int kernel_xics_fd;
47} KVMXICSState;
48
49
50
51
52static void icp_get_kvm_state(ICPState *ss)
53{
54 uint64_t state;
55 struct kvm_one_reg reg = {
56 .id = KVM_REG_PPC_ICP_STATE,
57 .addr = (uintptr_t)&state,
58 };
59 int ret;
60
61
62 if (!ss->cs) {
63 return;
64 }
65
66 ret = kvm_vcpu_ioctl(ss->cs, KVM_GET_ONE_REG, ®);
67 if (ret != 0) {
68 error_report("Unable to retrieve KVM interrupt controller state"
69 " for CPU %ld: %s", kvm_arch_vcpu_id(ss->cs), strerror(errno));
70 exit(1);
71 }
72
73 ss->xirr = state >> KVM_REG_PPC_ICP_XISR_SHIFT;
74 ss->mfrr = (state >> KVM_REG_PPC_ICP_MFRR_SHIFT)
75 & KVM_REG_PPC_ICP_MFRR_MASK;
76 ss->pending_priority = (state >> KVM_REG_PPC_ICP_PPRI_SHIFT)
77 & KVM_REG_PPC_ICP_PPRI_MASK;
78}
79
80static int icp_set_kvm_state(ICPState *ss, int version_id)
81{
82 uint64_t state;
83 struct kvm_one_reg reg = {
84 .id = KVM_REG_PPC_ICP_STATE,
85 .addr = (uintptr_t)&state,
86 };
87 int ret;
88
89
90 if (!ss->cs) {
91 return 0;
92 }
93
94 state = ((uint64_t)ss->xirr << KVM_REG_PPC_ICP_XISR_SHIFT)
95 | ((uint64_t)ss->mfrr << KVM_REG_PPC_ICP_MFRR_SHIFT)
96 | ((uint64_t)ss->pending_priority << KVM_REG_PPC_ICP_PPRI_SHIFT);
97
98 ret = kvm_vcpu_ioctl(ss->cs, KVM_SET_ONE_REG, ®);
99 if (ret != 0) {
100 error_report("Unable to restore KVM interrupt controller state (0x%"
101 PRIx64 ") for CPU %ld: %s", state, kvm_arch_vcpu_id(ss->cs),
102 strerror(errno));
103 return ret;
104 }
105
106 return 0;
107}
108
109static void icp_kvm_reset(DeviceState *dev)
110{
111 ICPState *icp = ICP(dev);
112
113 icp->xirr = 0;
114 icp->pending_priority = 0xff;
115 icp->mfrr = 0xff;
116
117
118 if (icp->output) {
119 qemu_set_irq(icp->output, 0);
120 }
121
122 icp_set_kvm_state(icp, 1);
123}
124
125static void icp_kvm_class_init(ObjectClass *klass, void *data)
126{
127 DeviceClass *dc = DEVICE_CLASS(klass);
128 ICPStateClass *icpc = ICP_CLASS(klass);
129
130 dc->reset = icp_kvm_reset;
131 icpc->pre_save = icp_get_kvm_state;
132 icpc->post_load = icp_set_kvm_state;
133}
134
135static const TypeInfo icp_kvm_info = {
136 .name = TYPE_KVM_ICP,
137 .parent = TYPE_ICP,
138 .instance_size = sizeof(ICPState),
139 .class_init = icp_kvm_class_init,
140 .class_size = sizeof(ICPStateClass),
141};
142
143
144
145
146static void ics_get_kvm_state(ICSState *ics)
147{
148 KVMXICSState *xicskvm = XICS_SPAPR_KVM(ics->xics);
149 uint64_t state;
150 struct kvm_device_attr attr = {
151 .flags = 0,
152 .group = KVM_DEV_XICS_GRP_SOURCES,
153 .addr = (uint64_t)(uintptr_t)&state,
154 };
155 int i;
156
157 for (i = 0; i < ics->nr_irqs; i++) {
158 ICSIRQState *irq = &ics->irqs[i];
159 int ret;
160
161 attr.attr = i + ics->offset;
162
163 ret = ioctl(xicskvm->kernel_xics_fd, KVM_GET_DEVICE_ATTR, &attr);
164 if (ret != 0) {
165 error_report("Unable to retrieve KVM interrupt controller state"
166 " for IRQ %d: %s", i + ics->offset, strerror(errno));
167 exit(1);
168 }
169
170 irq->server = state & KVM_XICS_DESTINATION_MASK;
171 irq->saved_priority = (state >> KVM_XICS_PRIORITY_SHIFT)
172 & KVM_XICS_PRIORITY_MASK;
173
174
175
176
177
178
179
180
181 if (state & KVM_XICS_MASKED) {
182 irq->priority = 0xff;
183 } else {
184 irq->priority = irq->saved_priority;
185 }
186
187 if (state & KVM_XICS_PENDING) {
188 if (state & KVM_XICS_LEVEL_SENSITIVE) {
189 irq->status |= XICS_STATUS_ASSERTED;
190 } else {
191
192
193
194
195
196
197
198 irq->status |= XICS_STATUS_MASKED_PENDING
199 | XICS_STATUS_REJECTED;
200 }
201 }
202 }
203}
204
205static int ics_set_kvm_state(ICSState *ics, int version_id)
206{
207 KVMXICSState *xicskvm = XICS_SPAPR_KVM(ics->xics);
208 uint64_t state;
209 struct kvm_device_attr attr = {
210 .flags = 0,
211 .group = KVM_DEV_XICS_GRP_SOURCES,
212 .addr = (uint64_t)(uintptr_t)&state,
213 };
214 int i;
215
216 for (i = 0; i < ics->nr_irqs; i++) {
217 ICSIRQState *irq = &ics->irqs[i];
218 int ret;
219
220 attr.attr = i + ics->offset;
221
222 state = irq->server;
223 state |= (uint64_t)(irq->saved_priority & KVM_XICS_PRIORITY_MASK)
224 << KVM_XICS_PRIORITY_SHIFT;
225 if (irq->priority != irq->saved_priority) {
226 assert(irq->priority == 0xff);
227 state |= KVM_XICS_MASKED;
228 }
229
230 if (ics->irqs[i].flags & XICS_FLAGS_IRQ_LSI) {
231 state |= KVM_XICS_LEVEL_SENSITIVE;
232 if (irq->status & XICS_STATUS_ASSERTED) {
233 state |= KVM_XICS_PENDING;
234 }
235 } else {
236 if (irq->status & XICS_STATUS_MASKED_PENDING) {
237 state |= KVM_XICS_PENDING;
238 }
239 }
240
241 ret = ioctl(xicskvm->kernel_xics_fd, KVM_SET_DEVICE_ATTR, &attr);
242 if (ret != 0) {
243 error_report("Unable to restore KVM interrupt controller state"
244 " for IRQs %d: %s", i + ics->offset, strerror(errno));
245 return ret;
246 }
247 }
248
249 return 0;
250}
251
252static void ics_kvm_set_irq(void *opaque, int srcno, int val)
253{
254 ICSState *ics = opaque;
255 struct kvm_irq_level args;
256 int rc;
257
258 args.irq = srcno + ics->offset;
259 if (ics->irqs[srcno].flags & XICS_FLAGS_IRQ_MSI) {
260 if (!val) {
261 return;
262 }
263 args.level = KVM_INTERRUPT_SET;
264 } else {
265 args.level = val ? KVM_INTERRUPT_SET_LEVEL : KVM_INTERRUPT_UNSET;
266 }
267 rc = kvm_vm_ioctl(kvm_state, KVM_IRQ_LINE, &args);
268 if (rc < 0) {
269 perror("kvm_irq_line");
270 }
271}
272
273static void ics_kvm_reset(DeviceState *dev)
274{
275 ICSState *ics = ICS_SIMPLE(dev);
276 int i;
277 uint8_t flags[ics->nr_irqs];
278
279 for (i = 0; i < ics->nr_irqs; i++) {
280 flags[i] = ics->irqs[i].flags;
281 }
282
283 memset(ics->irqs, 0, sizeof(ICSIRQState) * ics->nr_irqs);
284
285 for (i = 0; i < ics->nr_irqs; i++) {
286 ics->irqs[i].priority = 0xff;
287 ics->irqs[i].saved_priority = 0xff;
288 ics->irqs[i].flags = flags[i];
289 }
290
291 ics_set_kvm_state(ics, 1);
292}
293
294static void ics_kvm_realize(DeviceState *dev, Error **errp)
295{
296 ICSState *ics = ICS_SIMPLE(dev);
297
298 if (!ics->nr_irqs) {
299 error_setg(errp, "Number of interrupts needs to be greater 0");
300 return;
301 }
302 ics->irqs = g_malloc0(ics->nr_irqs * sizeof(ICSIRQState));
303 ics->qirqs = qemu_allocate_irqs(ics_kvm_set_irq, ics, ics->nr_irqs);
304}
305
306static void ics_kvm_class_init(ObjectClass *klass, void *data)
307{
308 DeviceClass *dc = DEVICE_CLASS(klass);
309 ICSStateClass *icsc = ICS_BASE_CLASS(klass);
310
311 dc->realize = ics_kvm_realize;
312 dc->reset = ics_kvm_reset;
313 icsc->pre_save = ics_get_kvm_state;
314 icsc->post_load = ics_set_kvm_state;
315}
316
317static const TypeInfo ics_kvm_info = {
318 .name = TYPE_ICS_KVM,
319 .parent = TYPE_ICS_SIMPLE,
320 .instance_size = sizeof(ICSState),
321 .class_init = ics_kvm_class_init,
322};
323
324
325
326
327static void xics_kvm_cpu_setup(XICSState *xics, PowerPCCPU *cpu)
328{
329 CPUState *cs;
330 ICPState *ss;
331 KVMXICSState *xicskvm = XICS_SPAPR_KVM(xics);
332 int ret;
333
334 cs = CPU(cpu);
335 ss = &xics->ss[cs->cpu_index];
336
337 assert(cs->cpu_index < xics->nr_servers);
338 if (xicskvm->kernel_xics_fd == -1) {
339 abort();
340 }
341
342
343
344
345
346
347 if (ss->cap_irq_xics_enabled) {
348 return;
349 }
350
351 ret = kvm_vcpu_enable_cap(cs, KVM_CAP_IRQ_XICS, 0, xicskvm->kernel_xics_fd,
352 kvm_arch_vcpu_id(cs));
353 if (ret < 0) {
354 error_report("Unable to connect CPU%ld to kernel XICS: %s",
355 kvm_arch_vcpu_id(cs), strerror(errno));
356 exit(1);
357 }
358 ss->cap_irq_xics_enabled = true;
359}
360
361static void xics_kvm_set_nr_irqs(XICSState *xics, uint32_t nr_irqs,
362 Error **errp)
363{
364 ICSState *ics = QLIST_FIRST(&xics->ics);
365
366
367 xics->nr_irqs = nr_irqs;
368 if (ics) {
369 ics->nr_irqs = nr_irqs;
370 }
371}
372
373static void xics_kvm_set_nr_servers(XICSState *xics, uint32_t nr_servers,
374 Error **errp)
375{
376 xics_set_nr_servers(xics, nr_servers, TYPE_KVM_ICP, errp);
377}
378
379static void rtas_dummy(PowerPCCPU *cpu, sPAPRMachineState *spapr,
380 uint32_t token,
381 uint32_t nargs, target_ulong args,
382 uint32_t nret, target_ulong rets)
383{
384 error_report("pseries: %s must never be called for in-kernel XICS",
385 __func__);
386}
387
388static void xics_kvm_realize(DeviceState *dev, Error **errp)
389{
390 KVMXICSState *xicskvm = XICS_SPAPR_KVM(dev);
391 XICSState *xics = XICS_COMMON(dev);
392 ICSState *ics;
393 int i, rc;
394 Error *error = NULL;
395 struct kvm_create_device xics_create_device = {
396 .type = KVM_DEV_TYPE_XICS,
397 .flags = 0,
398 };
399
400 if (!kvm_enabled() || !kvm_check_extension(kvm_state, KVM_CAP_IRQ_XICS)) {
401 error_setg(errp,
402 "KVM and IRQ_XICS capability must be present for in-kernel XICS");
403 goto fail;
404 }
405
406 spapr_rtas_register(RTAS_IBM_SET_XIVE, "ibm,set-xive", rtas_dummy);
407 spapr_rtas_register(RTAS_IBM_GET_XIVE, "ibm,get-xive", rtas_dummy);
408 spapr_rtas_register(RTAS_IBM_INT_OFF, "ibm,int-off", rtas_dummy);
409 spapr_rtas_register(RTAS_IBM_INT_ON, "ibm,int-on", rtas_dummy);
410
411 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_SET_XIVE, "ibm,set-xive");
412 if (rc < 0) {
413 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,set-xive");
414 goto fail;
415 }
416
417 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_GET_XIVE, "ibm,get-xive");
418 if (rc < 0) {
419 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,get-xive");
420 goto fail;
421 }
422
423 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_ON, "ibm,int-on");
424 if (rc < 0) {
425 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-on");
426 goto fail;
427 }
428
429 rc = kvmppc_define_rtas_kernel_token(RTAS_IBM_INT_OFF, "ibm,int-off");
430 if (rc < 0) {
431 error_setg(errp, "kvmppc_define_rtas_kernel_token: ibm,int-off");
432 goto fail;
433 }
434
435
436 rc = kvm_vm_ioctl(kvm_state, KVM_CREATE_DEVICE, &xics_create_device);
437 if (rc < 0) {
438 error_setg_errno(errp, -rc, "Error on KVM_CREATE_DEVICE for XICS");
439 goto fail;
440 }
441
442 xicskvm->kernel_xics_fd = xics_create_device.fd;
443
444 QLIST_FOREACH(ics, &xics->ics, list) {
445 object_property_set_bool(OBJECT(ics), true, "realized", &error);
446 if (error) {
447 error_propagate(errp, error);
448 goto fail;
449 }
450 }
451
452 assert(xics->nr_servers);
453 for (i = 0; i < xics->nr_servers; i++) {
454 object_property_set_bool(OBJECT(&xics->ss[i]), true, "realized",
455 &error);
456 if (error) {
457 error_propagate(errp, error);
458 goto fail;
459 }
460 }
461
462 kvm_kernel_irqchip = true;
463 kvm_msi_via_irqfd_allowed = true;
464 kvm_gsi_direct_mapping = true;
465
466 return;
467
468fail:
469 kvmppc_define_rtas_kernel_token(0, "ibm,set-xive");
470 kvmppc_define_rtas_kernel_token(0, "ibm,get-xive");
471 kvmppc_define_rtas_kernel_token(0, "ibm,int-on");
472 kvmppc_define_rtas_kernel_token(0, "ibm,int-off");
473}
474
475static void xics_kvm_initfn(Object *obj)
476{
477 XICSState *xics = XICS_COMMON(obj);
478 ICSState *ics;
479
480 ics = ICS_SIMPLE(object_new(TYPE_ICS_KVM));
481 object_property_add_child(obj, "ics", OBJECT(ics), NULL);
482 ics->xics = xics;
483 QLIST_INSERT_HEAD(&xics->ics, ics, list);
484}
485
486static void xics_kvm_class_init(ObjectClass *oc, void *data)
487{
488 DeviceClass *dc = DEVICE_CLASS(oc);
489 XICSStateClass *xsc = XICS_COMMON_CLASS(oc);
490
491 dc->realize = xics_kvm_realize;
492 xsc->cpu_setup = xics_kvm_cpu_setup;
493 xsc->set_nr_irqs = xics_kvm_set_nr_irqs;
494 xsc->set_nr_servers = xics_kvm_set_nr_servers;
495}
496
497static const TypeInfo xics_spapr_kvm_info = {
498 .name = TYPE_XICS_SPAPR_KVM,
499 .parent = TYPE_XICS_COMMON,
500 .instance_size = sizeof(KVMXICSState),
501 .class_init = xics_kvm_class_init,
502 .instance_init = xics_kvm_initfn,
503};
504
505static void xics_kvm_register_types(void)
506{
507 type_register_static(&xics_spapr_kvm_info);
508 type_register_static(&ics_kvm_info);
509 type_register_static(&icp_kvm_info);
510}
511
512type_init(xics_kvm_register_types)
513