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25#include "qemu/osdep.h"
26#include <zlib.h>
27
28#include "hw/net/cadence_gem.h"
29#include "qapi/error.h"
30#include "qemu/log.h"
31#include "net/checksum.h"
32#include "exec/address-spaces.h"
33
34#ifdef CADENCE_GEM_ERR_DEBUG
35#define DB_PRINT(...) do { \
36 fprintf(stderr, ": %s: ", __func__); \
37 fprintf(stderr, ## __VA_ARGS__); \
38 } while (0);
39#else
40 #define DB_PRINT(...)
41#endif
42
43#define GEM_NWCTRL (0x00000000/4)
44#define GEM_NWCFG (0x00000004/4)
45#define GEM_NWSTATUS (0x00000008/4)
46#define GEM_USERIO (0x0000000C/4)
47#define GEM_DMACFG (0x00000010/4)
48#define GEM_TXSTATUS (0x00000014/4)
49#define GEM_RXQBASE (0x00000018/4)
50#define GEM_TXQBASE (0x0000001C/4)
51#define GEM_RXSTATUS (0x00000020/4)
52#define GEM_ISR (0x00000024/4)
53#define GEM_IER (0x00000028/4)
54#define GEM_IDR (0x0000002C/4)
55#define GEM_IMR (0x00000030/4)
56#define GEM_PHYMNTNC (0x00000034/4)
57#define GEM_RXPAUSE (0x00000038/4)
58#define GEM_TXPAUSE (0x0000003C/4)
59#define GEM_TXPARTIALSF (0x00000040/4)
60#define GEM_RXPARTIALSF (0x00000044/4)
61#define GEM_HASHLO (0x00000080/4)
62#define GEM_HASHHI (0x00000084/4)
63#define GEM_SPADDR1LO (0x00000088/4)
64#define GEM_SPADDR1HI (0x0000008C/4)
65#define GEM_SPADDR2LO (0x00000090/4)
66#define GEM_SPADDR2HI (0x00000094/4)
67#define GEM_SPADDR3LO (0x00000098/4)
68#define GEM_SPADDR3HI (0x0000009C/4)
69#define GEM_SPADDR4LO (0x000000A0/4)
70#define GEM_SPADDR4HI (0x000000A4/4)
71#define GEM_TIDMATCH1 (0x000000A8/4)
72#define GEM_TIDMATCH2 (0x000000AC/4)
73#define GEM_TIDMATCH3 (0x000000B0/4)
74#define GEM_TIDMATCH4 (0x000000B4/4)
75#define GEM_WOLAN (0x000000B8/4)
76#define GEM_IPGSTRETCH (0x000000BC/4)
77#define GEM_SVLAN (0x000000C0/4)
78#define GEM_MODID (0x000000FC/4)
79#define GEM_OCTTXLO (0x00000100/4)
80#define GEM_OCTTXHI (0x00000104/4)
81#define GEM_TXCNT (0x00000108/4)
82#define GEM_TXBCNT (0x0000010C/4)
83#define GEM_TXMCNT (0x00000110/4)
84#define GEM_TXPAUSECNT (0x00000114/4)
85#define GEM_TX64CNT (0x00000118/4)
86#define GEM_TX65CNT (0x0000011C/4)
87#define GEM_TX128CNT (0x00000120/4)
88#define GEM_TX256CNT (0x00000124/4)
89#define GEM_TX512CNT (0x00000128/4)
90#define GEM_TX1024CNT (0x0000012C/4)
91#define GEM_TX1519CNT (0x00000130/4)
92#define GEM_TXURUNCNT (0x00000134/4)
93#define GEM_SINGLECOLLCNT (0x00000138/4)
94#define GEM_MULTCOLLCNT (0x0000013C/4)
95#define GEM_EXCESSCOLLCNT (0x00000140/4)
96#define GEM_LATECOLLCNT (0x00000144/4)
97#define GEM_DEFERTXCNT (0x00000148/4)
98#define GEM_CSENSECNT (0x0000014C/4)
99#define GEM_OCTRXLO (0x00000150/4)
100#define GEM_OCTRXHI (0x00000154/4)
101#define GEM_RXCNT (0x00000158/4)
102#define GEM_RXBROADCNT (0x0000015C/4)
103#define GEM_RXMULTICNT (0x00000160/4)
104#define GEM_RXPAUSECNT (0x00000164/4)
105#define GEM_RX64CNT (0x00000168/4)
106#define GEM_RX65CNT (0x0000016C/4)
107#define GEM_RX128CNT (0x00000170/4)
108#define GEM_RX256CNT (0x00000174/4)
109#define GEM_RX512CNT (0x00000178/4)
110#define GEM_RX1024CNT (0x0000017C/4)
111#define GEM_RX1519CNT (0x00000180/4)
112#define GEM_RXUNDERCNT (0x00000184/4)
113#define GEM_RXOVERCNT (0x00000188/4)
114#define GEM_RXJABCNT (0x0000018C/4)
115#define GEM_RXFCSCNT (0x00000190/4)
116#define GEM_RXLENERRCNT (0x00000194/4)
117#define GEM_RXSYMERRCNT (0x00000198/4)
118#define GEM_RXALIGNERRCNT (0x0000019C/4)
119#define GEM_RXRSCERRCNT (0x000001A0/4)
120#define GEM_RXORUNCNT (0x000001A4/4)
121#define GEM_RXIPCSERRCNT (0x000001A8/4)
122#define GEM_RXTCPCCNT (0x000001AC/4)
123#define GEM_RXUDPCCNT (0x000001B0/4)
124
125#define GEM_1588S (0x000001D0/4)
126#define GEM_1588NS (0x000001D4/4)
127#define GEM_1588ADJ (0x000001D8/4)
128#define GEM_1588INC (0x000001DC/4)
129#define GEM_PTPETXS (0x000001E0/4)
130#define GEM_PTPETXNS (0x000001E4/4)
131#define GEM_PTPERXS (0x000001E8/4)
132#define GEM_PTPERXNS (0x000001EC/4)
133#define GEM_PTPPTXS (0x000001E0/4)
134#define GEM_PTPPTXNS (0x000001E4/4)
135#define GEM_PTPPRXS (0x000001E8/4)
136#define GEM_PTPPRXNS (0x000001EC/4)
137
138
139#define GEM_DESCONF (0x00000280/4)
140#define GEM_DESCONF2 (0x00000284/4)
141#define GEM_DESCONF3 (0x00000288/4)
142#define GEM_DESCONF4 (0x0000028C/4)
143#define GEM_DESCONF5 (0x00000290/4)
144#define GEM_DESCONF6 (0x00000294/4)
145#define GEM_DESCONF7 (0x00000298/4)
146
147#define GEM_INT_Q1_STATUS (0x00000400 / 4)
148#define GEM_INT_Q1_MASK (0x00000640 / 4)
149
150#define GEM_TRANSMIT_Q1_PTR (0x00000440 / 4)
151#define GEM_TRANSMIT_Q7_PTR (GEM_TRANSMIT_Q1_PTR + 6)
152
153#define GEM_RECEIVE_Q1_PTR (0x00000480 / 4)
154#define GEM_RECEIVE_Q7_PTR (GEM_RECEIVE_Q1_PTR + 6)
155
156#define GEM_INT_Q1_ENABLE (0x00000600 / 4)
157#define GEM_INT_Q7_ENABLE (GEM_INT_Q1_ENABLE + 6)
158
159#define GEM_INT_Q1_DISABLE (0x00000620 / 4)
160#define GEM_INT_Q7_DISABLE (GEM_INT_Q1_DISABLE + 6)
161
162#define GEM_INT_Q1_MASK (0x00000640 / 4)
163#define GEM_INT_Q7_MASK (GEM_INT_Q1_MASK + 6)
164
165#define GEM_SCREENING_TYPE1_REGISTER_0 (0x00000500 / 4)
166
167#define GEM_ST1R_UDP_PORT_MATCH_ENABLE (1 << 29)
168#define GEM_ST1R_DSTC_ENABLE (1 << 28)
169#define GEM_ST1R_UDP_PORT_MATCH_SHIFT (12)
170#define GEM_ST1R_UDP_PORT_MATCH_WIDTH (27 - GEM_ST1R_UDP_PORT_MATCH_SHIFT + 1)
171#define GEM_ST1R_DSTC_MATCH_SHIFT (4)
172#define GEM_ST1R_DSTC_MATCH_WIDTH (11 - GEM_ST1R_DSTC_MATCH_SHIFT + 1)
173#define GEM_ST1R_QUEUE_SHIFT (0)
174#define GEM_ST1R_QUEUE_WIDTH (3 - GEM_ST1R_QUEUE_SHIFT + 1)
175
176#define GEM_SCREENING_TYPE2_REGISTER_0 (0x00000540 / 4)
177
178#define GEM_ST2R_COMPARE_A_ENABLE (1 << 18)
179#define GEM_ST2R_COMPARE_A_SHIFT (13)
180#define GEM_ST2R_COMPARE_WIDTH (17 - GEM_ST2R_COMPARE_A_SHIFT + 1)
181#define GEM_ST2R_ETHERTYPE_ENABLE (1 << 12)
182#define GEM_ST2R_ETHERTYPE_INDEX_SHIFT (9)
183#define GEM_ST2R_ETHERTYPE_INDEX_WIDTH (11 - GEM_ST2R_ETHERTYPE_INDEX_SHIFT \
184 + 1)
185#define GEM_ST2R_QUEUE_SHIFT (0)
186#define GEM_ST2R_QUEUE_WIDTH (3 - GEM_ST2R_QUEUE_SHIFT + 1)
187
188#define GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 (0x000006e0 / 4)
189#define GEM_TYPE2_COMPARE_0_WORD_0 (0x00000700 / 4)
190
191#define GEM_T2CW1_COMPARE_OFFSET_SHIFT (7)
192#define GEM_T2CW1_COMPARE_OFFSET_WIDTH (8 - GEM_T2CW1_COMPARE_OFFSET_SHIFT + 1)
193#define GEM_T2CW1_OFFSET_VALUE_SHIFT (0)
194#define GEM_T2CW1_OFFSET_VALUE_WIDTH (6 - GEM_T2CW1_OFFSET_VALUE_SHIFT + 1)
195
196
197#define GEM_NWCTRL_TXSTART 0x00000200
198#define GEM_NWCTRL_TXENA 0x00000008
199#define GEM_NWCTRL_RXENA 0x00000004
200#define GEM_NWCTRL_LOCALLOOP 0x00000002
201
202#define GEM_NWCFG_STRIP_FCS 0x00020000
203#define GEM_NWCFG_LERR_DISC 0x00010000
204#define GEM_NWCFG_BUFF_OFST_M 0x0000C000
205#define GEM_NWCFG_BUFF_OFST_S 14
206#define GEM_NWCFG_UCAST_HASH 0x00000080
207#define GEM_NWCFG_MCAST_HASH 0x00000040
208#define GEM_NWCFG_BCAST_REJ 0x00000020
209#define GEM_NWCFG_PROMISC 0x00000010
210
211#define GEM_DMACFG_ADDR_BUS_WIDTH_M 0x40000000
212#define GEM_DMACFG_TX_BD_EXT (1 << 29)
213#define GEM_DMACFG_RX_BD_EXT (1 << 28)
214#define GEM_DMACFG_RBUFSZ_M 0x00FF0000
215#define GEM_DMACFG_RBUFSZ_S 16
216#define GEM_DMACFG_RBUFSZ_MUL 64
217#define GEM_DMACFG_TXCSUM_OFFL 0x00000800
218
219#define GEM_TXSTATUS_TXCMPL 0x00000020
220#define GEM_TXSTATUS_USED 0x00000001
221
222#define GEM_RXSTATUS_FRMRCVD 0x00000002
223#define GEM_RXSTATUS_NOBUF 0x00000001
224
225
226#define GEM_INT_TXCMPL 0x00000080
227#define GEM_INT_TXUSED 0x00000008
228#define GEM_INT_RXUSED 0x00000004
229#define GEM_INT_RXCMPL 0x00000002
230
231#define GEM_PHYMNTNC_OP_R 0x20000000
232#define GEM_PHYMNTNC_OP_W 0x10000000
233#define GEM_PHYMNTNC_ADDR 0x0F800000
234#define GEM_PHYMNTNC_ADDR_SHFT 23
235#define GEM_PHYMNTNC_REG 0x007C0000
236#define GEM_PHYMNTNC_REG_SHIFT 18
237
238
239#define BOARD_PHY_ADDRESS 7
240
241#define PHY_REG_CONTROL 0
242#define PHY_REG_STATUS 1
243#define PHY_REG_PHYID1 2
244#define PHY_REG_PHYID2 3
245#define PHY_REG_ANEGADV 4
246#define PHY_REG_LINKPABIL 5
247#define PHY_REG_ANEGEXP 6
248#define PHY_REG_NEXTP 7
249#define PHY_REG_LINKPNEXTP 8
250#define PHY_REG_100BTCTRL 9
251#define PHY_REG_1000BTSTAT 10
252#define PHY_REG_EXTSTAT 15
253#define PHY_REG_PHYSPCFC_CTL 16
254#define PHY_REG_PHYSPCFC_ST 17
255#define PHY_REG_INT_EN 18
256#define PHY_REG_INT_ST 19
257#define PHY_REG_EXT_PHYSPCFC_CTL 20
258#define PHY_REG_RXERR 21
259#define PHY_REG_EACD 22
260#define PHY_REG_LED 24
261#define PHY_REG_LED_OVRD 25
262#define PHY_REG_EXT_PHYSPCFC_CTL2 26
263#define PHY_REG_EXT_PHYSPCFC_ST 27
264#define PHY_REG_CABLE_DIAG 28
265
266#define PHY_REG_CONTROL_RST 0x8000
267#define PHY_REG_CONTROL_LOOP 0x4000
268#define PHY_REG_CONTROL_ANEG 0x1000
269
270#define PHY_REG_STATUS_LINK 0x0004
271#define PHY_REG_STATUS_ANEGCMPL 0x0020
272
273#define PHY_REG_INT_ST_ANEGCMPL 0x0800
274#define PHY_REG_INT_ST_LINKC 0x0400
275#define PHY_REG_INT_ST_ENERGY 0x0010
276
277
278#define GEM_RX_REJECT (-1)
279#define GEM_RX_PROMISCUOUS_ACCEPT (-2)
280#define GEM_RX_BROADCAST_ACCEPT (-3)
281#define GEM_RX_MULTICAST_HASH_ACCEPT (-4)
282#define GEM_RX_UNICAST_HASH_ACCEPT (-5)
283
284#define GEM_RX_SAR_ACCEPT 0
285
286
287
288#define DESC_1_USED 0x80000000
289#define DESC_1_LENGTH 0x00003FFF
290
291#define DESC_1_TX_WRAP 0x40000000
292#define DESC_1_TX_LAST 0x00008000
293
294#define DESC_0_RX_WRAP 0x00000002
295#define DESC_0_RX_OWNERSHIP 0x00000001
296
297#define R_DESC_1_RX_SAR_SHIFT 25
298#define R_DESC_1_RX_SAR_LENGTH 2
299#define R_DESC_1_RX_SAR_MATCH (1 << 27)
300#define R_DESC_1_RX_UNICAST_HASH (1 << 29)
301#define R_DESC_1_RX_MULTICAST_HASH (1 << 30)
302#define R_DESC_1_RX_BROADCAST (1 << 31)
303
304#define DESC_1_RX_SOF 0x00004000
305#define DESC_1_RX_EOF 0x00008000
306
307#define GEM_MODID_VALUE 0x00020118
308
309static inline uint64_t tx_desc_get_buffer(CadenceGEMState *s, unsigned *desc)
310{
311 uint64_t ret = desc[0];
312
313 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TX_BD_EXT) {
314 ret |= (uint64_t)desc[2] << 32;
315 }
316 return ret;
317}
318
319static inline unsigned tx_desc_get_used(unsigned *desc)
320{
321 return (desc[1] & DESC_1_USED) ? 1 : 0;
322}
323
324static inline void tx_desc_set_used(unsigned *desc)
325{
326 desc[1] |= DESC_1_USED;
327}
328
329static inline unsigned tx_desc_get_wrap(unsigned *desc)
330{
331 return (desc[1] & DESC_1_TX_WRAP) ? 1 : 0;
332}
333
334static inline unsigned tx_desc_get_last(unsigned *desc)
335{
336 return (desc[1] & DESC_1_TX_LAST) ? 1 : 0;
337}
338
339static inline void tx_desc_set_last(unsigned *desc)
340{
341 desc[1] |= DESC_1_TX_LAST;
342}
343
344static inline unsigned tx_desc_get_length(unsigned *desc)
345{
346 return desc[1] & DESC_1_LENGTH;
347}
348
349static inline void print_gem_tx_desc(unsigned *desc, uint8_t queue)
350{
351 DB_PRINT("TXDESC (queue %" PRId8 "):\n", queue);
352 DB_PRINT("bufaddr: 0x%08x\n", *desc);
353 DB_PRINT("used_hw: %d\n", tx_desc_get_used(desc));
354 DB_PRINT("wrap: %d\n", tx_desc_get_wrap(desc));
355 DB_PRINT("last: %d\n", tx_desc_get_last(desc));
356 DB_PRINT("length: %d\n", tx_desc_get_length(desc));
357}
358
359static inline uint64_t rx_desc_get_buffer(CadenceGEMState * s, unsigned *desc)
360{
361 uint64_t ret = desc[0] & ~0x3UL;
362
363 if (s->regs[GEM_DMACFG] & GEM_DMACFG_RX_BD_EXT) {
364 ret |= (uint64_t)desc[2] << 32;
365 }
366 return ret;
367}
368
369static inline int gem_get_desc_len(CadenceGEMState *s, bool rx_n_tx)
370{
371 int ret = 2;
372
373 if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_BUS_WIDTH_M) {
374 ret += 2;
375 }
376 if (s->regs[GEM_DMACFG] & (rx_n_tx ? GEM_DMACFG_RX_BD_EXT
377 : GEM_DMACFG_TX_BD_EXT)) {
378 ret += 2;
379 }
380 return ret;
381}
382
383static inline unsigned rx_desc_get_wrap(unsigned *desc)
384{
385 return desc[0] & DESC_0_RX_WRAP ? 1 : 0;
386}
387
388static inline unsigned rx_desc_get_ownership(unsigned *desc)
389{
390 return desc[0] & DESC_0_RX_OWNERSHIP ? 1 : 0;
391}
392
393static inline void rx_desc_set_ownership(unsigned *desc)
394{
395 desc[0] |= DESC_0_RX_OWNERSHIP;
396}
397
398static inline void rx_desc_set_sof(unsigned *desc)
399{
400 desc[1] |= DESC_1_RX_SOF;
401}
402
403static inline void rx_desc_set_eof(unsigned *desc)
404{
405 desc[1] |= DESC_1_RX_EOF;
406}
407
408static inline void rx_desc_set_length(unsigned *desc, unsigned len)
409{
410 desc[1] &= ~DESC_1_LENGTH;
411 desc[1] |= len;
412}
413
414static inline void rx_desc_set_broadcast(unsigned *desc)
415{
416 desc[1] |= R_DESC_1_RX_BROADCAST;
417}
418
419static inline void rx_desc_set_unicast_hash(unsigned *desc)
420{
421 desc[1] |= R_DESC_1_RX_UNICAST_HASH;
422}
423
424static inline void rx_desc_set_multicast_hash(unsigned *desc)
425{
426 desc[1] |= R_DESC_1_RX_MULTICAST_HASH;
427}
428
429static inline void rx_desc_set_sar(unsigned *desc, int sar_idx)
430{
431 desc[1] = deposit32(desc[1], R_DESC_1_RX_SAR_SHIFT, R_DESC_1_RX_SAR_LENGTH,
432 sar_idx);
433 desc[1] |= R_DESC_1_RX_SAR_MATCH;
434}
435
436
437static const uint8_t broadcast_addr[] = { 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
438
439
440
441
442
443
444static void gem_init_register_masks(CadenceGEMState *s)
445{
446
447 memset(&s->regs_ro[0], 0, sizeof(s->regs_ro));
448 s->regs_ro[GEM_NWCTRL] = 0xFFF80000;
449 s->regs_ro[GEM_NWSTATUS] = 0xFFFFFFFF;
450 s->regs_ro[GEM_DMACFG] = 0x8E00F000;
451 s->regs_ro[GEM_TXSTATUS] = 0xFFFFFE08;
452 s->regs_ro[GEM_RXQBASE] = 0x00000003;
453 s->regs_ro[GEM_TXQBASE] = 0x00000003;
454 s->regs_ro[GEM_RXSTATUS] = 0xFFFFFFF0;
455 s->regs_ro[GEM_ISR] = 0xFFFFFFFF;
456 s->regs_ro[GEM_IMR] = 0xFFFFFFFF;
457 s->regs_ro[GEM_MODID] = 0xFFFFFFFF;
458
459
460 memset(&s->regs_rtc[0], 0, sizeof(s->regs_rtc));
461 s->regs_rtc[GEM_ISR] = 0xFFFFFFFF;
462
463
464 memset(&s->regs_w1c[0], 0, sizeof(s->regs_w1c));
465 s->regs_w1c[GEM_TXSTATUS] = 0x000001F7;
466 s->regs_w1c[GEM_RXSTATUS] = 0x0000000F;
467
468
469 memset(&s->regs_wo[0], 0, sizeof(s->regs_wo));
470 s->regs_wo[GEM_NWCTRL] = 0x00073E60;
471 s->regs_wo[GEM_IER] = 0x07FFFFFF;
472 s->regs_wo[GEM_IDR] = 0x07FFFFFF;
473}
474
475
476
477
478
479static void phy_update_link(CadenceGEMState *s)
480{
481 DB_PRINT("down %d\n", qemu_get_queue(s->nic)->link_down);
482
483
484 if (qemu_get_queue(s->nic)->link_down) {
485 s->phy_regs[PHY_REG_STATUS] &= ~(PHY_REG_STATUS_ANEGCMPL |
486 PHY_REG_STATUS_LINK);
487 s->phy_regs[PHY_REG_INT_ST] |= PHY_REG_INT_ST_LINKC;
488 } else {
489 s->phy_regs[PHY_REG_STATUS] |= (PHY_REG_STATUS_ANEGCMPL |
490 PHY_REG_STATUS_LINK);
491 s->phy_regs[PHY_REG_INT_ST] |= (PHY_REG_INT_ST_LINKC |
492 PHY_REG_INT_ST_ANEGCMPL |
493 PHY_REG_INT_ST_ENERGY);
494 }
495}
496
497static int gem_can_receive(NetClientState *nc)
498{
499 CadenceGEMState *s;
500 int i;
501
502 s = qemu_get_nic_opaque(nc);
503
504
505 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_RXENA)) {
506 if (s->can_rx_state != 1) {
507 s->can_rx_state = 1;
508 DB_PRINT("can't receive - no enable\n");
509 }
510 return 0;
511 }
512
513 for (i = 0; i < s->num_priority_queues; i++) {
514 if (rx_desc_get_ownership(s->rx_desc[i]) != 1) {
515 break;
516 }
517 };
518
519 if (i == s->num_priority_queues) {
520 if (s->can_rx_state != 2) {
521 s->can_rx_state = 2;
522 DB_PRINT("can't receive - all the buffer descriptors are busy\n");
523 }
524 return 0;
525 }
526
527 if (s->can_rx_state != 0) {
528 s->can_rx_state = 0;
529 DB_PRINT("can receive\n");
530 }
531 return 1;
532}
533
534
535
536
537
538static void gem_update_int_status(CadenceGEMState *s)
539{
540 int i;
541
542 if (!s->regs[GEM_ISR]) {
543
544 for (i = 0; i < s->num_priority_queues; ++i) {
545 qemu_set_irq(s->irq[i], 0);
546 }
547 return;
548 }
549
550
551
552
553 if (s->num_priority_queues == 1) {
554
555 DB_PRINT("asserting int.\n");
556 qemu_set_irq(s->irq[0], 1);
557 return;
558 }
559
560 for (i = 0; i < s->num_priority_queues; ++i) {
561 if (s->regs[GEM_INT_Q1_STATUS + i]) {
562 DB_PRINT("asserting int. (q=%d)\n", i);
563 qemu_set_irq(s->irq[i], 1);
564 }
565 }
566}
567
568
569
570
571
572static void gem_receive_updatestats(CadenceGEMState *s, const uint8_t *packet,
573 unsigned bytes)
574{
575 uint64_t octets;
576
577
578 octets = ((uint64_t)(s->regs[GEM_OCTRXLO]) << 32) |
579 s->regs[GEM_OCTRXHI];
580 octets += bytes;
581 s->regs[GEM_OCTRXLO] = octets >> 32;
582 s->regs[GEM_OCTRXHI] = octets;
583
584
585 s->regs[GEM_RXCNT]++;
586
587
588 if (!memcmp(packet, broadcast_addr, 6)) {
589 s->regs[GEM_RXBROADCNT]++;
590 }
591
592
593 if (packet[0] == 0x01) {
594 s->regs[GEM_RXMULTICNT]++;
595 }
596
597 if (bytes <= 64) {
598 s->regs[GEM_RX64CNT]++;
599 } else if (bytes <= 127) {
600 s->regs[GEM_RX65CNT]++;
601 } else if (bytes <= 255) {
602 s->regs[GEM_RX128CNT]++;
603 } else if (bytes <= 511) {
604 s->regs[GEM_RX256CNT]++;
605 } else if (bytes <= 1023) {
606 s->regs[GEM_RX512CNT]++;
607 } else if (bytes <= 1518) {
608 s->regs[GEM_RX1024CNT]++;
609 } else {
610 s->regs[GEM_RX1519CNT]++;
611 }
612}
613
614
615
616
617static unsigned get_bit(const uint8_t *mac, unsigned bit)
618{
619 unsigned byte;
620
621 byte = mac[bit / 8];
622 byte >>= (bit & 0x7);
623 byte &= 1;
624
625 return byte;
626}
627
628
629
630
631static unsigned calc_mac_hash(const uint8_t *mac)
632{
633 int index_bit, mac_bit;
634 unsigned hash_index;
635
636 hash_index = 0;
637 mac_bit = 5;
638 for (index_bit = 5; index_bit >= 0; index_bit--) {
639 hash_index |= (get_bit(mac, mac_bit) ^
640 get_bit(mac, mac_bit + 6) ^
641 get_bit(mac, mac_bit + 12) ^
642 get_bit(mac, mac_bit + 18) ^
643 get_bit(mac, mac_bit + 24) ^
644 get_bit(mac, mac_bit + 30) ^
645 get_bit(mac, mac_bit + 36) ^
646 get_bit(mac, mac_bit + 42)) << index_bit;
647 mac_bit--;
648 }
649
650 return hash_index;
651}
652
653
654
655
656
657
658
659
660
661
662
663static int gem_mac_address_filter(CadenceGEMState *s, const uint8_t *packet)
664{
665 uint8_t *gem_spaddr;
666 int i;
667
668
669 if (s->regs[GEM_NWCFG] & GEM_NWCFG_PROMISC) {
670 return GEM_RX_PROMISCUOUS_ACCEPT;
671 }
672
673 if (!memcmp(packet, broadcast_addr, 6)) {
674
675 if (s->regs[GEM_NWCFG] & GEM_NWCFG_BCAST_REJ) {
676 return GEM_RX_REJECT;
677 }
678 return GEM_RX_BROADCAST_ACCEPT;
679 }
680
681
682 if ((packet[0] == 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_MCAST_HASH)) ||
683 (packet[0] != 0x01 && (s->regs[GEM_NWCFG] & GEM_NWCFG_UCAST_HASH))) {
684 unsigned hash_index;
685
686 hash_index = calc_mac_hash(packet);
687 if (hash_index < 32) {
688 if (s->regs[GEM_HASHLO] & (1<<hash_index)) {
689 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
690 GEM_RX_UNICAST_HASH_ACCEPT;
691 }
692 } else {
693 hash_index -= 32;
694 if (s->regs[GEM_HASHHI] & (1<<hash_index)) {
695 return packet[0] == 0x01 ? GEM_RX_MULTICAST_HASH_ACCEPT :
696 GEM_RX_UNICAST_HASH_ACCEPT;
697 }
698 }
699 }
700
701
702 gem_spaddr = (uint8_t *)&(s->regs[GEM_SPADDR1LO]);
703 for (i = 3; i >= 0; i--) {
704 if (s->sar_active[i] && !memcmp(packet, gem_spaddr + 8 * i, 6)) {
705 return GEM_RX_SAR_ACCEPT + i;
706 }
707 }
708
709
710 return GEM_RX_REJECT;
711}
712
713
714static int get_queue_from_screen(CadenceGEMState *s, uint8_t *rxbuf_ptr,
715 unsigned rxbufsize)
716{
717 uint32_t reg;
718 bool matched, mismatched;
719 int i, j;
720
721 for (i = 0; i < s->num_type1_screeners; i++) {
722 reg = s->regs[GEM_SCREENING_TYPE1_REGISTER_0 + i];
723 matched = false;
724 mismatched = false;
725
726
727 if (reg & GEM_ST1R_UDP_PORT_MATCH_ENABLE) {
728 uint16_t udp_port = rxbuf_ptr[14 + 22] << 8 | rxbuf_ptr[14 + 23];
729 if (udp_port == extract32(reg, GEM_ST1R_UDP_PORT_MATCH_SHIFT,
730 GEM_ST1R_UDP_PORT_MATCH_WIDTH)) {
731 matched = true;
732 } else {
733 mismatched = true;
734 }
735 }
736
737
738 if (reg & GEM_ST1R_DSTC_ENABLE) {
739 uint8_t dscp = rxbuf_ptr[14 + 1];
740 if (dscp == extract32(reg, GEM_ST1R_DSTC_MATCH_SHIFT,
741 GEM_ST1R_DSTC_MATCH_WIDTH)) {
742 matched = true;
743 } else {
744 mismatched = true;
745 }
746 }
747
748 if (matched && !mismatched) {
749 return extract32(reg, GEM_ST1R_QUEUE_SHIFT, GEM_ST1R_QUEUE_WIDTH);
750 }
751 }
752
753 for (i = 0; i < s->num_type2_screeners; i++) {
754 reg = s->regs[GEM_SCREENING_TYPE2_REGISTER_0 + i];
755 matched = false;
756 mismatched = false;
757
758 if (reg & GEM_ST2R_ETHERTYPE_ENABLE) {
759 uint16_t type = rxbuf_ptr[12] << 8 | rxbuf_ptr[13];
760 int et_idx = extract32(reg, GEM_ST2R_ETHERTYPE_INDEX_SHIFT,
761 GEM_ST2R_ETHERTYPE_INDEX_WIDTH);
762
763 if (et_idx > s->num_type2_screeners) {
764 qemu_log_mask(LOG_GUEST_ERROR, "Out of range ethertype "
765 "register index: %d\n", et_idx);
766 }
767 if (type == s->regs[GEM_SCREENING_TYPE2_ETHERTYPE_REG_0 +
768 et_idx]) {
769 matched = true;
770 } else {
771 mismatched = true;
772 }
773 }
774
775
776 for (j = 0; j < 3; j++) {
777 uint32_t cr0, cr1, mask;
778 uint16_t rx_cmp;
779 int offset;
780 int cr_idx = extract32(reg, GEM_ST2R_COMPARE_A_SHIFT + j * 6,
781 GEM_ST2R_COMPARE_WIDTH);
782
783 if (!(reg & (GEM_ST2R_COMPARE_A_ENABLE << (j * 6)))) {
784 continue;
785 }
786 if (cr_idx > s->num_type2_screeners) {
787 qemu_log_mask(LOG_GUEST_ERROR, "Out of range compare "
788 "register index: %d\n", cr_idx);
789 }
790
791 cr0 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2];
792 cr1 = s->regs[GEM_TYPE2_COMPARE_0_WORD_0 + cr_idx * 2 + 1];
793 offset = extract32(cr1, GEM_T2CW1_OFFSET_VALUE_SHIFT,
794 GEM_T2CW1_OFFSET_VALUE_WIDTH);
795
796 switch (extract32(cr1, GEM_T2CW1_COMPARE_OFFSET_SHIFT,
797 GEM_T2CW1_COMPARE_OFFSET_WIDTH)) {
798 case 3:
799 qemu_log_mask(LOG_UNIMP, "TCP compare offsets"
800 "unimplemented - assuming UDP\n");
801 offset += 8;
802
803 case 2:
804 offset += 20;
805
806 case 1:
807 offset += 14;
808 break;
809 case 0:
810
811 break;
812 }
813
814 rx_cmp = rxbuf_ptr[offset] << 8 | rxbuf_ptr[offset];
815 mask = extract32(cr0, 0, 16);
816
817 if ((rx_cmp & mask) == (extract32(cr0, 16, 16) & mask)) {
818 matched = true;
819 } else {
820 mismatched = true;
821 }
822 }
823
824 if (matched && !mismatched) {
825 return extract32(reg, GEM_ST2R_QUEUE_SHIFT, GEM_ST2R_QUEUE_WIDTH);
826 }
827 }
828
829
830 return 0;
831}
832
833static void gem_get_rx_desc(CadenceGEMState *s, int q)
834{
835 DB_PRINT("read descriptor 0x%x\n", (unsigned)s->rx_desc_addr[q]);
836
837 address_space_rw(s->dma_as, s->rx_desc_addr[q], *s->attr,
838 (uint8_t *)s->rx_desc[q],
839 sizeof(uint32_t) * gem_get_desc_len(s, true), false);
840
841
842 if (rx_desc_get_ownership(s->rx_desc[q]) == 1) {
843 DB_PRINT("descriptor 0x%x owned by sw.\n",
844 (unsigned)s->rx_desc_addr[q]);
845 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_NOBUF;
846 s->regs[GEM_ISR] |= GEM_INT_RXUSED & ~(s->regs[GEM_IMR]);
847
848 gem_update_int_status(s);
849 }
850}
851
852
853
854
855
856static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
857{
858 CadenceGEMState *s;
859 unsigned rxbufsize, bytes_to_copy;
860 unsigned rxbuf_offset;
861 uint8_t rxbuf[2048];
862 uint8_t *rxbuf_ptr;
863 bool first_desc = true;
864 int maf;
865 int q = 0;
866
867 s = qemu_get_nic_opaque(nc);
868
869
870 maf = gem_mac_address_filter(s, buf);
871 if (maf == GEM_RX_REJECT) {
872 return -1;
873 }
874
875
876 if (s->regs[GEM_NWCFG] & GEM_NWCFG_LERR_DISC) {
877 unsigned type_len;
878
879
880 type_len = buf[12] << 8 | buf[13];
881
882 if (type_len < 0x600) {
883 if (size < type_len) {
884
885 return -1;
886 }
887 }
888 }
889
890
891
892
893 rxbuf_offset = (s->regs[GEM_NWCFG] & GEM_NWCFG_BUFF_OFST_M) >>
894 GEM_NWCFG_BUFF_OFST_S;
895
896
897
898
899 rxbufsize = ((s->regs[GEM_DMACFG] & GEM_DMACFG_RBUFSZ_M) >>
900 GEM_DMACFG_RBUFSZ_S) * GEM_DMACFG_RBUFSZ_MUL;
901 bytes_to_copy = size;
902
903
904
905
906 if (rxbufsize < GEM_DMACFG_RBUFSZ_MUL) {
907 rxbufsize = GEM_DMACFG_RBUFSZ_MUL;
908 }
909
910
911
912
913
914 if (size < 60) {
915 size = 60;
916 }
917
918
919 if (s->regs[GEM_NWCFG] & GEM_NWCFG_STRIP_FCS) {
920 rxbuf_ptr = (void *)buf;
921 } else {
922 unsigned crc_val;
923
924 if (size > sizeof(rxbuf) - sizeof(crc_val)) {
925 size = sizeof(rxbuf) - sizeof(crc_val);
926 }
927 bytes_to_copy = size;
928
929
930
931
932 memcpy(rxbuf, buf, size);
933 memset(rxbuf + size, 0, sizeof(rxbuf) - size);
934 rxbuf_ptr = rxbuf;
935 crc_val = cpu_to_le32(crc32(0, rxbuf, MAX(size, 60)));
936 memcpy(rxbuf + size, &crc_val, sizeof(crc_val));
937
938 bytes_to_copy += 4;
939 size += 4;
940 }
941
942 DB_PRINT("config bufsize: %d packet size: %ld\n", rxbufsize, size);
943
944
945 q = get_queue_from_screen(s, rxbuf_ptr, rxbufsize);
946
947 while (bytes_to_copy) {
948
949 if (!gem_can_receive(nc)) {
950 assert(!first_desc);
951 return -1;
952 }
953
954 DB_PRINT("copy %d bytes to 0x%" PRIx64 "\n",
955 MIN(bytes_to_copy, rxbufsize),
956 rx_desc_get_buffer(s, s->rx_desc[q]));
957
958
959 address_space_rw(s->dma_as, rx_desc_get_buffer(s, s->rx_desc[q]) +
960 rxbuf_offset,
961 *s->attr, rxbuf_ptr,
962 MIN(bytes_to_copy, rxbufsize), true);
963 rxbuf_ptr += MIN(bytes_to_copy, rxbufsize);
964 bytes_to_copy -= MIN(bytes_to_copy, rxbufsize);
965
966
967 if (first_desc) {
968 rx_desc_set_sof(s->rx_desc[q]);
969 first_desc = false;
970 }
971 if (bytes_to_copy == 0) {
972 rx_desc_set_eof(s->rx_desc[q]);
973 rx_desc_set_length(s->rx_desc[q], size);
974 }
975 rx_desc_set_ownership(s->rx_desc[q]);
976
977 switch (maf) {
978 case GEM_RX_PROMISCUOUS_ACCEPT:
979 break;
980 case GEM_RX_BROADCAST_ACCEPT:
981 rx_desc_set_broadcast(s->rx_desc[q]);
982 break;
983 case GEM_RX_UNICAST_HASH_ACCEPT:
984 rx_desc_set_unicast_hash(s->rx_desc[q]);
985 break;
986 case GEM_RX_MULTICAST_HASH_ACCEPT:
987 rx_desc_set_multicast_hash(s->rx_desc[q]);
988 break;
989 case GEM_RX_REJECT:
990 abort();
991 default:
992 rx_desc_set_sar(s->rx_desc[q], maf);
993 }
994
995
996 address_space_rw(s->dma_as, s->rx_desc_addr[q], *s->attr,
997 (uint8_t *)s->rx_desc[q],
998 sizeof(uint32_t) * gem_get_desc_len(s, true), true);
999
1000
1001 if (rx_desc_get_wrap(s->rx_desc[q])) {
1002 DB_PRINT("wrapping RX descriptor list\n");
1003 s->rx_desc_addr[q] = s->regs[GEM_RXQBASE];
1004 } else {
1005 DB_PRINT("incrementing RX descriptor list\n");
1006 s->rx_desc_addr[q] += 4 * gem_get_desc_len(s, true);
1007 }
1008
1009 gem_get_rx_desc(s, q);
1010 }
1011
1012
1013 gem_receive_updatestats(s, buf, size);
1014
1015 s->regs[GEM_RXSTATUS] |= GEM_RXSTATUS_FRMRCVD;
1016 s->regs[GEM_ISR] |= GEM_INT_RXCMPL & ~(s->regs[GEM_IMR]);
1017
1018
1019 gem_update_int_status(s);
1020
1021 return size;
1022}
1023
1024
1025
1026
1027
1028static void gem_transmit_updatestats(CadenceGEMState *s, const uint8_t *packet,
1029 unsigned bytes)
1030{
1031 uint64_t octets;
1032
1033
1034 octets = ((uint64_t)(s->regs[GEM_OCTTXLO]) << 32) |
1035 s->regs[GEM_OCTTXHI];
1036 octets += bytes;
1037 s->regs[GEM_OCTTXLO] = octets >> 32;
1038 s->regs[GEM_OCTTXHI] = octets;
1039
1040
1041 s->regs[GEM_TXCNT]++;
1042
1043
1044 if (!memcmp(packet, broadcast_addr, 6)) {
1045 s->regs[GEM_TXBCNT]++;
1046 }
1047
1048
1049 if (packet[0] == 0x01) {
1050 s->regs[GEM_TXMCNT]++;
1051 }
1052
1053 if (bytes <= 64) {
1054 s->regs[GEM_TX64CNT]++;
1055 } else if (bytes <= 127) {
1056 s->regs[GEM_TX65CNT]++;
1057 } else if (bytes <= 255) {
1058 s->regs[GEM_TX128CNT]++;
1059 } else if (bytes <= 511) {
1060 s->regs[GEM_TX256CNT]++;
1061 } else if (bytes <= 1023) {
1062 s->regs[GEM_TX512CNT]++;
1063 } else if (bytes <= 1518) {
1064 s->regs[GEM_TX1024CNT]++;
1065 } else {
1066 s->regs[GEM_TX1519CNT]++;
1067 }
1068}
1069
1070
1071
1072
1073
1074static void gem_transmit(CadenceGEMState *s)
1075{
1076 unsigned desc[4];
1077 hwaddr packet_desc_addr;
1078 uint8_t tx_packet[2048];
1079 uint8_t *p;
1080 unsigned total_bytes;
1081 int q = 0;
1082
1083
1084 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1085 return;
1086 }
1087
1088 DB_PRINT("\n");
1089
1090
1091
1092
1093
1094 p = tx_packet;
1095 total_bytes = 0;
1096
1097 for (q = s->num_priority_queues - 1; q >= 0; q--) {
1098
1099 packet_desc_addr = s->tx_desc_addr[q];
1100
1101 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1102 address_space_rw(s->dma_as, packet_desc_addr, *s->attr,
1103 (uint8_t *)desc,
1104 sizeof(uint32_t) * gem_get_desc_len(s, false),
1105 false);
1106
1107 while (tx_desc_get_used(desc) == 0) {
1108
1109
1110 if (!(s->regs[GEM_NWCTRL] & GEM_NWCTRL_TXENA)) {
1111 return;
1112 }
1113 print_gem_tx_desc(desc, q);
1114
1115
1116
1117
1118 if ((tx_desc_get_buffer(s, desc) == 0) ||
1119 (tx_desc_get_length(desc) == 0)) {
1120 DB_PRINT("Invalid TX descriptor @ 0x%x\n",
1121 (unsigned)packet_desc_addr);
1122 break;
1123 }
1124
1125 if (tx_desc_get_length(desc) > sizeof(tx_packet) -
1126 (p - tx_packet)) {
1127 DB_PRINT("TX descriptor @ 0x%x too large: size 0x%x space " \
1128 "0x%lx\n", (unsigned)packet_desc_addr,
1129 (unsigned)tx_desc_get_length(desc),
1130 sizeof(tx_packet) - (p - tx_packet));
1131 break;
1132 }
1133
1134
1135
1136
1137 address_space_rw(s->dma_as, tx_desc_get_buffer(s, desc), *s->attr,
1138 p, tx_desc_get_length(desc), false);
1139 p += tx_desc_get_length(desc);
1140 total_bytes += tx_desc_get_length(desc);
1141
1142
1143 if (tx_desc_get_last(desc)) {
1144 unsigned desc_first[2];
1145
1146
1147
1148
1149 address_space_rw(s->dma_as, s->tx_desc_addr[q], *s->attr,
1150 (uint8_t *)desc_first, sizeof(desc_first),
1151 false);
1152 tx_desc_set_used(desc_first);
1153 address_space_rw(s->dma_as, s->tx_desc_addr[q], *s->attr,
1154 (uint8_t *)desc_first, sizeof(desc_first),
1155 true);
1156
1157 if (tx_desc_get_wrap(desc)) {
1158 s->tx_desc_addr[q] = s->regs[GEM_TXQBASE];
1159 } else {
1160 s->tx_desc_addr[q] = packet_desc_addr +
1161 4 * gem_get_desc_len(s, false);
1162 }
1163 DB_PRINT("TX descriptor next: 0x%08x\n", s->tx_desc_addr[q]);
1164
1165 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_TXCMPL;
1166 s->regs[GEM_ISR] |= GEM_INT_TXCMPL & ~(s->regs[GEM_IMR]);
1167
1168
1169 if (s->num_priority_queues > 1) {
1170 s->regs[GEM_INT_Q1_STATUS + q] |=
1171 GEM_INT_TXCMPL & ~(s->regs[GEM_INT_Q1_MASK + q]);
1172 }
1173
1174
1175 gem_update_int_status(s);
1176
1177
1178 if (s->regs[GEM_DMACFG] & GEM_DMACFG_TXCSUM_OFFL) {
1179 net_checksum_calculate(tx_packet, total_bytes);
1180 }
1181
1182
1183 gem_transmit_updatestats(s, tx_packet, total_bytes);
1184
1185
1186 if (s->phy_loop || (s->regs[GEM_NWCTRL] &
1187 GEM_NWCTRL_LOCALLOOP)) {
1188 gem_receive(qemu_get_queue(s->nic), tx_packet,
1189 total_bytes);
1190 } else {
1191 qemu_send_packet(qemu_get_queue(s->nic), tx_packet,
1192 total_bytes);
1193 }
1194
1195
1196 p = tx_packet;
1197 total_bytes = 0;
1198 }
1199
1200
1201 if (tx_desc_get_wrap(desc)) {
1202 tx_desc_set_last(desc);
1203 packet_desc_addr = s->regs[GEM_TXQBASE];
1204 } else {
1205 packet_desc_addr += 4 * gem_get_desc_len(s, false);
1206 }
1207 DB_PRINT("read descriptor 0x%" HWADDR_PRIx "\n", packet_desc_addr);
1208 address_space_rw(s->dma_as, packet_desc_addr, *s->attr,
1209 (uint8_t *)desc,
1210 sizeof(uint32_t) * gem_get_desc_len(s, false),
1211 false);
1212 }
1213
1214 if (tx_desc_get_used(desc)) {
1215 s->regs[GEM_TXSTATUS] |= GEM_TXSTATUS_USED;
1216 s->regs[GEM_ISR] |= GEM_INT_TXUSED & ~(s->regs[GEM_IMR]);
1217 gem_update_int_status(s);
1218 }
1219 }
1220
1221 phy_update_link(s);
1222}
1223
1224static void gem_reset(DeviceState *d)
1225{
1226 int i;
1227 CadenceGEMState *s = CADENCE_GEM(d);
1228 const uint8_t *a;
1229
1230 DB_PRINT("\n");
1231
1232
1233 memset(&s->regs[0], 0, sizeof(s->regs));
1234 s->regs[GEM_NWCFG] = 0x00080000;
1235 s->regs[GEM_NWSTATUS] = 0x00000006;
1236 s->regs[GEM_DMACFG] = 0x00020784;
1237 s->regs[GEM_IMR] = 0x07ffffff;
1238 s->regs[GEM_TXPAUSE] = 0x0000ffff;
1239 s->regs[GEM_TXPARTIALSF] = 0x000003ff;
1240 s->regs[GEM_RXPARTIALSF] = 0x000003ff;
1241 s->regs[GEM_MODID] = s->revision;
1242 s->regs[GEM_DESCONF] = 0x02500111;
1243 s->regs[GEM_DESCONF2] = 0x2ab13fff;
1244 s->regs[GEM_DESCONF5] = 0x002f2145;
1245 s->regs[GEM_DESCONF6] = 0x00000200;
1246
1247
1248 a = &s->conf.macaddr.a[0];
1249 s->regs[GEM_SPADDR1LO] = a[0] | (a[1] << 8) | (a[2] << 16) | (a[3] << 24);
1250 s->regs[GEM_SPADDR1HI] = a[4] | (a[5] << 8);
1251
1252 for (i = 0; i < 4; i++) {
1253 s->sar_active[i] = false;
1254 }
1255
1256 phy_update_link(s);
1257 gem_update_int_status(s);
1258}
1259
1260static void gem_phy_loopback_setup(CadenceGEMState *s, unsigned reg_num,
1261 uint16_t val)
1262{
1263 switch (reg_num) {
1264 case PHY_REG_CONTROL:
1265 if (val & PHY_REG_CONTROL_RST) {
1266
1267 s->phy_loop = 0;
1268 }
1269 if (val & PHY_REG_CONTROL_LOOP) {
1270 DB_PRINT("PHY placed in loopback\n");
1271 s->phy_loop = 1;
1272 } else {
1273 s->phy_loop = 0;
1274 }
1275 break;
1276 }
1277}
1278
1279
1280
1281
1282
1283static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
1284{
1285 CadenceGEMState *s;
1286 uint32_t retval;
1287 s = (CadenceGEMState *)opaque;
1288
1289 offset >>= 2;
1290 retval = s->regs[offset];
1291
1292 DB_PRINT("offset: 0x%04x read: 0x%08x\n", (unsigned)offset*4, retval);
1293
1294 switch (offset) {
1295 case GEM_ISR:
1296 DB_PRINT("lowering irqs on ISR read\n");
1297 gem_update_int_status(s);
1298 break;
1299 case GEM_PHYMNTNC:
1300 if (retval & GEM_PHYMNTNC_OP_R) {
1301 uint32_t phy_addr, reg_num;
1302
1303 phy_addr = (retval & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1304 reg_num = (retval & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1305 retval &= 0xFFFF0000;
1306 if (s->mdio) {
1307 retval |= s->mdio->read(s->mdio, phy_addr, reg_num);
1308 }
1309 }
1310 break;
1311 }
1312
1313
1314 s->regs[offset] &= ~(s->regs_rtc[offset]);
1315
1316
1317 retval &= ~(s->regs_wo[offset]);
1318
1319 DB_PRINT("0x%08x\n", retval);
1320 gem_update_int_status(s);
1321 return retval;
1322}
1323
1324
1325
1326
1327
1328static void gem_write(void *opaque, hwaddr offset, uint64_t val,
1329 unsigned size)
1330{
1331 CadenceGEMState *s = (CadenceGEMState *)opaque;
1332 uint32_t readonly;
1333 int i;
1334
1335 DB_PRINT("offset: 0x%04x write: 0x%08x ", (unsigned)offset, (unsigned)val);
1336 offset >>= 2;
1337
1338
1339 val &= ~(s->regs_ro[offset]);
1340
1341 readonly = s->regs[offset] & (s->regs_ro[offset] | s->regs_w1c[offset]);
1342
1343
1344 s->regs[offset] = (val & ~s->regs_w1c[offset]) | readonly;
1345
1346
1347 s->regs[offset] &= ~(s->regs_w1c[offset] & val);
1348
1349
1350 switch (offset) {
1351 case GEM_NWCTRL:
1352 if (val & GEM_NWCTRL_RXENA) {
1353 for (i = 0; i < s->num_priority_queues; ++i) {
1354 gem_get_rx_desc(s, i);
1355 }
1356 }
1357 if (val & GEM_NWCTRL_TXSTART) {
1358 gem_transmit(s);
1359 }
1360 if (!(val & GEM_NWCTRL_TXENA)) {
1361
1362 for (i = 0; i < s->num_priority_queues; i++) {
1363 s->tx_desc_addr[i] = s->regs[GEM_TXQBASE];
1364 }
1365 }
1366 if (gem_can_receive(qemu_get_queue(s->nic))) {
1367 qemu_flush_queued_packets(qemu_get_queue(s->nic));
1368 }
1369 break;
1370
1371 case GEM_TXSTATUS:
1372 gem_update_int_status(s);
1373 break;
1374 case GEM_RXQBASE:
1375 s->rx_desc_addr[0] = val;
1376 break;
1377 case GEM_RECEIVE_Q1_PTR ... GEM_RECEIVE_Q7_PTR:
1378 s->rx_desc_addr[offset - GEM_RECEIVE_Q1_PTR + 1] = val;
1379 break;
1380 case GEM_TXQBASE:
1381 s->tx_desc_addr[0] = val;
1382 break;
1383 case GEM_TRANSMIT_Q1_PTR ... GEM_TRANSMIT_Q7_PTR:
1384 s->tx_desc_addr[offset - GEM_TRANSMIT_Q1_PTR + 1] = val;
1385 break;
1386 case GEM_RXSTATUS:
1387 gem_update_int_status(s);
1388 break;
1389 case GEM_IER:
1390 s->regs[GEM_IMR] &= ~val;
1391 gem_update_int_status(s);
1392 break;
1393 case GEM_INT_Q1_ENABLE ... GEM_INT_Q7_ENABLE:
1394 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_ENABLE] &= ~val;
1395 gem_update_int_status(s);
1396 break;
1397 case GEM_IDR:
1398 s->regs[GEM_IMR] |= val;
1399 gem_update_int_status(s);
1400 break;
1401 case GEM_INT_Q1_DISABLE ... GEM_INT_Q7_DISABLE:
1402 s->regs[GEM_INT_Q1_MASK + offset - GEM_INT_Q1_DISABLE] |= val;
1403 gem_update_int_status(s);
1404 break;
1405 case GEM_SPADDR1LO:
1406 case GEM_SPADDR2LO:
1407 case GEM_SPADDR3LO:
1408 case GEM_SPADDR4LO:
1409 s->sar_active[(offset - GEM_SPADDR1LO) / 2] = false;
1410 break;
1411 case GEM_SPADDR1HI:
1412 case GEM_SPADDR2HI:
1413 case GEM_SPADDR3HI:
1414 case GEM_SPADDR4HI:
1415 s->sar_active[(offset - GEM_SPADDR1HI) / 2] = true;
1416 break;
1417 case GEM_PHYMNTNC:
1418 if (val & GEM_PHYMNTNC_OP_W) {
1419 uint32_t phy_addr, reg_num;
1420
1421 phy_addr = (val & GEM_PHYMNTNC_ADDR) >> GEM_PHYMNTNC_ADDR_SHFT;
1422 reg_num = (val & GEM_PHYMNTNC_REG) >> GEM_PHYMNTNC_REG_SHIFT;
1423 gem_phy_loopback_setup(s, reg_num, val);
1424 if (s->mdio) {
1425 s->mdio->write(s->mdio, phy_addr, reg_num, val);
1426 }
1427 }
1428 break;
1429 }
1430
1431 DB_PRINT("newval: 0x%08x\n", s->regs[offset]);
1432}
1433
1434static const MemoryRegionOps gem_ops = {
1435 .read = gem_read,
1436 .write = gem_write,
1437 .endianness = DEVICE_LITTLE_ENDIAN,
1438};
1439
1440static void gem_set_link(NetClientState *nc)
1441{
1442 CadenceGEMState *s = qemu_get_nic_opaque(nc);
1443
1444 DB_PRINT("\n");
1445 phy_update_link(s);
1446 gem_update_int_status(s);
1447}
1448
1449static NetClientInfo net_gem_info = {
1450 .type = NET_CLIENT_DRIVER_NIC,
1451 .size = sizeof(NICState),
1452 .can_receive = gem_can_receive,
1453 .receive = gem_receive,
1454 .link_status_changed = gem_set_link,
1455};
1456
1457static void gem_realize(DeviceState *dev, Error **errp)
1458{
1459 CadenceGEMState *s = CADENCE_GEM(dev);
1460 int i;
1461
1462 s->dma_as = s->dma_mr ? address_space_init_shareable(s->dma_mr, NULL)
1463 : &address_space_memory;
1464
1465 if (s->num_priority_queues == 0 ||
1466 s->num_priority_queues > MAX_PRIORITY_QUEUES) {
1467 error_setg(errp, "Invalid num-priority-queues value: %" PRIx8,
1468 s->num_priority_queues);
1469 return;
1470 } else if (s->num_type1_screeners > MAX_TYPE1_SCREENERS) {
1471 error_setg(errp, "Invalid num-type1-screeners value: %" PRIx8,
1472 s->num_type1_screeners);
1473 return;
1474 } else if (s->num_type2_screeners > MAX_TYPE2_SCREENERS) {
1475 error_setg(errp, "Invalid num-type2-screeners value: %" PRIx8,
1476 s->num_type2_screeners);
1477 return;
1478 }
1479
1480 for (i = 0; i < s->num_priority_queues; ++i) {
1481 sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->irq[i]);
1482 }
1483
1484 if (!s->attr) {
1485 s->attr = MEMORY_TRANSACTION_ATTR(
1486 object_new(TYPE_MEMORY_TRANSACTION_ATTR));
1487 }
1488
1489 qemu_macaddr_default_if_unset(&s->conf.macaddr);
1490
1491 s->nic = qemu_new_nic(&net_gem_info, &s->conf,
1492 object_get_typename(OBJECT(dev)), dev->id, s);
1493}
1494
1495static void gem_init(Object *obj)
1496{
1497 CadenceGEMState *s = CADENCE_GEM(obj);
1498 DeviceState *dev = DEVICE(obj);
1499
1500 DB_PRINT("\n");
1501
1502 gem_init_register_masks(s);
1503 memory_region_init_io(&s->iomem, OBJECT(s), &gem_ops, s,
1504 "enet", sizeof(s->regs));
1505
1506 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
1507
1508 object_property_add_link(obj, "dma", TYPE_MEMORY_REGION,
1509 (Object **)&s->dma_mr,
1510 qdev_prop_allow_set_link_before_realize,
1511 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1512 &error_abort);
1513 object_property_add_link(obj, "memattr", TYPE_MEMORY_TRANSACTION_ATTR,
1514 (Object **)&s->attr,
1515 qdev_prop_allow_set_link_before_realize,
1516 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1517 &error_abort);
1518 object_property_add_link(obj, "mdio", TYPE_MDIO, (Object **)&s->mdio,
1519 qdev_prop_allow_set_link,
1520 OBJ_PROP_LINK_UNREF_ON_RELEASE,
1521 &error_abort);
1522}
1523
1524static const VMStateDescription vmstate_cadence_gem = {
1525 .name = "cadence_gem",
1526 .version_id = 4,
1527 .minimum_version_id = 4,
1528 .fields = (VMStateField[]) {
1529 VMSTATE_UINT32_ARRAY(regs, CadenceGEMState, CADENCE_GEM_MAXREG),
1530 VMSTATE_UINT8(phy_loop, CadenceGEMState),
1531 VMSTATE_UINT32_ARRAY(rx_desc_addr, CadenceGEMState,
1532 MAX_PRIORITY_QUEUES),
1533 VMSTATE_UINT32_ARRAY(tx_desc_addr, CadenceGEMState,
1534 MAX_PRIORITY_QUEUES),
1535 VMSTATE_BOOL_ARRAY(sar_active, CadenceGEMState, 4),
1536 VMSTATE_END_OF_LIST(),
1537 }
1538};
1539
1540static Property gem_properties[] = {
1541 DEFINE_NIC_PROPERTIES(CadenceGEMState, conf),
1542 DEFINE_PROP_UINT32("revision", CadenceGEMState, revision,
1543 GEM_MODID_VALUE),
1544 DEFINE_PROP_UINT8("num-priority-queues", CadenceGEMState,
1545 num_priority_queues, 1),
1546 DEFINE_PROP_UINT8("num-type1-screeners", CadenceGEMState,
1547 num_type1_screeners, 4),
1548 DEFINE_PROP_UINT8("num-type2-screeners", CadenceGEMState,
1549 num_type2_screeners, 4),
1550 DEFINE_PROP_END_OF_LIST(),
1551};
1552
1553static void gem_class_init(ObjectClass *klass, void *data)
1554{
1555 DeviceClass *dc = DEVICE_CLASS(klass);
1556
1557 dc->realize = gem_realize;
1558 dc->props = gem_properties;
1559 dc->vmsd = &vmstate_cadence_gem;
1560 dc->reset = gem_reset;
1561}
1562
1563static const TypeInfo gem_info = {
1564 .name = TYPE_CADENCE_GEM,
1565 .parent = TYPE_SYS_BUS_DEVICE,
1566 .instance_size = sizeof(CadenceGEMState),
1567 .instance_init = gem_init,
1568 .class_init = gem_class_init,
1569};
1570
1571static void gem_register_types(void)
1572{
1573 type_register_static(&gem_info);
1574}
1575
1576type_init(gem_register_types)
1577