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14#ifndef HW_S390_PCI_BUS_H
15#define HW_S390_PCI_BUS_H
16
17#include "hw/pci/pci.h"
18#include "hw/pci/pci_host.h"
19#include "hw/s390x/sclp.h"
20#include "hw/s390x/s390_flic.h"
21#include "hw/s390x/css.h"
22
23#define TYPE_S390_PCI_HOST_BRIDGE "s390-pcihost"
24#define TYPE_S390_PCI_BUS "s390-pcibus"
25#define TYPE_S390_PCI_DEVICE "zpci"
26#define FH_MASK_ENABLE 0x80000000
27#define FH_MASK_INSTANCE 0x7f000000
28#define FH_MASK_SHM 0x00ff0000
29#define FH_MASK_INDEX 0x0000001f
30#define FH_SHM_VFIO 0x00010000
31#define FH_SHM_EMUL 0x00020000
32#define S390_PCIPT_ADAPTER 2
33#define ZPCI_MAX_FID 0xffffffff
34#define ZPCI_MAX_UID 0xffff
35#define UID_UNDEFINED 0
36#define UID_CHECKING_ENABLED 0x01
37#define HOT_UNPLUG_TIMEOUT (NANOSECONDS_PER_SECOND * 60 * 5)
38
39#define S390_PCI_HOST_BRIDGE(obj) \
40 OBJECT_CHECK(S390pciState, (obj), TYPE_S390_PCI_HOST_BRIDGE)
41#define S390_PCI_BUS(obj) \
42 OBJECT_CHECK(S390PCIBus, (obj), TYPE_S390_PCI_BUS)
43#define S390_PCI_DEVICE(obj) \
44 OBJECT_CHECK(S390PCIBusDevice, (obj), TYPE_S390_PCI_DEVICE)
45
46#define HP_EVENT_TO_CONFIGURED 0x0301
47#define HP_EVENT_RESERVED_TO_STANDBY 0x0302
48#define HP_EVENT_DECONFIGURE_REQUEST 0x0303
49#define HP_EVENT_CONFIGURED_TO_STBRES 0x0304
50#define HP_EVENT_STANDBY_TO_RESERVED 0x0308
51
52#define ERR_EVENT_INVALAS 0x1
53#define ERR_EVENT_OORANGE 0x2
54#define ERR_EVENT_INVALTF 0x3
55#define ERR_EVENT_TPROTE 0x4
56#define ERR_EVENT_APROTE 0x5
57#define ERR_EVENT_KEYE 0x6
58#define ERR_EVENT_INVALTE 0x7
59#define ERR_EVENT_INVALTL 0x8
60#define ERR_EVENT_TT 0x9
61#define ERR_EVENT_INVALMS 0xa
62#define ERR_EVENT_SERR 0xb
63#define ERR_EVENT_NOMSI 0x10
64#define ERR_EVENT_INVALBV 0x11
65#define ERR_EVENT_AIBV 0x12
66#define ERR_EVENT_AIRERR 0x13
67#define ERR_EVENT_FMBA 0x2a
68#define ERR_EVENT_FMBUP 0x2b
69#define ERR_EVENT_FMBPRO 0x2c
70#define ERR_EVENT_CCONF 0x30
71#define ERR_EVENT_SERVAC 0x3a
72#define ERR_EVENT_PERMERR 0x3b
73
74#define ERR_EVENT_Q_BIT 0x2
75#define ERR_EVENT_MVN_OFFSET 16
76
77#define ZPCI_MSI_VEC_BITS 11
78#define ZPCI_MSI_VEC_MASK 0x7ff
79
80#define ZPCI_MSI_ADDR 0xfe00000000000000ULL
81#define ZPCI_SDMA_ADDR 0x100000000ULL
82#define ZPCI_EDMA_ADDR 0x1ffffffffffffffULL
83
84#define PAGE_SHIFT 12
85#define PAGE_SIZE (1 << PAGE_SHIFT)
86#define PAGE_MASK (~(PAGE_SIZE-1))
87#define PAGE_DEFAULT_ACC 0
88#define PAGE_DEFAULT_KEY (PAGE_DEFAULT_ACC << 4)
89
90
91enum ZpciIoatDtype {
92 ZPCI_IOTA_STO = 0,
93 ZPCI_IOTA_RTTO = 1,
94 ZPCI_IOTA_RSTO = 2,
95 ZPCI_IOTA_RFTO = 3,
96 ZPCI_IOTA_PFAA = 4,
97 ZPCI_IOTA_IOPFAA = 5,
98 ZPCI_IOTA_IOPTO = 7
99};
100
101#define ZPCI_IOTA_IOT_ENABLED 0x800ULL
102#define ZPCI_IOTA_DT_ST (ZPCI_IOTA_STO << 2)
103#define ZPCI_IOTA_DT_RT (ZPCI_IOTA_RTTO << 2)
104#define ZPCI_IOTA_DT_RS (ZPCI_IOTA_RSTO << 2)
105#define ZPCI_IOTA_DT_RF (ZPCI_IOTA_RFTO << 2)
106#define ZPCI_IOTA_DT_PF (ZPCI_IOTA_PFAA << 2)
107#define ZPCI_IOTA_FS_4K 0
108#define ZPCI_IOTA_FS_1M 1
109#define ZPCI_IOTA_FS_2G 2
110#define ZPCI_KEY (PAGE_DEFAULT_KEY << 5)
111
112#define ZPCI_IOTA_STO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_ST)
113#define ZPCI_IOTA_RTTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RT)
114#define ZPCI_IOTA_RSTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RS)
115#define ZPCI_IOTA_RFTO_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY | ZPCI_IOTA_DT_RF)
116#define ZPCI_IOTA_RFAA_FLAG (ZPCI_IOTA_IOT_ENABLED | ZPCI_KEY |\
117 ZPCI_IOTA_DT_PF | ZPCI_IOTA_FS_2G)
118
119
120#define ZPCI_INDEX_MASK 0x7ffULL
121
122#define ZPCI_TABLE_TYPE_MASK 0xc
123#define ZPCI_TABLE_TYPE_RFX 0xc
124#define ZPCI_TABLE_TYPE_RSX 0x8
125#define ZPCI_TABLE_TYPE_RTX 0x4
126#define ZPCI_TABLE_TYPE_SX 0x0
127
128#define ZPCI_TABLE_LEN_RFX 0x3
129#define ZPCI_TABLE_LEN_RSX 0x3
130#define ZPCI_TABLE_LEN_RTX 0x3
131
132#define ZPCI_TABLE_OFFSET_MASK 0xc0
133#define ZPCI_TABLE_SIZE 0x4000
134#define ZPCI_TABLE_ALIGN ZPCI_TABLE_SIZE
135#define ZPCI_TABLE_ENTRY_SIZE (sizeof(unsigned long))
136#define ZPCI_TABLE_ENTRIES (ZPCI_TABLE_SIZE / ZPCI_TABLE_ENTRY_SIZE)
137
138#define ZPCI_TABLE_BITS 11
139#define ZPCI_PT_BITS 8
140#define ZPCI_ST_SHIFT (ZPCI_PT_BITS + PAGE_SHIFT)
141#define ZPCI_RT_SHIFT (ZPCI_ST_SHIFT + ZPCI_TABLE_BITS)
142
143#define ZPCI_RTE_FLAG_MASK 0x3fffULL
144#define ZPCI_RTE_ADDR_MASK (~ZPCI_RTE_FLAG_MASK)
145#define ZPCI_STE_FLAG_MASK 0x7ffULL
146#define ZPCI_STE_ADDR_MASK (~ZPCI_STE_FLAG_MASK)
147
148
149#define ZPCI_PTE_VALID_MASK 0x400
150#define ZPCI_PTE_INVALID 0x400
151#define ZPCI_PTE_VALID 0x000
152#define ZPCI_PT_SIZE 0x800
153#define ZPCI_PT_ALIGN ZPCI_PT_SIZE
154#define ZPCI_PT_ENTRIES (ZPCI_PT_SIZE / ZPCI_TABLE_ENTRY_SIZE)
155#define ZPCI_PT_MASK (ZPCI_PT_ENTRIES - 1)
156
157#define ZPCI_PTE_FLAG_MASK 0xfffULL
158#define ZPCI_PTE_ADDR_MASK (~ZPCI_PTE_FLAG_MASK)
159
160
161#define ZPCI_TABLE_VALID 0x00
162#define ZPCI_TABLE_INVALID 0x20
163#define ZPCI_TABLE_PROTECTED 0x200
164#define ZPCI_TABLE_UNPROTECTED 0x000
165
166#define ZPCI_TABLE_VALID_MASK 0x20
167#define ZPCI_TABLE_PROT_MASK 0x200
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187typedef enum {
188 ZPCI_FS_RESERVED,
189 ZPCI_FS_STANDBY,
190 ZPCI_FS_DISABLED,
191 ZPCI_FS_ENABLED,
192 ZPCI_FS_BLOCKED,
193 ZPCI_FS_ERROR,
194 ZPCI_FS_PERMANENT_ERROR,
195} ZpciState;
196
197typedef struct SeiContainer {
198 QTAILQ_ENTRY(SeiContainer) link;
199 uint32_t fid;
200 uint32_t fh;
201 uint8_t cc;
202 uint16_t pec;
203 uint64_t faddr;
204 uint32_t e;
205} SeiContainer;
206
207typedef struct PciCcdfErr {
208 uint32_t reserved1;
209 uint32_t fh;
210 uint32_t fid;
211 uint32_t e;
212 uint64_t faddr;
213 uint32_t reserved3;
214 uint16_t reserved4;
215 uint16_t pec;
216} QEMU_PACKED PciCcdfErr;
217
218typedef struct PciCcdfAvail {
219 uint32_t reserved1;
220 uint32_t fh;
221 uint32_t fid;
222 uint32_t reserved2;
223 uint32_t reserved3;
224 uint32_t reserved4;
225 uint32_t reserved5;
226 uint16_t reserved6;
227 uint16_t pec;
228} QEMU_PACKED PciCcdfAvail;
229
230typedef struct ChscSeiNt2Res {
231 uint16_t length;
232 uint16_t code;
233 uint16_t reserved1;
234 uint8_t reserved2;
235 uint8_t nt;
236 uint8_t flags;
237 uint8_t reserved3;
238 uint8_t reserved4;
239 uint8_t cc;
240 uint32_t reserved5[13];
241 uint8_t ccdf[4016];
242} QEMU_PACKED ChscSeiNt2Res;
243
244typedef struct PciCfgSccb {
245 SCCBHeader header;
246 uint8_t atype;
247 uint8_t reserved1;
248 uint16_t reserved2;
249 uint32_t aid;
250} QEMU_PACKED PciCfgSccb;
251
252typedef struct S390MsixInfo {
253 bool available;
254 uint8_t table_bar;
255 uint8_t pba_bar;
256 uint16_t entries;
257 uint32_t table_offset;
258 uint32_t pba_offset;
259} S390MsixInfo;
260
261typedef struct S390PCIIOMMU {
262 AddressSpace as;
263 MemoryRegion mr;
264} S390PCIIOMMU;
265
266typedef struct S390PCIBusDevice {
267 DeviceState qdev;
268 PCIDevice *pdev;
269 ZpciState state;
270 bool iommu_enabled;
271 char *target;
272 uint16_t uid;
273 uint32_t fh;
274 uint32_t fid;
275 bool fid_defined;
276 uint64_t g_iota;
277 uint64_t pba;
278 uint64_t pal;
279 uint64_t fmb_addr;
280 uint8_t isc;
281 uint16_t noi;
282 uint8_t sum;
283 S390MsixInfo msix;
284 AdapterRoutes routes;
285 S390PCIIOMMU *iommu;
286 MemoryRegion iommu_mr;
287 MemoryRegion msix_notify_mr;
288 IndAddr *summary_ind;
289 IndAddr *indicator;
290 QEMUTimer *release_timer;
291} S390PCIBusDevice;
292
293typedef struct S390PCIBus {
294 BusState qbus;
295} S390PCIBus;
296
297typedef struct S390pciState {
298 PCIHostState parent_obj;
299 S390PCIBus *bus;
300 S390PCIBusDevice *pbdev[PCI_SLOT_MAX];
301 S390PCIIOMMU *iommu[PCI_SLOT_MAX];
302 QTAILQ_HEAD(, SeiContainer) pending_sei;
303} S390pciState;
304
305int chsc_sei_nt2_get_event(void *res);
306int chsc_sei_nt2_have_event(void);
307void s390_pci_sclp_configure(SCCB *sccb);
308void s390_pci_sclp_deconfigure(SCCB *sccb);
309void s390_pci_iommu_enable(S390PCIBusDevice *pbdev);
310void s390_pci_iommu_disable(S390PCIBusDevice *pbdev);
311void s390_pci_generate_error_event(uint16_t pec, uint32_t fh, uint32_t fid,
312 uint64_t faddr, uint32_t e);
313S390PCIBusDevice *s390_pci_find_dev_by_idx(uint32_t idx);
314S390PCIBusDevice *s390_pci_find_dev_by_fh(uint32_t fh);
315S390PCIBusDevice *s390_pci_find_dev_by_fid(uint32_t fid);
316S390PCIBusDevice *s390_pci_find_next_avail_dev(S390PCIBusDevice *pbdev);
317
318#endif
319
