1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20#ifndef PCI_HOST_SPAPR_H
21#define PCI_HOST_SPAPR_H
22
23#include "hw/ppc/spapr.h"
24#include "hw/pci/pci.h"
25#include "hw/pci/pci_host.h"
26#include "hw/ppc/xics.h"
27
28#define TYPE_SPAPR_PCI_HOST_BRIDGE "spapr-pci-host-bridge"
29
30#define SPAPR_PCI_HOST_BRIDGE(obj) \
31 OBJECT_CHECK(sPAPRPHBState, (obj), TYPE_SPAPR_PCI_HOST_BRIDGE)
32
33#define SPAPR_PCI_DMA_MAX_WINDOWS 2
34
35typedef struct sPAPRPHBState sPAPRPHBState;
36
37typedef struct spapr_pci_msi {
38 uint32_t first_irq;
39 uint32_t num;
40} spapr_pci_msi;
41
42typedef struct spapr_pci_msi_mig {
43 uint32_t key;
44 spapr_pci_msi value;
45} spapr_pci_msi_mig;
46
47struct sPAPRPHBState {
48 PCIHostState parent_obj;
49
50 uint32_t index;
51 uint64_t buid;
52 char *dtbusname;
53 bool dr_enabled;
54
55 MemoryRegion memspace, iospace;
56 hwaddr mem_win_addr, mem_win_size, mem64_win_addr, mem64_win_size;
57 uint64_t mem64_win_pciaddr;
58 hwaddr io_win_addr, io_win_size;
59 MemoryRegion mem32window, mem64window, iowindow, msiwindow;
60
61 uint32_t dma_liobn[SPAPR_PCI_DMA_MAX_WINDOWS];
62 hwaddr dma_win_addr, dma_win_size;
63 AddressSpace iommu_as;
64 MemoryRegion iommu_root;
65
66 struct spapr_pci_lsi {
67 uint32_t irq;
68 } lsi_table[PCI_NUM_PINS];
69
70 GHashTable *msi;
71
72 int32_t msi_devs_num;
73 spapr_pci_msi_mig *msi_devs;
74
75 QLIST_ENTRY(sPAPRPHBState) list;
76
77 bool ddw_enabled;
78 uint64_t page_size_mask;
79 uint64_t dma64_win_addr;
80
81 uint32_t numa_node;
82
83
84 bool pre_2_8_migration;
85 uint32_t mig_liobn;
86 hwaddr mig_mem_win_addr, mig_mem_win_size;
87 hwaddr mig_io_win_addr, mig_io_win_size;
88};
89
90#define SPAPR_PCI_MEM_WIN_BUS_OFFSET 0x80000000ULL
91#define SPAPR_PCI_MEM32_WIN_SIZE \
92 ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
93#define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL
94
95
96
97#define SPAPR_PCI_BASE (1ULL << 45)
98#define SPAPR_PCI_LIMIT (1ULL << 46)
99
100#define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000
101#define SPAPR_PCI_IO_WIN_SIZE 0x10000
102
103#define SPAPR_PCI_MSI_WINDOW 0x40000000000ULL
104
105static inline qemu_irq spapr_phb_lsi_qirq(struct sPAPRPHBState *phb, int pin)
106{
107 sPAPRMachineState *spapr = SPAPR_MACHINE(qdev_get_machine());
108
109 return xics_get_qirq(spapr->xics, phb->lsi_table[pin].irq);
110}
111
112PCIHostState *spapr_create_phb(sPAPRMachineState *spapr, int index);
113
114int spapr_populate_pci_dt(sPAPRPHBState *phb,
115 uint32_t xics_phandle,
116 void *fdt);
117
118void spapr_pci_rtas_init(void);
119
120sPAPRPHBState *spapr_pci_find_phb(sPAPRMachineState *spapr, uint64_t buid);
121PCIDevice *spapr_pci_find_dev(sPAPRMachineState *spapr, uint64_t buid,
122 uint32_t config_addr);
123
124
125#ifdef CONFIG_LINUX
126bool spapr_phb_eeh_available(sPAPRPHBState *sphb);
127int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
128 unsigned int addr, int option);
129int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb, int *state);
130int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option);
131int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb);
132void spapr_phb_vfio_reset(DeviceState *qdev);
133#else
134static inline bool spapr_phb_eeh_available(sPAPRPHBState *sphb)
135{
136 return false;
137}
138static inline int spapr_phb_vfio_eeh_set_option(sPAPRPHBState *sphb,
139 unsigned int addr, int option)
140{
141 return RTAS_OUT_HW_ERROR;
142}
143static inline int spapr_phb_vfio_eeh_get_state(sPAPRPHBState *sphb,
144 int *state)
145{
146 return RTAS_OUT_HW_ERROR;
147}
148static inline int spapr_phb_vfio_eeh_reset(sPAPRPHBState *sphb, int option)
149{
150 return RTAS_OUT_HW_ERROR;
151}
152static inline int spapr_phb_vfio_eeh_configure(sPAPRPHBState *sphb)
153{
154 return RTAS_OUT_HW_ERROR;
155}
156static inline void spapr_phb_vfio_reset(DeviceState *qdev)
157{
158}
159#endif
160
161void spapr_phb_dma_reset(sPAPRPHBState *sphb);
162
163#endif
164