1/* 2 * SD Association Host Standard Specification v2.0 controller emulation 3 * 4 * Copyright (c) 2011 Samsung Electronics Co., Ltd. 5 * Mitsyanko Igor <i.mitsyanko@samsung.com> 6 * Peter A.G. Crosthwaite <peter.crosthwaite@petalogix.com> 7 * 8 * Based on MMC controller for Samsung S5PC1xx-based board emulation 9 * by Alexey Merkulov and Vladimir Monakhov. 10 * 11 * This program is free software; you can redistribute it and/or modify it 12 * under the terms of the GNU General Public License as published by the 13 * Free Software Foundation; either version 2 of the License, or (at your 14 * option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 19 * See the GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU _General Public License along 22 * with this program; if not, see <http://www.gnu.org/licenses/>. 23 */ 24 25#ifndef SDHCI_H 26#define SDHCI_H 27 28#include "qemu-common.h" 29#include "hw/block/block.h" 30#include "hw/pci/pci.h" 31#include "hw/sysbus.h" 32#include "hw/sd/sd.h" 33 34/* Default SD/MMC host controller features information, which will be 35 * presented in CAPABILITIES register of generic SD host controller at reset. 36 * If not stated otherwise: 37 * 0 - not supported, 1 - supported, other - prohibited. 38 */ 39#define SDHC_CAPAB_DRIVER_D 1ull /* Driver type D support */ 40#define SDHC_CAPAB_DRIVER_C 1ull /* Driver type C support */ 41#define SDHC_CAPAB_DRIVER_A 1ull /* Driver type A support */ 42#define SDHC_CAPAB_DDR50 1ull /* DDR50 support */ 43#define SDHC_CAPAB_SDR104 1ull /* SDR104 support */ 44#define SDHC_CAPAB_SDR50 1ull /* SDR50 support */ 45#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ 46#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ 47#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ 48#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ 49#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ 50#define SDHC_CAPAB_SDMA 1ul /* SDMA support */ 51#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ 52#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ 53#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ 54/* Maximum host controller R/W buffers size 55 * Possible values: 512, 1024, 2048 bytes */ 56#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul 57/* Maximum clock frequency for SDclock in MHz 58 * value in range 10-63 MHz, 0 - not defined */ 59#define SDHC_CAPAB_BASECLKFREQ 52ul 60#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ 61/* Timeout clock frequency 1-63, 0 - not defined */ 62#define SDHC_CAPAB_TOCLKFREQ 52ul 63 64/* Now check all parameters and calculate CAPABILITIES REGISTER value */ 65#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ 66 SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ 67 SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ 68 SDHC_CAPAB_TOUNIT > 1 69#error Capabilities features can have value 0 or 1 only! 70#endif 71 72#if SDHC_CAPAB_MAXBLOCKLENGTH == 512 73#define MAX_BLOCK_LENGTH 0ul 74#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 75#define MAX_BLOCK_LENGTH 1ul 76#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 77#define MAX_BLOCK_LENGTH 2ul 78#else 79#error Max host controller block size can have value 512, 1024 or 2048 only! 80#endif 81 82#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ 83 SDHC_CAPAB_BASECLKFREQ > 63 84#error SDclock frequency can have value in range 0, 10-63 only! 85#endif 86 87#if SDHC_CAPAB_TOCLKFREQ > 63 88#error Timeout clock frequency can have value in range 0-63 only! 89#endif 90 91#define SDHC_CAPAB_REG_DEFAULT \ 92 ((SDHC_CAPAB_DRIVER_D << 38) | (SDHC_CAPAB_DRIVER_C << 37) |\ 93 (SDHC_CAPAB_DRIVER_A << 36) | (SDHC_CAPAB_DDR50 << 34) | \ 94 (SDHC_CAPAB_SDR104 << 33) | (SDHC_CAPAB_SDR50 << 32) | \ 95 (SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ 96 (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ 97 (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ 98 (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ 99 (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ 100 (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ 101 (SDHC_CAPAB_TOCLKFREQ)) 102 103/* SD/MMC host controller state */ 104typedef struct SDHCIState { 105 union { 106 PCIDevice pcidev; 107 SysBusDevice busdev; 108 }; 109 SDBus sdbus; 110 MemoryRegion iomem; 111 BlockBackend *blk; 112 MemoryRegion *dma_mr; 113 AddressSpace *dma_as; 114 115 QEMUTimer *insert_timer; /* timer for 'changing' sd card. */ 116 QEMUTimer *transfer_timer; 117 qemu_irq eject_cb; 118 qemu_irq ro_cb; 119 qemu_irq irq; 120 121 uint32_t sdmasysad; /* SDMA System Address register */ 122 uint16_t blksize; /* Host DMA Buff Boundary and Transfer BlkSize Reg */ 123 uint16_t blkcnt; /* Blocks count for current transfer */ 124 uint32_t argument; /* Command Argument Register */ 125 uint16_t trnmod; /* Transfer Mode Setting Register */ 126 uint16_t cmdreg; /* Command Register */ 127 uint32_t rspreg[4]; /* Response Registers 0-3 */ 128 uint32_t prnsts; /* Present State Register */ 129 uint8_t hostctl; /* Host Control Register */ 130 uint8_t pwrcon; /* Power control Register */ 131 uint8_t blkgap; /* Block Gap Control Register */ 132 uint8_t wakcon; /* WakeUp Control Register */ 133 uint16_t clkcon; /* Clock control Register */ 134 uint8_t timeoutcon; /* Timeout Control Register */ 135 uint8_t admaerr; /* ADMA Error Status Register */ 136 uint16_t norintsts; /* Normal Interrupt Status Register */ 137 uint16_t errintsts; /* Error Interrupt Status Register */ 138 uint16_t norintstsen; /* Normal Interrupt Status Enable Register */ 139 uint16_t errintstsen; /* Error Interrupt Status Enable Register */ 140 uint16_t norintsigen; /* Normal Interrupt Signal Enable Register */ 141 uint16_t errintsigen; /* Error Interrupt Signal Enable Register */ 142 uint16_t acmd12errsts; /* Auto CMD12 error status register */ 143 uint16_t hostctl2; /* Host Control 2 */ 144 uint64_t admasysaddr; /* ADMA System Address Register */ 145 146 uint32_t capareg; /* Capabilities Register */ 147 uint32_t maxcurr; /* Maximum Current Capabilities Register */ 148 uint8_t *fifo_buffer; /* SD host i/o FIFO buffer */ 149 uint32_t buf_maxsz; 150 uint16_t data_count; /* current element in FIFO buffer */ 151 uint8_t stopped_state;/* Current SDHC state */ 152 bool pending_insert_quirk;/* Quirk for Raspberry Pi card insert int */ 153 bool pending_insert_state; 154 /* Buffer Data Port Register - virtual access point to R and W buffers */ 155 /* Software Reset Register - always reads as 0 */ 156 /* Force Event Auto CMD12 Error Interrupt Reg - write only */ 157 /* Force Event Error Interrupt Register- write only */ 158 /* RO Host Controller Version Register always reads as 0x2401 */ 159} SDHCIState; 160 161#define TYPE_PCI_SDHCI "sdhci-pci" 162#define PCI_SDHCI(obj) OBJECT_CHECK(SDHCIState, (obj), TYPE_PCI_SDHCI) 163 164#define TYPE_SYSBUS_SDHCI "generic-sdhci" 165#define SYSBUS_SDHCI(obj) \ 166 OBJECT_CHECK(SDHCIState, (obj), TYPE_SYSBUS_SDHCI) 167 168#endif /* SDHCI_H */ 169