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20#ifndef I386_CPU_H
21#define I386_CPU_H
22
23#include "qemu-common.h"
24#include "cpu-qom.h"
25#include "standard-headers/asm-x86/hyperv.h"
26
27#ifdef TARGET_X86_64
28#define TARGET_LONG_BITS 64
29#else
30#define TARGET_LONG_BITS 32
31#endif
32
33
34#define TARGET_MAX_INSN_SIZE 16
35
36
37
38#define TARGET_HAS_PRECISE_SMC
39
40#ifdef TARGET_X86_64
41#define I386_ELF_MACHINE EM_X86_64
42#define ELF_MACHINE_UNAME "x86_64"
43#else
44#define I386_ELF_MACHINE EM_386
45#define ELF_MACHINE_UNAME "i686"
46#endif
47
48#define CPUArchState struct CPUX86State
49
50#include "exec/cpu-defs.h"
51
52#include "fpu/softfloat.h"
53
54#define R_EAX 0
55#define R_ECX 1
56#define R_EDX 2
57#define R_EBX 3
58#define R_ESP 4
59#define R_EBP 5
60#define R_ESI 6
61#define R_EDI 7
62
63#define R_AL 0
64#define R_CL 1
65#define R_DL 2
66#define R_BL 3
67#define R_AH 4
68#define R_CH 5
69#define R_DH 6
70#define R_BH 7
71
72#define R_ES 0
73#define R_CS 1
74#define R_SS 2
75#define R_DS 3
76#define R_FS 4
77#define R_GS 5
78
79
80#define DESC_G_MASK (1 << 23)
81#define DESC_B_SHIFT 22
82#define DESC_B_MASK (1 << DESC_B_SHIFT)
83#define DESC_L_SHIFT 21
84#define DESC_L_MASK (1 << DESC_L_SHIFT)
85#define DESC_AVL_MASK (1 << 20)
86#define DESC_P_MASK (1 << 15)
87#define DESC_DPL_SHIFT 13
88#define DESC_DPL_MASK (3 << DESC_DPL_SHIFT)
89#define DESC_S_MASK (1 << 12)
90#define DESC_TYPE_SHIFT 8
91#define DESC_TYPE_MASK (15 << DESC_TYPE_SHIFT)
92#define DESC_A_MASK (1 << 8)
93
94#define DESC_CS_MASK (1 << 11)
95#define DESC_C_MASK (1 << 10)
96#define DESC_R_MASK (1 << 9)
97
98#define DESC_E_MASK (1 << 10)
99#define DESC_W_MASK (1 << 9)
100
101#define DESC_TSS_BUSY_MASK (1 << 9)
102
103
104#define CC_C 0x0001
105#define CC_P 0x0004
106#define CC_A 0x0010
107#define CC_Z 0x0040
108#define CC_S 0x0080
109#define CC_O 0x0800
110
111#define TF_SHIFT 8
112#define IOPL_SHIFT 12
113#define VM_SHIFT 17
114
115#define TF_MASK 0x00000100
116#define IF_MASK 0x00000200
117#define DF_MASK 0x00000400
118#define IOPL_MASK 0x00003000
119#define NT_MASK 0x00004000
120#define RF_MASK 0x00010000
121#define VM_MASK 0x00020000
122#define AC_MASK 0x00040000
123#define VIF_MASK 0x00080000
124#define VIP_MASK 0x00100000
125#define ID_MASK 0x00200000
126
127
128
129
130
131
132#define HF_CPL_SHIFT 0
133
134#define HF_INHIBIT_IRQ_SHIFT 3
135
136#define HF_CS32_SHIFT 4
137#define HF_SS32_SHIFT 5
138
139#define HF_ADDSEG_SHIFT 6
140
141#define HF_PE_SHIFT 7
142#define HF_TF_SHIFT 8
143#define HF_MP_SHIFT 9
144#define HF_EM_SHIFT 10
145#define HF_TS_SHIFT 11
146#define HF_IOPL_SHIFT 12
147#define HF_LMA_SHIFT 14
148#define HF_CS64_SHIFT 15
149#define HF_RF_SHIFT 16
150#define HF_VM_SHIFT 17
151#define HF_AC_SHIFT 18
152#define HF_SMM_SHIFT 19
153#define HF_SVME_SHIFT 20
154#define HF_SVMI_SHIFT 21
155#define HF_OSFXSR_SHIFT 22
156#define HF_SMAP_SHIFT 23
157#define HF_IOBPT_SHIFT 24
158#define HF_MPX_EN_SHIFT 25
159#define HF_MPX_IU_SHIFT 26
160
161#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
162#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
163#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
164#define HF_SS32_MASK (1 << HF_SS32_SHIFT)
165#define HF_ADDSEG_MASK (1 << HF_ADDSEG_SHIFT)
166#define HF_PE_MASK (1 << HF_PE_SHIFT)
167#define HF_TF_MASK (1 << HF_TF_SHIFT)
168#define HF_MP_MASK (1 << HF_MP_SHIFT)
169#define HF_EM_MASK (1 << HF_EM_SHIFT)
170#define HF_TS_MASK (1 << HF_TS_SHIFT)
171#define HF_IOPL_MASK (3 << HF_IOPL_SHIFT)
172#define HF_LMA_MASK (1 << HF_LMA_SHIFT)
173#define HF_CS64_MASK (1 << HF_CS64_SHIFT)
174#define HF_RF_MASK (1 << HF_RF_SHIFT)
175#define HF_VM_MASK (1 << HF_VM_SHIFT)
176#define HF_AC_MASK (1 << HF_AC_SHIFT)
177#define HF_SMM_MASK (1 << HF_SMM_SHIFT)
178#define HF_SVME_MASK (1 << HF_SVME_SHIFT)
179#define HF_SVMI_MASK (1 << HF_SVMI_SHIFT)
180#define HF_OSFXSR_MASK (1 << HF_OSFXSR_SHIFT)
181#define HF_SMAP_MASK (1 << HF_SMAP_SHIFT)
182#define HF_IOBPT_MASK (1 << HF_IOBPT_SHIFT)
183#define HF_MPX_EN_MASK (1 << HF_MPX_EN_SHIFT)
184#define HF_MPX_IU_MASK (1 << HF_MPX_IU_SHIFT)
185
186
187
188#define HF2_GIF_SHIFT 0
189#define HF2_HIF_SHIFT 1
190#define HF2_NMI_SHIFT 2
191#define HF2_VINTR_SHIFT 3
192#define HF2_SMM_INSIDE_NMI_SHIFT 4
193#define HF2_MPX_PR_SHIFT 5
194
195#define HF2_GIF_MASK (1 << HF2_GIF_SHIFT)
196#define HF2_HIF_MASK (1 << HF2_HIF_SHIFT)
197#define HF2_NMI_MASK (1 << HF2_NMI_SHIFT)
198#define HF2_VINTR_MASK (1 << HF2_VINTR_SHIFT)
199#define HF2_SMM_INSIDE_NMI_MASK (1 << HF2_SMM_INSIDE_NMI_SHIFT)
200#define HF2_MPX_PR_MASK (1 << HF2_MPX_PR_SHIFT)
201
202#define CR0_PE_SHIFT 0
203#define CR0_MP_SHIFT 1
204
205#define CR0_PE_MASK (1U << 0)
206#define CR0_MP_MASK (1U << 1)
207#define CR0_EM_MASK (1U << 2)
208#define CR0_TS_MASK (1U << 3)
209#define CR0_ET_MASK (1U << 4)
210#define CR0_NE_MASK (1U << 5)
211#define CR0_WP_MASK (1U << 16)
212#define CR0_AM_MASK (1U << 18)
213#define CR0_PG_MASK (1U << 31)
214
215#define CR4_VME_MASK (1U << 0)
216#define CR4_PVI_MASK (1U << 1)
217#define CR4_TSD_MASK (1U << 2)
218#define CR4_DE_MASK (1U << 3)
219#define CR4_PSE_MASK (1U << 4)
220#define CR4_PAE_MASK (1U << 5)
221#define CR4_MCE_MASK (1U << 6)
222#define CR4_PGE_MASK (1U << 7)
223#define CR4_PCE_MASK (1U << 8)
224#define CR4_OSFXSR_SHIFT 9
225#define CR4_OSFXSR_MASK (1U << CR4_OSFXSR_SHIFT)
226#define CR4_OSXMMEXCPT_MASK (1U << 10)
227#define CR4_VMXE_MASK (1U << 13)
228#define CR4_SMXE_MASK (1U << 14)
229#define CR4_FSGSBASE_MASK (1U << 16)
230#define CR4_PCIDE_MASK (1U << 17)
231#define CR4_OSXSAVE_MASK (1U << 18)
232#define CR4_SMEP_MASK (1U << 20)
233#define CR4_SMAP_MASK (1U << 21)
234#define CR4_PKE_MASK (1U << 22)
235
236#define DR6_BD (1 << 13)
237#define DR6_BS (1 << 14)
238#define DR6_BT (1 << 15)
239#define DR6_FIXED_1 0xffff0ff0
240
241#define DR7_GD (1 << 13)
242#define DR7_TYPE_SHIFT 16
243#define DR7_LEN_SHIFT 18
244#define DR7_FIXED_1 0x00000400
245#define DR7_GLOBAL_BP_MASK 0xaa
246#define DR7_LOCAL_BP_MASK 0x55
247#define DR7_MAX_BP 4
248#define DR7_TYPE_BP_INST 0x0
249#define DR7_TYPE_DATA_WR 0x1
250#define DR7_TYPE_IO_RW 0x2
251#define DR7_TYPE_DATA_RW 0x3
252
253#define PG_PRESENT_BIT 0
254#define PG_RW_BIT 1
255#define PG_USER_BIT 2
256#define PG_PWT_BIT 3
257#define PG_PCD_BIT 4
258#define PG_ACCESSED_BIT 5
259#define PG_DIRTY_BIT 6
260#define PG_PSE_BIT 7
261#define PG_GLOBAL_BIT 8
262#define PG_PSE_PAT_BIT 12
263#define PG_PKRU_BIT 59
264#define PG_NX_BIT 63
265
266#define PG_PRESENT_MASK (1 << PG_PRESENT_BIT)
267#define PG_RW_MASK (1 << PG_RW_BIT)
268#define PG_USER_MASK (1 << PG_USER_BIT)
269#define PG_PWT_MASK (1 << PG_PWT_BIT)
270#define PG_PCD_MASK (1 << PG_PCD_BIT)
271#define PG_ACCESSED_MASK (1 << PG_ACCESSED_BIT)
272#define PG_DIRTY_MASK (1 << PG_DIRTY_BIT)
273#define PG_PSE_MASK (1 << PG_PSE_BIT)
274#define PG_GLOBAL_MASK (1 << PG_GLOBAL_BIT)
275#define PG_PSE_PAT_MASK (1 << PG_PSE_PAT_BIT)
276#define PG_ADDRESS_MASK 0x000ffffffffff000LL
277#define PG_HI_RSVD_MASK (PG_ADDRESS_MASK & ~PHYS_ADDR_MASK)
278#define PG_HI_USER_MASK 0x7ff0000000000000LL
279#define PG_PKRU_MASK (15ULL << PG_PKRU_BIT)
280#define PG_NX_MASK (1ULL << PG_NX_BIT)
281
282#define PG_ERROR_W_BIT 1
283
284#define PG_ERROR_P_MASK 0x01
285#define PG_ERROR_W_MASK (1 << PG_ERROR_W_BIT)
286#define PG_ERROR_U_MASK 0x04
287#define PG_ERROR_RSVD_MASK 0x08
288#define PG_ERROR_I_D_MASK 0x10
289#define PG_ERROR_PK_MASK 0x20
290
291#define MCG_CTL_P (1ULL<<8)
292#define MCG_SER_P (1ULL<<24)
293#define MCG_LMCE_P (1ULL<<27)
294
295#define MCE_CAP_DEF (MCG_CTL_P|MCG_SER_P)
296#define MCE_BANKS_DEF 10
297
298#define MCG_CAP_BANKS_MASK 0xff
299
300#define MCG_STATUS_RIPV (1ULL<<0)
301#define MCG_STATUS_EIPV (1ULL<<1)
302#define MCG_STATUS_MCIP (1ULL<<2)
303#define MCG_STATUS_LMCE (1ULL<<3)
304
305#define MCG_EXT_CTL_LMCE_EN (1ULL<<0)
306
307#define MCI_STATUS_VAL (1ULL<<63)
308#define MCI_STATUS_OVER (1ULL<<62)
309#define MCI_STATUS_UC (1ULL<<61)
310#define MCI_STATUS_EN (1ULL<<60)
311#define MCI_STATUS_MISCV (1ULL<<59)
312#define MCI_STATUS_ADDRV (1ULL<<58)
313#define MCI_STATUS_PCC (1ULL<<57)
314#define MCI_STATUS_S (1ULL<<56)
315#define MCI_STATUS_AR (1ULL<<55)
316
317
318#define MCM_ADDR_SEGOFF 0
319#define MCM_ADDR_LINEAR 1
320#define MCM_ADDR_PHYS 2
321#define MCM_ADDR_MEM 3
322#define MCM_ADDR_GENERIC 7
323
324#define MSR_IA32_TSC 0x10
325#define MSR_IA32_APICBASE 0x1b
326#define MSR_IA32_APICBASE_BSP (1<<8)
327#define MSR_IA32_APICBASE_ENABLE (1<<11)
328#define MSR_IA32_APICBASE_EXTD (1 << 10)
329#define MSR_IA32_APICBASE_BASE (0xfffffU<<12)
330#define MSR_IA32_FEATURE_CONTROL 0x0000003a
331#define MSR_TSC_ADJUST 0x0000003b
332#define MSR_IA32_TSCDEADLINE 0x6e0
333
334#define FEATURE_CONTROL_LOCKED (1<<0)
335#define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX (1<<2)
336#define FEATURE_CONTROL_LMCE (1<<20)
337
338#define MSR_P6_PERFCTR0 0xc1
339
340#define MSR_IA32_SMBASE 0x9e
341#define MSR_MTRRcap 0xfe
342#define MSR_MTRRcap_VCNT 8
343#define MSR_MTRRcap_FIXRANGE_SUPPORT (1 << 8)
344#define MSR_MTRRcap_WC_SUPPORTED (1 << 10)
345
346#define MSR_IA32_SYSENTER_CS 0x174
347#define MSR_IA32_SYSENTER_ESP 0x175
348#define MSR_IA32_SYSENTER_EIP 0x176
349
350#define MSR_MCG_CAP 0x179
351#define MSR_MCG_STATUS 0x17a
352#define MSR_MCG_CTL 0x17b
353#define MSR_MCG_EXT_CTL 0x4d0
354
355#define MSR_P6_EVNTSEL0 0x186
356
357#define MSR_IA32_PERF_STATUS 0x198
358
359#define MSR_IA32_MISC_ENABLE 0x1a0
360
361#define MSR_IA32_MISC_ENABLE_DEFAULT 1
362
363#define MSR_MTRRphysBase(reg) (0x200 + 2 * (reg))
364#define MSR_MTRRphysMask(reg) (0x200 + 2 * (reg) + 1)
365
366#define MSR_MTRRphysIndex(addr) ((((addr) & ~1u) - 0x200) / 2)
367
368#define MSR_MTRRfix64K_00000 0x250
369#define MSR_MTRRfix16K_80000 0x258
370#define MSR_MTRRfix16K_A0000 0x259
371#define MSR_MTRRfix4K_C0000 0x268
372#define MSR_MTRRfix4K_C8000 0x269
373#define MSR_MTRRfix4K_D0000 0x26a
374#define MSR_MTRRfix4K_D8000 0x26b
375#define MSR_MTRRfix4K_E0000 0x26c
376#define MSR_MTRRfix4K_E8000 0x26d
377#define MSR_MTRRfix4K_F0000 0x26e
378#define MSR_MTRRfix4K_F8000 0x26f
379
380#define MSR_PAT 0x277
381
382#define MSR_MTRRdefType 0x2ff
383
384#define MSR_CORE_PERF_FIXED_CTR0 0x309
385#define MSR_CORE_PERF_FIXED_CTR1 0x30a
386#define MSR_CORE_PERF_FIXED_CTR2 0x30b
387#define MSR_CORE_PERF_FIXED_CTR_CTRL 0x38d
388#define MSR_CORE_PERF_GLOBAL_STATUS 0x38e
389#define MSR_CORE_PERF_GLOBAL_CTRL 0x38f
390#define MSR_CORE_PERF_GLOBAL_OVF_CTRL 0x390
391
392#define MSR_MC0_CTL 0x400
393#define MSR_MC0_STATUS 0x401
394#define MSR_MC0_ADDR 0x402
395#define MSR_MC0_MISC 0x403
396
397#define MSR_EFER 0xc0000080
398
399#define MSR_EFER_SCE (1 << 0)
400#define MSR_EFER_LME (1 << 8)
401#define MSR_EFER_LMA (1 << 10)
402#define MSR_EFER_NXE (1 << 11)
403#define MSR_EFER_SVME (1 << 12)
404#define MSR_EFER_FFXSR (1 << 14)
405
406#define MSR_STAR 0xc0000081
407#define MSR_LSTAR 0xc0000082
408#define MSR_CSTAR 0xc0000083
409#define MSR_FMASK 0xc0000084
410#define MSR_FSBASE 0xc0000100
411#define MSR_GSBASE 0xc0000101
412#define MSR_KERNELGSBASE 0xc0000102
413#define MSR_TSC_AUX 0xc0000103
414
415#define MSR_VM_HSAVE_PA 0xc0010117
416
417#define MSR_IA32_BNDCFGS 0x00000d90
418#define MSR_IA32_XSS 0x00000da0
419
420#define XSTATE_FP_BIT 0
421#define XSTATE_SSE_BIT 1
422#define XSTATE_YMM_BIT 2
423#define XSTATE_BNDREGS_BIT 3
424#define XSTATE_BNDCSR_BIT 4
425#define XSTATE_OPMASK_BIT 5
426#define XSTATE_ZMM_Hi256_BIT 6
427#define XSTATE_Hi16_ZMM_BIT 7
428#define XSTATE_PKRU_BIT 9
429
430#define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT)
431#define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT)
432#define XSTATE_YMM_MASK (1ULL << XSTATE_YMM_BIT)
433#define XSTATE_BNDREGS_MASK (1ULL << XSTATE_BNDREGS_BIT)
434#define XSTATE_BNDCSR_MASK (1ULL << XSTATE_BNDCSR_BIT)
435#define XSTATE_OPMASK_MASK (1ULL << XSTATE_OPMASK_BIT)
436#define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT)
437#define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT)
438#define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT)
439
440
441typedef enum FeatureWord {
442 FEAT_1_EDX,
443 FEAT_1_ECX,
444 FEAT_7_0_EBX,
445 FEAT_7_0_ECX,
446 FEAT_7_0_EDX,
447 FEAT_8000_0001_EDX,
448 FEAT_8000_0001_ECX,
449 FEAT_8000_0007_EDX,
450 FEAT_C000_0001_EDX,
451 FEAT_KVM,
452 FEAT_HYPERV_EAX,
453 FEAT_HYPERV_EBX,
454 FEAT_HYPERV_EDX,
455 FEAT_SVM,
456 FEAT_XSAVE,
457 FEAT_6_EAX,
458 FEAT_XSAVE_COMP_LO,
459 FEAT_XSAVE_COMP_HI,
460 FEATURE_WORDS,
461} FeatureWord;
462
463typedef uint32_t FeatureWordArray[FEATURE_WORDS];
464
465
466#define CPUID_FP87 (1U << 0)
467#define CPUID_VME (1U << 1)
468#define CPUID_DE (1U << 2)
469#define CPUID_PSE (1U << 3)
470#define CPUID_TSC (1U << 4)
471#define CPUID_MSR (1U << 5)
472#define CPUID_PAE (1U << 6)
473#define CPUID_MCE (1U << 7)
474#define CPUID_CX8 (1U << 8)
475#define CPUID_APIC (1U << 9)
476#define CPUID_SEP (1U << 11)
477#define CPUID_MTRR (1U << 12)
478#define CPUID_PGE (1U << 13)
479#define CPUID_MCA (1U << 14)
480#define CPUID_CMOV (1U << 15)
481#define CPUID_PAT (1U << 16)
482#define CPUID_PSE36 (1U << 17)
483#define CPUID_PN (1U << 18)
484#define CPUID_CLFLUSH (1U << 19)
485#define CPUID_DTS (1U << 21)
486#define CPUID_ACPI (1U << 22)
487#define CPUID_MMX (1U << 23)
488#define CPUID_FXSR (1U << 24)
489#define CPUID_SSE (1U << 25)
490#define CPUID_SSE2 (1U << 26)
491#define CPUID_SS (1U << 27)
492#define CPUID_HT (1U << 28)
493#define CPUID_TM (1U << 29)
494#define CPUID_IA64 (1U << 30)
495#define CPUID_PBE (1U << 31)
496
497#define CPUID_EXT_SSE3 (1U << 0)
498#define CPUID_EXT_PCLMULQDQ (1U << 1)
499#define CPUID_EXT_DTES64 (1U << 2)
500#define CPUID_EXT_MONITOR (1U << 3)
501#define CPUID_EXT_DSCPL (1U << 4)
502#define CPUID_EXT_VMX (1U << 5)
503#define CPUID_EXT_SMX (1U << 6)
504#define CPUID_EXT_EST (1U << 7)
505#define CPUID_EXT_TM2 (1U << 8)
506#define CPUID_EXT_SSSE3 (1U << 9)
507#define CPUID_EXT_CID (1U << 10)
508#define CPUID_EXT_FMA (1U << 12)
509#define CPUID_EXT_CX16 (1U << 13)
510#define CPUID_EXT_XTPR (1U << 14)
511#define CPUID_EXT_PDCM (1U << 15)
512#define CPUID_EXT_PCID (1U << 17)
513#define CPUID_EXT_DCA (1U << 18)
514#define CPUID_EXT_SSE41 (1U << 19)
515#define CPUID_EXT_SSE42 (1U << 20)
516#define CPUID_EXT_X2APIC (1U << 21)
517#define CPUID_EXT_MOVBE (1U << 22)
518#define CPUID_EXT_POPCNT (1U << 23)
519#define CPUID_EXT_TSC_DEADLINE_TIMER (1U << 24)
520#define CPUID_EXT_AES (1U << 25)
521#define CPUID_EXT_XSAVE (1U << 26)
522#define CPUID_EXT_OSXSAVE (1U << 27)
523#define CPUID_EXT_AVX (1U << 28)
524#define CPUID_EXT_F16C (1U << 29)
525#define CPUID_EXT_RDRAND (1U << 30)
526#define CPUID_EXT_HYPERVISOR (1U << 31)
527
528#define CPUID_EXT2_FPU (1U << 0)
529#define CPUID_EXT2_VME (1U << 1)
530#define CPUID_EXT2_DE (1U << 2)
531#define CPUID_EXT2_PSE (1U << 3)
532#define CPUID_EXT2_TSC (1U << 4)
533#define CPUID_EXT2_MSR (1U << 5)
534#define CPUID_EXT2_PAE (1U << 6)
535#define CPUID_EXT2_MCE (1U << 7)
536#define CPUID_EXT2_CX8 (1U << 8)
537#define CPUID_EXT2_APIC (1U << 9)
538#define CPUID_EXT2_SYSCALL (1U << 11)
539#define CPUID_EXT2_MTRR (1U << 12)
540#define CPUID_EXT2_PGE (1U << 13)
541#define CPUID_EXT2_MCA (1U << 14)
542#define CPUID_EXT2_CMOV (1U << 15)
543#define CPUID_EXT2_PAT (1U << 16)
544#define CPUID_EXT2_PSE36 (1U << 17)
545#define CPUID_EXT2_MP (1U << 19)
546#define CPUID_EXT2_NX (1U << 20)
547#define CPUID_EXT2_MMXEXT (1U << 22)
548#define CPUID_EXT2_MMX (1U << 23)
549#define CPUID_EXT2_FXSR (1U << 24)
550#define CPUID_EXT2_FFXSR (1U << 25)
551#define CPUID_EXT2_PDPE1GB (1U << 26)
552#define CPUID_EXT2_RDTSCP (1U << 27)
553#define CPUID_EXT2_LM (1U << 29)
554#define CPUID_EXT2_3DNOWEXT (1U << 30)
555#define CPUID_EXT2_3DNOW (1U << 31)
556
557
558#define CPUID_EXT2_AMD_ALIASES (CPUID_EXT2_FPU | CPUID_EXT2_VME | \
559 CPUID_EXT2_DE | CPUID_EXT2_PSE | \
560 CPUID_EXT2_TSC | CPUID_EXT2_MSR | \
561 CPUID_EXT2_PAE | CPUID_EXT2_MCE | \
562 CPUID_EXT2_CX8 | CPUID_EXT2_APIC | \
563 CPUID_EXT2_MTRR | CPUID_EXT2_PGE | \
564 CPUID_EXT2_MCA | CPUID_EXT2_CMOV | \
565 CPUID_EXT2_PAT | CPUID_EXT2_PSE36 | \
566 CPUID_EXT2_MMX | CPUID_EXT2_FXSR)
567
568#define CPUID_EXT3_LAHF_LM (1U << 0)
569#define CPUID_EXT3_CMP_LEG (1U << 1)
570#define CPUID_EXT3_SVM (1U << 2)
571#define CPUID_EXT3_EXTAPIC (1U << 3)
572#define CPUID_EXT3_CR8LEG (1U << 4)
573#define CPUID_EXT3_ABM (1U << 5)
574#define CPUID_EXT3_SSE4A (1U << 6)
575#define CPUID_EXT3_MISALIGNSSE (1U << 7)
576#define CPUID_EXT3_3DNOWPREFETCH (1U << 8)
577#define CPUID_EXT3_OSVW (1U << 9)
578#define CPUID_EXT3_IBS (1U << 10)
579#define CPUID_EXT3_XOP (1U << 11)
580#define CPUID_EXT3_SKINIT (1U << 12)
581#define CPUID_EXT3_WDT (1U << 13)
582#define CPUID_EXT3_LWP (1U << 15)
583#define CPUID_EXT3_FMA4 (1U << 16)
584#define CPUID_EXT3_TCE (1U << 17)
585#define CPUID_EXT3_NODEID (1U << 19)
586#define CPUID_EXT3_TBM (1U << 21)
587#define CPUID_EXT3_TOPOEXT (1U << 22)
588#define CPUID_EXT3_PERFCORE (1U << 23)
589#define CPUID_EXT3_PERFNB (1U << 24)
590
591#define CPUID_SVM_NPT (1U << 0)
592#define CPUID_SVM_LBRV (1U << 1)
593#define CPUID_SVM_SVMLOCK (1U << 2)
594#define CPUID_SVM_NRIPSAVE (1U << 3)
595#define CPUID_SVM_TSCSCALE (1U << 4)
596#define CPUID_SVM_VMCBCLEAN (1U << 5)
597#define CPUID_SVM_FLUSHASID (1U << 6)
598#define CPUID_SVM_DECODEASSIST (1U << 7)
599#define CPUID_SVM_PAUSEFILTER (1U << 10)
600#define CPUID_SVM_PFTHRESHOLD (1U << 12)
601
602#define CPUID_7_0_EBX_FSGSBASE (1U << 0)
603#define CPUID_7_0_EBX_BMI1 (1U << 3)
604#define CPUID_7_0_EBX_HLE (1U << 4)
605#define CPUID_7_0_EBX_AVX2 (1U << 5)
606#define CPUID_7_0_EBX_SMEP (1U << 7)
607#define CPUID_7_0_EBX_BMI2 (1U << 8)
608#define CPUID_7_0_EBX_ERMS (1U << 9)
609#define CPUID_7_0_EBX_INVPCID (1U << 10)
610#define CPUID_7_0_EBX_RTM (1U << 11)
611#define CPUID_7_0_EBX_MPX (1U << 14)
612#define CPUID_7_0_EBX_AVX512F (1U << 16)
613#define CPUID_7_0_EBX_AVX512DQ (1U << 17)
614#define CPUID_7_0_EBX_RDSEED (1U << 18)
615#define CPUID_7_0_EBX_ADX (1U << 19)
616#define CPUID_7_0_EBX_SMAP (1U << 20)
617#define CPUID_7_0_EBX_AVX512IFMA (1U << 21)
618#define CPUID_7_0_EBX_PCOMMIT (1U << 22)
619#define CPUID_7_0_EBX_CLFLUSHOPT (1U << 23)
620#define CPUID_7_0_EBX_CLWB (1U << 24)
621#define CPUID_7_0_EBX_AVX512PF (1U << 26)
622#define CPUID_7_0_EBX_AVX512ER (1U << 27)
623#define CPUID_7_0_EBX_AVX512CD (1U << 28)
624#define CPUID_7_0_EBX_AVX512BW (1U << 30)
625#define CPUID_7_0_EBX_AVX512VL (1U << 31)
626
627#define CPUID_7_0_ECX_VBMI (1U << 1)
628#define CPUID_7_0_ECX_UMIP (1U << 2)
629#define CPUID_7_0_ECX_PKU (1U << 3)
630#define CPUID_7_0_ECX_OSPKE (1U << 4)
631#define CPUID_7_0_ECX_RDPID (1U << 22)
632
633#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
634#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
635
636#define CPUID_XSAVE_XSAVEOPT (1U << 0)
637#define CPUID_XSAVE_XSAVEC (1U << 1)
638#define CPUID_XSAVE_XGETBV1 (1U << 2)
639#define CPUID_XSAVE_XSAVES (1U << 3)
640
641#define CPUID_6_EAX_ARAT (1U << 2)
642
643
644#define CPUID_APM_INVTSC (1U << 8)
645
646#define CPUID_VENDOR_SZ 12
647
648#define CPUID_VENDOR_INTEL_1 0x756e6547
649#define CPUID_VENDOR_INTEL_2 0x49656e69
650#define CPUID_VENDOR_INTEL_3 0x6c65746e
651#define CPUID_VENDOR_INTEL "GenuineIntel"
652
653#define CPUID_VENDOR_AMD_1 0x68747541
654#define CPUID_VENDOR_AMD_2 0x69746e65
655#define CPUID_VENDOR_AMD_3 0x444d4163
656#define CPUID_VENDOR_AMD "AuthenticAMD"
657
658#define CPUID_VENDOR_VIA "CentaurHauls"
659
660#define CPUID_MWAIT_IBE (1U << 1)
661#define CPUID_MWAIT_EMX (1U << 0)
662
663
664#define CPUID_TOPOLOGY_LEVEL_INVALID (0U << 8)
665#define CPUID_TOPOLOGY_LEVEL_SMT (1U << 8)
666#define CPUID_TOPOLOGY_LEVEL_CORE (2U << 8)
667
668#ifndef HYPERV_SPINLOCK_NEVER_RETRY
669#define HYPERV_SPINLOCK_NEVER_RETRY 0xFFFFFFFF
670#endif
671
672#define EXCP00_DIVZ 0
673#define EXCP01_DB 1
674#define EXCP02_NMI 2
675#define EXCP03_INT3 3
676#define EXCP04_INTO 4
677#define EXCP05_BOUND 5
678#define EXCP06_ILLOP 6
679#define EXCP07_PREX 7
680#define EXCP08_DBLE 8
681#define EXCP09_XERR 9
682#define EXCP0A_TSS 10
683#define EXCP0B_NOSEG 11
684#define EXCP0C_STACK 12
685#define EXCP0D_GPF 13
686#define EXCP0E_PAGE 14
687#define EXCP10_COPR 16
688#define EXCP11_ALGN 17
689#define EXCP12_MCHK 18
690
691#define EXCP_SYSCALL 0x100
692
693
694
695#define CPU_INTERRUPT_POLL CPU_INTERRUPT_TGT_EXT_1
696#define CPU_INTERRUPT_SMI CPU_INTERRUPT_TGT_EXT_2
697#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3
698#define CPU_INTERRUPT_MCE CPU_INTERRUPT_TGT_EXT_4
699#define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_INT_0
700#define CPU_INTERRUPT_SIPI CPU_INTERRUPT_TGT_INT_1
701#define CPU_INTERRUPT_TPR CPU_INTERRUPT_TGT_INT_2
702
703
704#define CPU_INTERRUPT_INIT CPU_INTERRUPT_RESET
705
706
707
708
709
710
711
712
713typedef enum {
714 CC_OP_DYNAMIC,
715 CC_OP_EFLAGS,
716
717 CC_OP_MULB,
718 CC_OP_MULW,
719 CC_OP_MULL,
720 CC_OP_MULQ,
721
722 CC_OP_ADDB,
723 CC_OP_ADDW,
724 CC_OP_ADDL,
725 CC_OP_ADDQ,
726
727 CC_OP_ADCB,
728 CC_OP_ADCW,
729 CC_OP_ADCL,
730 CC_OP_ADCQ,
731
732 CC_OP_SUBB,
733 CC_OP_SUBW,
734 CC_OP_SUBL,
735 CC_OP_SUBQ,
736
737 CC_OP_SBBB,
738 CC_OP_SBBW,
739 CC_OP_SBBL,
740 CC_OP_SBBQ,
741
742 CC_OP_LOGICB,
743 CC_OP_LOGICW,
744 CC_OP_LOGICL,
745 CC_OP_LOGICQ,
746
747 CC_OP_INCB,
748 CC_OP_INCW,
749 CC_OP_INCL,
750 CC_OP_INCQ,
751
752 CC_OP_DECB,
753 CC_OP_DECW,
754 CC_OP_DECL,
755 CC_OP_DECQ,
756
757 CC_OP_SHLB,
758 CC_OP_SHLW,
759 CC_OP_SHLL,
760 CC_OP_SHLQ,
761
762 CC_OP_SARB,
763 CC_OP_SARW,
764 CC_OP_SARL,
765 CC_OP_SARQ,
766
767 CC_OP_BMILGB,
768 CC_OP_BMILGW,
769 CC_OP_BMILGL,
770 CC_OP_BMILGQ,
771
772 CC_OP_ADCX,
773 CC_OP_ADOX,
774 CC_OP_ADCOX,
775
776 CC_OP_CLR,
777
778 CC_OP_NB,
779} CCOp;
780
781typedef struct SegmentCache {
782 uint32_t selector;
783 target_ulong base;
784 uint32_t limit;
785 uint32_t flags;
786} SegmentCache;
787
788#define MMREG_UNION(n, bits) \
789 union n { \
790 uint8_t _b_##n[(bits)/8]; \
791 uint16_t _w_##n[(bits)/16]; \
792 uint32_t _l_##n[(bits)/32]; \
793 uint64_t _q_##n[(bits)/64]; \
794 float32 _s_##n[(bits)/32]; \
795 float64 _d_##n[(bits)/64]; \
796 }
797
798typedef MMREG_UNION(ZMMReg, 512) ZMMReg;
799typedef MMREG_UNION(MMXReg, 64) MMXReg;
800
801typedef struct BNDReg {
802 uint64_t lb;
803 uint64_t ub;
804} BNDReg;
805
806typedef struct BNDCSReg {
807 uint64_t cfgu;
808 uint64_t sts;
809} BNDCSReg;
810
811#define BNDCFG_ENABLE 1ULL
812#define BNDCFG_BNDPRESERVE 2ULL
813#define BNDCFG_BDIR_MASK TARGET_PAGE_MASK
814
815#ifdef HOST_WORDS_BIGENDIAN
816#define ZMM_B(n) _b_ZMMReg[63 - (n)]
817#define ZMM_W(n) _w_ZMMReg[31 - (n)]
818#define ZMM_L(n) _l_ZMMReg[15 - (n)]
819#define ZMM_S(n) _s_ZMMReg[15 - (n)]
820#define ZMM_Q(n) _q_ZMMReg[7 - (n)]
821#define ZMM_D(n) _d_ZMMReg[7 - (n)]
822
823#define MMX_B(n) _b_MMXReg[7 - (n)]
824#define MMX_W(n) _w_MMXReg[3 - (n)]
825#define MMX_L(n) _l_MMXReg[1 - (n)]
826#define MMX_S(n) _s_MMXReg[1 - (n)]
827#else
828#define ZMM_B(n) _b_ZMMReg[n]
829#define ZMM_W(n) _w_ZMMReg[n]
830#define ZMM_L(n) _l_ZMMReg[n]
831#define ZMM_S(n) _s_ZMMReg[n]
832#define ZMM_Q(n) _q_ZMMReg[n]
833#define ZMM_D(n) _d_ZMMReg[n]
834
835#define MMX_B(n) _b_MMXReg[n]
836#define MMX_W(n) _w_MMXReg[n]
837#define MMX_L(n) _l_MMXReg[n]
838#define MMX_S(n) _s_MMXReg[n]
839#endif
840#define MMX_Q(n) _q_MMXReg[n]
841
842typedef union {
843 floatx80 d __attribute__((aligned(16)));
844 MMXReg mmx;
845} FPReg;
846
847typedef struct {
848 uint64_t base;
849 uint64_t mask;
850} MTRRVar;
851
852#define CPU_NB_REGS64 16
853#define CPU_NB_REGS32 8
854
855#ifdef TARGET_X86_64
856#define CPU_NB_REGS CPU_NB_REGS64
857#else
858#define CPU_NB_REGS CPU_NB_REGS32
859#endif
860
861#define MAX_FIXED_COUNTERS 3
862#define MAX_GP_COUNTERS (MSR_IA32_PERF_STATUS - MSR_P6_EVNTSEL0)
863
864#define NB_MMU_MODES 3
865#define TARGET_INSN_START_EXTRA_WORDS 1
866
867#define NB_OPMASK_REGS 8
868
869
870
871
872#define UNASSIGNED_APIC_ID 0xFFFFFFFF
873
874typedef union X86LegacyXSaveArea {
875 struct {
876 uint16_t fcw;
877 uint16_t fsw;
878 uint8_t ftw;
879 uint8_t reserved;
880 uint16_t fpop;
881 uint64_t fpip;
882 uint64_t fpdp;
883 uint32_t mxcsr;
884 uint32_t mxcsr_mask;
885 FPReg fpregs[8];
886 uint8_t xmm_regs[16][16];
887 };
888 uint8_t data[512];
889} X86LegacyXSaveArea;
890
891typedef struct X86XSaveHeader {
892 uint64_t xstate_bv;
893 uint64_t xcomp_bv;
894 uint64_t reserve0;
895 uint8_t reserved[40];
896} X86XSaveHeader;
897
898
899typedef struct XSaveAVX {
900 uint8_t ymmh[16][16];
901} XSaveAVX;
902
903
904typedef struct XSaveBNDREG {
905 BNDReg bnd_regs[4];
906} XSaveBNDREG;
907
908
909typedef union XSaveBNDCSR {
910 BNDCSReg bndcsr;
911 uint8_t data[64];
912} XSaveBNDCSR;
913
914
915typedef struct XSaveOpmask {
916 uint64_t opmask_regs[NB_OPMASK_REGS];
917} XSaveOpmask;
918
919
920typedef struct XSaveZMM_Hi256 {
921 uint8_t zmm_hi256[16][32];
922} XSaveZMM_Hi256;
923
924
925typedef struct XSaveHi16_ZMM {
926 uint8_t hi16_zmm[16][64];
927} XSaveHi16_ZMM;
928
929
930typedef struct XSavePKRU {
931 uint32_t pkru;
932 uint32_t padding;
933} XSavePKRU;
934
935typedef struct X86XSaveArea {
936 X86LegacyXSaveArea legacy;
937 X86XSaveHeader header;
938
939
940
941
942 XSaveAVX avx_state;
943 uint8_t padding[960 - 576 - sizeof(XSaveAVX)];
944
945 XSaveBNDREG bndreg_state;
946 XSaveBNDCSR bndcsr_state;
947
948 XSaveOpmask opmask_state;
949 XSaveZMM_Hi256 zmm_hi256_state;
950 XSaveHi16_ZMM hi16_zmm_state;
951
952 XSavePKRU pkru_state;
953} X86XSaveArea;
954
955QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, avx_state) != 0x240);
956QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) != 0x100);
957QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndreg_state) != 0x3c0);
958QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) != 0x40);
959QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, bndcsr_state) != 0x400);
960QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) != 0x40);
961QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, opmask_state) != 0x440);
962QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) != 0x40);
963QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, zmm_hi256_state) != 0x480);
964QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) != 0x200);
965QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, hi16_zmm_state) != 0x680);
966QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) != 0x400);
967QEMU_BUILD_BUG_ON(offsetof(X86XSaveArea, pkru_state) != 0xA80);
968QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) != 0x8);
969
970typedef enum TPRAccess {
971 TPR_ACCESS_READ,
972 TPR_ACCESS_WRITE,
973} TPRAccess;
974
975typedef struct CPUX86State {
976
977 target_ulong regs[CPU_NB_REGS];
978 target_ulong eip;
979 target_ulong eflags;
980
981
982
983
984 target_ulong cc_dst;
985 target_ulong cc_src;
986 target_ulong cc_src2;
987 uint32_t cc_op;
988 int32_t df;
989 uint32_t hflags;
990
991 uint32_t hflags2;
992
993
994 SegmentCache segs[6];
995 SegmentCache ldt;
996 SegmentCache tr;
997 SegmentCache gdt;
998 SegmentCache idt;
999
1000 target_ulong cr[5];
1001 int32_t a20_mask;
1002
1003 BNDReg bnd_regs[4];
1004 BNDCSReg bndcs_regs;
1005 uint64_t msr_bndcfgs;
1006 uint64_t efer;
1007
1008
1009 struct {} start_init_save;
1010
1011
1012 unsigned int fpstt;
1013 uint16_t fpus;
1014 uint16_t fpuc;
1015 uint8_t fptags[8];
1016 FPReg fpregs[8];
1017
1018 uint16_t fpop;
1019 uint64_t fpip;
1020 uint64_t fpdp;
1021
1022
1023 float_status fp_status;
1024 floatx80 ft0;
1025
1026 float_status mmx_status;
1027 float_status sse_status;
1028 uint32_t mxcsr;
1029 ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32];
1030 ZMMReg xmm_t0;
1031 MMXReg mmx_t0;
1032
1033 uint64_t opmask_regs[NB_OPMASK_REGS];
1034
1035
1036 uint32_t sysenter_cs;
1037 target_ulong sysenter_esp;
1038 target_ulong sysenter_eip;
1039 uint64_t star;
1040
1041 uint64_t vm_hsave;
1042
1043#ifdef TARGET_X86_64
1044 target_ulong lstar;
1045 target_ulong cstar;
1046 target_ulong fmask;
1047 target_ulong kernelgsbase;
1048#endif
1049
1050 uint64_t tsc;
1051 uint64_t tsc_adjust;
1052 uint64_t tsc_deadline;
1053 uint64_t tsc_aux;
1054
1055 uint64_t xcr0;
1056
1057 uint64_t mcg_status;
1058 uint64_t msr_ia32_misc_enable;
1059 uint64_t msr_ia32_feature_control;
1060
1061 uint64_t msr_fixed_ctr_ctrl;
1062 uint64_t msr_global_ctrl;
1063 uint64_t msr_global_status;
1064 uint64_t msr_global_ovf_ctrl;
1065 uint64_t msr_fixed_counters[MAX_FIXED_COUNTERS];
1066 uint64_t msr_gp_counters[MAX_GP_COUNTERS];
1067 uint64_t msr_gp_evtsel[MAX_GP_COUNTERS];
1068
1069 uint64_t pat;
1070 uint32_t smbase;
1071
1072 uint32_t pkru;
1073
1074
1075 struct {} end_init_save;
1076
1077 uint64_t system_time_msr;
1078 uint64_t wall_clock_msr;
1079 uint64_t steal_time_msr;
1080 uint64_t async_pf_en_msr;
1081 uint64_t pv_eoi_en_msr;
1082
1083 uint64_t msr_hv_hypercall;
1084 uint64_t msr_hv_guest_os_id;
1085 uint64_t msr_hv_vapic;
1086 uint64_t msr_hv_tsc;
1087 uint64_t msr_hv_crash_params[HV_X64_MSR_CRASH_PARAMS];
1088 uint64_t msr_hv_runtime;
1089 uint64_t msr_hv_synic_control;
1090 uint64_t msr_hv_synic_version;
1091 uint64_t msr_hv_synic_evt_page;
1092 uint64_t msr_hv_synic_msg_page;
1093 uint64_t msr_hv_synic_sint[HV_SYNIC_SINT_COUNT];
1094 uint64_t msr_hv_stimer_config[HV_SYNIC_STIMER_COUNT];
1095 uint64_t msr_hv_stimer_count[HV_SYNIC_STIMER_COUNT];
1096
1097
1098 int error_code;
1099 int exception_is_int;
1100 target_ulong exception_next_eip;
1101 target_ulong dr[8];
1102 union {
1103 struct CPUBreakpoint *cpu_breakpoint[4];
1104 struct CPUWatchpoint *cpu_watchpoint[4];
1105 };
1106 int old_exception;
1107
1108 uint64_t vm_vmcb;
1109 uint64_t tsc_offset;
1110 uint64_t intercept;
1111 uint16_t intercept_cr_read;
1112 uint16_t intercept_cr_write;
1113 uint16_t intercept_dr_read;
1114 uint16_t intercept_dr_write;
1115 uint32_t intercept_exceptions;
1116 uint8_t v_tpr;
1117
1118
1119 uint8_t nmi_injected;
1120 uint8_t nmi_pending;
1121
1122 CPU_COMMON
1123
1124
1125 struct {} end_reset_fields;
1126
1127
1128
1129 uint32_t cpuid_min_level, cpuid_min_xlevel, cpuid_min_xlevel2;
1130
1131 uint32_t cpuid_max_level, cpuid_max_xlevel, cpuid_max_xlevel2;
1132
1133 uint32_t cpuid_level, cpuid_xlevel, cpuid_xlevel2;
1134 uint32_t cpuid_vendor1;
1135 uint32_t cpuid_vendor2;
1136 uint32_t cpuid_vendor3;
1137 uint32_t cpuid_version;
1138 FeatureWordArray features;
1139 uint32_t cpuid_model[12];
1140
1141
1142 uint64_t mtrr_fixed[11];
1143 uint64_t mtrr_deftype;
1144 MTRRVar mtrr_var[MSR_MTRRcap_VCNT];
1145
1146
1147 uint32_t mp_state;
1148 int32_t exception_injected;
1149 int32_t interrupt_injected;
1150 uint8_t soft_interrupt;
1151 uint8_t has_error_code;
1152 uint32_t sipi_vector;
1153 bool tsc_valid;
1154 int64_t tsc_khz;
1155 int64_t user_tsc_khz;
1156 void *kvm_xsave_buf;
1157
1158 uint64_t mcg_cap;
1159 uint64_t mcg_ctl;
1160 uint64_t mcg_ext_ctl;
1161 uint64_t mce_banks[MCE_BANKS_DEF*4];
1162 uint64_t xstate_bv;
1163
1164
1165 uint16_t fpus_vmstate;
1166 uint16_t fptag_vmstate;
1167 uint16_t fpregs_format_vmstate;
1168
1169 uint64_t xss;
1170
1171 TPRAccess tpr_access_type;
1172} CPUX86State;
1173
1174struct kvm_msrs;
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185struct X86CPU {
1186
1187 CPUState parent_obj;
1188
1189
1190 CPUX86State env;
1191
1192 bool hyperv_vapic;
1193 bool hyperv_relaxed_timing;
1194 int hyperv_spinlock_attempts;
1195 char *hyperv_vendor_id;
1196 bool hyperv_time;
1197 bool hyperv_crash;
1198 bool hyperv_reset;
1199 bool hyperv_vpindex;
1200 bool hyperv_runtime;
1201 bool hyperv_synic;
1202 bool hyperv_stimer;
1203 bool check_cpuid;
1204 bool enforce_cpuid;
1205 bool expose_kvm;
1206 bool migratable;
1207 bool host_features;
1208 uint32_t apic_id;
1209
1210
1211 bool cache_info_passthrough;
1212
1213
1214 uint32_t filtered_features[FEATURE_WORDS];
1215
1216
1217
1218
1219
1220
1221 bool enable_pmu;
1222
1223
1224
1225
1226
1227 bool enable_lmce;
1228
1229
1230
1231
1232
1233 bool enable_l3_cache;
1234
1235
1236 bool enable_cpuid_0xb;
1237
1238
1239 bool full_cpuid_auto_level;
1240
1241
1242 bool fill_mtrr_mask;
1243
1244
1245 bool host_phys_bits;
1246
1247
1248 uint32_t phys_bits;
1249
1250
1251
1252 struct DeviceState *apic_state;
1253 struct MemoryRegion *cpu_as_root, *cpu_as_mem, *smram;
1254 Notifier machine_done;
1255
1256 struct kvm_msrs *kvm_msr_buf;
1257
1258 int32_t socket_id;
1259 int32_t core_id;
1260 int32_t thread_id;
1261};
1262
1263static inline X86CPU *x86_env_get_cpu(CPUX86State *env)
1264{
1265 return container_of(env, X86CPU, env);
1266}
1267
1268#define ENV_GET_CPU(e) CPU(x86_env_get_cpu(e))
1269
1270#define ENV_OFFSET offsetof(X86CPU, env)
1271
1272#ifndef CONFIG_USER_ONLY
1273extern struct VMStateDescription vmstate_x86_cpu;
1274#endif
1275
1276
1277
1278
1279
1280void x86_cpu_do_interrupt(CPUState *cpu);
1281bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req);
1282
1283int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu,
1284 int cpuid, void *opaque);
1285int x86_cpu_write_elf32_note(WriteCoreDumpFunction f, CPUState *cpu,
1286 int cpuid, void *opaque);
1287int x86_cpu_write_elf64_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1288 void *opaque);
1289int x86_cpu_write_elf32_qemunote(WriteCoreDumpFunction f, CPUState *cpu,
1290 void *opaque);
1291
1292void x86_cpu_get_memory_mapping(CPUState *cpu, MemoryMappingList *list,
1293 Error **errp);
1294
1295void x86_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
1296 int flags);
1297
1298hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr);
1299
1300int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
1301int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
1302
1303void x86_cpu_exec_enter(CPUState *cpu);
1304void x86_cpu_exec_exit(CPUState *cpu);
1305
1306X86CPU *cpu_x86_init(const char *cpu_model);
1307void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf);
1308int cpu_x86_support_mca_broadcast(CPUX86State *env);
1309
1310int cpu_get_pic_interrupt(CPUX86State *s);
1311
1312void cpu_set_ferr(CPUX86State *s);
1313
1314
1315
1316static inline void cpu_x86_load_seg_cache(CPUX86State *env,
1317 int seg_reg, unsigned int selector,
1318 target_ulong base,
1319 unsigned int limit,
1320 unsigned int flags)
1321{
1322 SegmentCache *sc;
1323 unsigned int new_hflags;
1324
1325 sc = &env->segs[seg_reg];
1326 sc->selector = selector;
1327 sc->base = base;
1328 sc->limit = limit;
1329 sc->flags = flags;
1330
1331
1332 {
1333 if (seg_reg == R_CS) {
1334#ifdef TARGET_X86_64
1335 if ((env->hflags & HF_LMA_MASK) && (flags & DESC_L_MASK)) {
1336
1337 env->hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
1338 env->hflags &= ~(HF_ADDSEG_MASK);
1339 } else
1340#endif
1341 {
1342
1343 new_hflags = (env->segs[R_CS].flags & DESC_B_MASK)
1344 >> (DESC_B_SHIFT - HF_CS32_SHIFT);
1345 env->hflags = (env->hflags & ~(HF_CS32_MASK | HF_CS64_MASK)) |
1346 new_hflags;
1347 }
1348 }
1349 if (seg_reg == R_SS) {
1350 int cpl = (flags >> DESC_DPL_SHIFT) & 3;
1351#if HF_CPL_MASK != 3
1352#error HF_CPL_MASK is hardcoded
1353#endif
1354 env->hflags = (env->hflags & ~HF_CPL_MASK) | cpl;
1355 }
1356 new_hflags = (env->segs[R_SS].flags & DESC_B_MASK)
1357 >> (DESC_B_SHIFT - HF_SS32_SHIFT);
1358 if (env->hflags & HF_CS64_MASK) {
1359
1360 } else if (!(env->cr[0] & CR0_PE_MASK) ||
1361 (env->eflags & VM_MASK) ||
1362 !(env->hflags & HF_CS32_MASK)) {
1363
1364
1365
1366
1367
1368 new_hflags |= HF_ADDSEG_MASK;
1369 } else {
1370 new_hflags |= ((env->segs[R_DS].base |
1371 env->segs[R_ES].base |
1372 env->segs[R_SS].base) != 0) <<
1373 HF_ADDSEG_SHIFT;
1374 }
1375 env->hflags = (env->hflags &
1376 ~(HF_SS32_MASK | HF_ADDSEG_MASK)) | new_hflags;
1377 }
1378}
1379
1380static inline void cpu_x86_load_seg_cache_sipi(X86CPU *cpu,
1381 uint8_t sipi_vector)
1382{
1383 CPUState *cs = CPU(cpu);
1384 CPUX86State *env = &cpu->env;
1385
1386 env->eip = 0;
1387 cpu_x86_load_seg_cache(env, R_CS, sipi_vector << 8,
1388 sipi_vector << 12,
1389 env->segs[R_CS].limit,
1390 env->segs[R_CS].flags);
1391 cs->halted = 0;
1392}
1393
1394int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
1395 target_ulong *base, unsigned int *limit,
1396 unsigned int *flags);
1397
1398
1399
1400void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f);
1401floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper);
1402
1403
1404
1405
1406void cpu_x86_load_seg(CPUX86State *s, int seg_reg, int selector);
1407void cpu_x86_fsave(CPUX86State *s, target_ulong ptr, int data32);
1408void cpu_x86_frstor(CPUX86State *s, target_ulong ptr, int data32);
1409
1410
1411
1412
1413int cpu_x86_signal_handler(int host_signum, void *pinfo,
1414 void *puc);
1415
1416
1417void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
1418 uint32_t *eax, uint32_t *ebx,
1419 uint32_t *ecx, uint32_t *edx);
1420void cpu_clear_apic_feature(CPUX86State *env);
1421void host_cpuid(uint32_t function, uint32_t count,
1422 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx);
1423
1424
1425int x86_cpu_handle_mmu_fault(CPUState *cpu, vaddr addr,
1426 int is_write, int mmu_idx);
1427void x86_cpu_set_a20(X86CPU *cpu, int a20_state);
1428
1429#ifndef CONFIG_USER_ONLY
1430uint8_t x86_ldub_phys(CPUState *cs, hwaddr addr);
1431uint32_t x86_lduw_phys(CPUState *cs, hwaddr addr);
1432uint32_t x86_ldl_phys(CPUState *cs, hwaddr addr);
1433uint64_t x86_ldq_phys(CPUState *cs, hwaddr addr);
1434void x86_stb_phys(CPUState *cs, hwaddr addr, uint8_t val);
1435void x86_stl_phys_notdirty(CPUState *cs, hwaddr addr, uint32_t val);
1436void x86_stw_phys(CPUState *cs, hwaddr addr, uint32_t val);
1437void x86_stl_phys(CPUState *cs, hwaddr addr, uint32_t val);
1438void x86_stq_phys(CPUState *cs, hwaddr addr, uint64_t val);
1439#endif
1440
1441void breakpoint_handler(CPUState *cs);
1442
1443
1444void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0);
1445void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3);
1446void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4);
1447void cpu_x86_update_dr7(CPUX86State *env, uint32_t new_dr7);
1448
1449
1450uint64_t cpu_get_tsc(CPUX86State *env);
1451
1452#define TARGET_PAGE_BITS 12
1453
1454#ifdef TARGET_X86_64
1455#define TARGET_PHYS_ADDR_SPACE_BITS 52
1456
1457
1458
1459#define TARGET_VIRT_ADDR_SPACE_BITS 47
1460#else
1461#define TARGET_PHYS_ADDR_SPACE_BITS 36
1462#define TARGET_VIRT_ADDR_SPACE_BITS 32
1463#endif
1464
1465
1466
1467# if defined(TARGET_X86_64)
1468# define TCG_PHYS_ADDR_BITS 40
1469# else
1470# define TCG_PHYS_ADDR_BITS 36
1471# endif
1472
1473#define PHYS_ADDR_MASK MAKE_64BIT_MASK(0, TCG_PHYS_ADDR_BITS)
1474
1475#define cpu_init(cpu_model) CPU(cpu_x86_init(cpu_model))
1476
1477#define cpu_signal_handler cpu_x86_signal_handler
1478#define cpu_list x86_cpu_list
1479
1480
1481#define MMU_MODE0_SUFFIX _ksmap
1482#define MMU_MODE1_SUFFIX _user
1483#define MMU_MODE2_SUFFIX _knosmap
1484#define MMU_KSMAP_IDX 0
1485#define MMU_USER_IDX 1
1486#define MMU_KNOSMAP_IDX 2
1487static inline int cpu_mmu_index(CPUX86State *env, bool ifetch)
1488{
1489 return (env->hflags & HF_CPL_MASK) == 3 ? MMU_USER_IDX :
1490 (!(env->hflags & HF_SMAP_MASK) || (env->eflags & AC_MASK))
1491 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1492}
1493
1494static inline int cpu_mmu_index_kernel(CPUX86State *env)
1495{
1496 return !(env->hflags & HF_SMAP_MASK) ? MMU_KNOSMAP_IDX :
1497 ((env->hflags & HF_CPL_MASK) < 3 && (env->eflags & AC_MASK))
1498 ? MMU_KNOSMAP_IDX : MMU_KSMAP_IDX;
1499}
1500
1501#define CC_DST (env->cc_dst)
1502#define CC_SRC (env->cc_src)
1503#define CC_SRC2 (env->cc_src2)
1504#define CC_OP (env->cc_op)
1505
1506
1507static inline target_long lshift(target_long x, int n)
1508{
1509 if (n >= 0) {
1510 return x << n;
1511 } else {
1512 return x >> (-n);
1513 }
1514}
1515
1516
1517#define FT0 (env->ft0)
1518#define ST0 (env->fpregs[env->fpstt].d)
1519#define ST(n) (env->fpregs[(env->fpstt + (n)) & 7].d)
1520#define ST1 ST(1)
1521
1522
1523void tcg_x86_init(void);
1524
1525#include "exec/cpu-all.h"
1526#include "svm.h"
1527
1528#if !defined(CONFIG_USER_ONLY)
1529#include "hw/i386/apic.h"
1530#endif
1531
1532static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc,
1533 target_ulong *cs_base, uint32_t *flags)
1534{
1535 *cs_base = env->segs[R_CS].base;
1536 *pc = *cs_base + env->eip;
1537 *flags = env->hflags |
1538 (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK | AC_MASK));
1539}
1540
1541void do_cpu_init(X86CPU *cpu);
1542void do_cpu_sipi(X86CPU *cpu);
1543
1544#define MCE_INJECT_BROADCAST 1
1545#define MCE_INJECT_UNCOND_AO 2
1546
1547void cpu_x86_inject_mce(Monitor *mon, X86CPU *cpu, int bank,
1548 uint64_t status, uint64_t mcg_status, uint64_t addr,
1549 uint64_t misc, int flags);
1550
1551
1552void QEMU_NORETURN raise_exception(CPUX86State *env, int exception_index);
1553void QEMU_NORETURN raise_exception_ra(CPUX86State *env, int exception_index,
1554 uintptr_t retaddr);
1555void QEMU_NORETURN raise_exception_err(CPUX86State *env, int exception_index,
1556 int error_code);
1557void QEMU_NORETURN raise_exception_err_ra(CPUX86State *env, int exception_index,
1558 int error_code, uintptr_t retaddr);
1559void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
1560 int error_code, int next_eip_addend);
1561
1562
1563extern const uint8_t parity_table[256];
1564uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
1565void update_fp_status(CPUX86State *env);
1566
1567static inline uint32_t cpu_compute_eflags(CPUX86State *env)
1568{
1569 return env->eflags | cpu_cc_compute_all(env, CC_OP) | (env->df & DF_MASK);
1570}
1571
1572
1573
1574
1575static inline void cpu_load_eflags(CPUX86State *env, int eflags,
1576 int update_mask)
1577{
1578 CC_SRC = eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
1579 CC_OP = CC_OP_EFLAGS;
1580 env->df = 1 - (2 * ((eflags >> 10) & 1));
1581 env->eflags = (env->eflags & ~update_mask) |
1582 (eflags & update_mask) | 0x2;
1583}
1584
1585
1586
1587static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
1588{
1589 env->efer = val;
1590 env->hflags &= ~(HF_LMA_MASK | HF_SVME_MASK);
1591 if (env->efer & MSR_EFER_LMA) {
1592 env->hflags |= HF_LMA_MASK;
1593 }
1594 if (env->efer & MSR_EFER_SVME) {
1595 env->hflags |= HF_SVME_MASK;
1596 }
1597}
1598
1599static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
1600{
1601 return ((MemTxAttrs) { .secure = (env->hflags & HF_SMM_MASK) != 0 });
1602}
1603
1604
1605void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
1606void cpu_set_fpuc(CPUX86State *env, uint16_t val);
1607
1608
1609void helper_lock_init(void);
1610
1611
1612void cpu_svm_check_intercept_param(CPUX86State *env1, uint32_t type,
1613 uint64_t param, uintptr_t retaddr);
1614void cpu_vmexit(CPUX86State *nenv, uint32_t exit_code, uint64_t exit_info_1,
1615 uintptr_t retaddr);
1616
1617
1618void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw);
1619
1620
1621void do_smm_enter(X86CPU *cpu);
1622void cpu_smm_update(X86CPU *cpu);
1623
1624
1625void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
1626void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip,
1627 TPRAccess access);
1628
1629
1630
1631
1632
1633
1634
1635
1636
1637
1638void x86_cpu_change_kvm_default(const char *prop, const char *value);
1639
1640
1641void cpu_sync_bndcs_hflags(CPUX86State *env);
1642
1643
1644const char *get_register_name_32(unsigned int reg);
1645
1646void enable_compat_apic_id_mode(void);
1647
1648#define APIC_DEFAULT_ADDRESS 0xfee00000
1649#define APIC_SPACE_SIZE 0x100000
1650
1651void x86_cpu_dump_local_apic_state(CPUState *cs, FILE *f,
1652 fprintf_function cpu_fprintf, int flags);
1653
1654
1655bool cpu_is_bsp(X86CPU *cpu);
1656
1657#endif
1658