LXR qemu/tcg/mips/tcg-target.h

   1/*
   2 * Tiny Code Generator for QEMU
   3 *
   4 * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org>
   5 * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net>
   6 * Based on i386/tcg-target.c - Copyright (c) 2008 Fabrice Bellard
   7 *
   8 * Permission is hereby granted, free of charge, to any person obtaining a copy
   9 * of this software and associated documentation files (the "Software"), to deal
  10 * in the Software without restriction, including without limitation the rights
  11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  12 * copies of the Software, and to permit persons to whom the Software is
  13 * furnished to do so, subject to the following conditions:
  14 *
  15 * The above copyright notice and this permission notice shall be included in
  16 * all copies or substantial portions of the Software.
  17 *
  18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  24 * THE SOFTWARE.
  25 */
  26
  27#ifndef MIPS_TCG_TARGET_H
  28#define MIPS_TCG_TARGET_H
  29
  30#define TCG_TARGET_INSN_UNIT_SIZE 4
  31#define TCG_TARGET_TLB_DISPLACEMENT_BITS 16
  32#define TCG_TARGET_NB_REGS 32
  33
  34typedef enum {
  35    TCG_REG_ZERO = 0,
  36    TCG_REG_AT,
  37    TCG_REG_V0,
  38    TCG_REG_V1,
  39    TCG_REG_A0,
  40    TCG_REG_A1,
  41    TCG_REG_A2,
  42    TCG_REG_A3,
  43    TCG_REG_T0,
  44    TCG_REG_T1,
  45    TCG_REG_T2,
  46    TCG_REG_T3,
  47    TCG_REG_T4,
  48    TCG_REG_T5,
  49    TCG_REG_T6,
  50    TCG_REG_T7,
  51    TCG_REG_S0,
  52    TCG_REG_S1,
  53    TCG_REG_S2,
  54    TCG_REG_S3,
  55    TCG_REG_S4,
  56    TCG_REG_S5,
  57    TCG_REG_S6,
  58    TCG_REG_S7,
  59    TCG_REG_T8,
  60    TCG_REG_T9,
  61    TCG_REG_K0,
  62    TCG_REG_K1,
  63    TCG_REG_GP,
  64    TCG_REG_SP,
  65    TCG_REG_S8,
  66    TCG_REG_RA,
  67
  68    TCG_REG_CALL_STACK = TCG_REG_SP,
  69    TCG_AREG0 = TCG_REG_S0,
  70} TCGReg;
  71
  72/* used for function call generation */
  73#define TCG_TARGET_STACK_ALIGN 8
  74#define TCG_TARGET_CALL_STACK_OFFSET 16
  75#define TCG_TARGET_CALL_ALIGN_ARGS 1
  76
  77/* MOVN/MOVZ instructions detection */
  78#if (defined(__mips_isa_rev) && (__mips_isa_rev >= 1)) || \
  79    defined(_MIPS_ARCH_LOONGSON2E) || defined(_MIPS_ARCH_LOONGSON2F) || \
  80    defined(_MIPS_ARCH_MIPS4)
  81#define use_movnz_instructions  1
  82#else
  83extern bool use_movnz_instructions;
  84#endif
  85
  86/* MIPS32 instruction set detection */
  87#if defined(__mips_isa_rev) && (__mips_isa_rev >= 1)
  88#define use_mips32_instructions  1
  89#else
  90extern bool use_mips32_instructions;
  91#endif
  92
  93/* MIPS32R2 instruction set detection */
  94#if defined(__mips_isa_rev) && (__mips_isa_rev >= 2)
  95#define use_mips32r2_instructions  1
  96#else
  97extern bool use_mips32r2_instructions;
  98#endif
  99
 100/* MIPS32R6 instruction set detection */
 101#if defined(__mips_isa_rev) && (__mips_isa_rev >= 6)
 102#define use_mips32r6_instructions  1
 103#else
 104#define use_mips32r6_instructions  0
 105#endif
 106
 107/* optional instructions */
 108#define TCG_TARGET_HAS_div_i32          1
 109#define TCG_TARGET_HAS_rem_i32          1
 110#define TCG_TARGET_HAS_not_i32          1
 111#define TCG_TARGET_HAS_nor_i32          1
 112#define TCG_TARGET_HAS_andc_i32         0
 113#define TCG_TARGET_HAS_orc_i32          0
 114#define TCG_TARGET_HAS_eqv_i32          0
 115#define TCG_TARGET_HAS_nand_i32         0
 116#define TCG_TARGET_HAS_mulu2_i32        (!use_mips32r6_instructions)
 117#define TCG_TARGET_HAS_muls2_i32        (!use_mips32r6_instructions)
 118#define TCG_TARGET_HAS_muluh_i32        1
 119#define TCG_TARGET_HAS_mulsh_i32        1
 120
 121/* optional instructions detected at runtime */
 122#define TCG_TARGET_HAS_movcond_i32      use_movnz_instructions
 123#define TCG_TARGET_HAS_bswap16_i32      use_mips32r2_instructions
 124#define TCG_TARGET_HAS_bswap32_i32      use_mips32r2_instructions
 125#define TCG_TARGET_HAS_deposit_i32      use_mips32r2_instructions
 126#define TCG_TARGET_HAS_ext8s_i32        use_mips32r2_instructions
 127#define TCG_TARGET_HAS_ext16s_i32       use_mips32r2_instructions
 128#define TCG_TARGET_HAS_rot_i32          use_mips32r2_instructions
 129
 130/* optional instructions automatically implemented */
 131#define TCG_TARGET_HAS_neg_i32          0 /* sub  rd, zero, rt   */
 132#define TCG_TARGET_HAS_ext8u_i32        0 /* andi rt, rs, 0xff   */
 133#define TCG_TARGET_HAS_ext16u_i32       0 /* andi rt, rs, 0xffff */
 134
 135#ifdef __OpenBSD__
 136#include <machine/sysarch.h>
 137#else
 138#include <sys/cachectl.h>
 139#endif
 140
 141static inline void flush_icache_range(uintptr_t start, uintptr_t stop)
 142{
 143    cacheflush ((void *)start, stop-start, ICACHE);
 144}
 145
 146#endif
 147