LXR qemu/tests/i440fx-test.c

   1/*
   2 * qtest I440FX test case
   3 *
   4 * Copyright IBM, Corp. 2012-2013
   5 * Copyright Red Hat, Inc. 2013
   6 *
   7 * Authors:
   8 *  Anthony Liguori   <aliguori@us.ibm.com>
   9 *  Laszlo Ersek      <lersek@redhat.com>
  10 *
  11 * This work is licensed under the terms of the GNU GPL, version 2 or later.
  12 * See the COPYING file in the top-level directory.
  13 */
  14
  15#include "qemu/osdep.h"
  16
  17#include "libqtest.h"
  18#include "libqos/pci.h"
  19#include "libqos/pci-pc.h"
  20#include "hw/pci/pci_regs.h"
  21
  22#define BROKEN 1
  23
  24typedef struct TestData
  25{
  26    int num_cpus;
  27} TestData;
  28
  29typedef struct FirmwareTestFixture {
  30    /* decides whether we're testing -bios or -pflash */
  31    bool is_bios;
  32} FirmwareTestFixture;
  33
  34static QPCIBus *test_start_get_bus(const TestData *s)
  35{
  36    char *cmdline;
  37
  38    cmdline = g_strdup_printf("-smp %d", s->num_cpus);
  39    qtest_start(cmdline);
  40    g_free(cmdline);
  41    return qpci_init_pc(NULL);
  42}
  43
  44static void test_i440fx_defaults(gconstpointer opaque)
  45{
  46    const TestData *s = opaque;
  47    QPCIBus *bus;
  48    QPCIDevice *dev;
  49    uint32_t value;
  50
  51    bus = test_start_get_bus(s);
  52    dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
  53    g_assert(dev != NULL);
  54
  55    /* 3.2.2 */
  56    g_assert_cmpint(qpci_config_readw(dev, PCI_VENDOR_ID), ==, 0x8086);
  57    /* 3.2.3 */
  58    g_assert_cmpint(qpci_config_readw(dev, PCI_DEVICE_ID), ==, 0x1237);
  59#ifndef BROKEN
  60    /* 3.2.4 */
  61    g_assert_cmpint(qpci_config_readw(dev, PCI_COMMAND), ==, 0x0006);
  62    /* 3.2.5 */
  63    g_assert_cmpint(qpci_config_readw(dev, PCI_STATUS), ==, 0x0280);
  64#endif
  65    /* 3.2.7 */
  66    g_assert_cmpint(qpci_config_readb(dev, PCI_CLASS_PROG), ==, 0x00);
  67    g_assert_cmpint(qpci_config_readw(dev, PCI_CLASS_DEVICE), ==, 0x0600);
  68    /* 3.2.8 */
  69    g_assert_cmpint(qpci_config_readb(dev, PCI_LATENCY_TIMER), ==, 0x00);
  70    /* 3.2.9 */
  71    g_assert_cmpint(qpci_config_readb(dev, PCI_HEADER_TYPE), ==, 0x00);
  72    /* 3.2.10 */
  73    g_assert_cmpint(qpci_config_readb(dev, PCI_BIST), ==, 0x00);
  74
  75    /* 3.2.11 */
  76    value = qpci_config_readw(dev, 0x50); /* PMCCFG */
  77    if (s->num_cpus == 1) { /* WPE */
  78        g_assert(!(value & (1 << 15)));
  79    } else {
  80        g_assert((value & (1 << 15)));
  81    }
  82
  83    g_assert(!(value & (1 << 6))); /* EPTE */
  84
  85    /* 3.2.12 */
  86    g_assert_cmpint(qpci_config_readb(dev, 0x52), ==, 0x00); /* DETURBO */
  87    /* 3.2.13 */
  88#ifndef BROKEN
  89    g_assert_cmpint(qpci_config_readb(dev, 0x53), ==, 0x80); /* DBC */
  90#endif
  91    /* 3.2.14 */
  92    g_assert_cmpint(qpci_config_readb(dev, 0x54), ==, 0x00); /* AXC */
  93    /* 3.2.15 */
  94    g_assert_cmpint(qpci_config_readw(dev, 0x55), ==, 0x0000); /* DRT */
  95#ifndef BROKEN
  96    /* 3.2.16 */
  97    g_assert_cmpint(qpci_config_readb(dev, 0x57), ==, 0x01); /* DRAMC */
  98    /* 3.2.17 */
  99    g_assert_cmpint(qpci_config_readb(dev, 0x58), ==, 0x10); /* DRAMT */
 100#endif
 101    /* 3.2.18 */
 102    g_assert_cmpint(qpci_config_readb(dev, 0x59), ==, 0x00); /* PAM0 */
 103    g_assert_cmpint(qpci_config_readb(dev, 0x5A), ==, 0x00); /* PAM1 */
 104    g_assert_cmpint(qpci_config_readb(dev, 0x5B), ==, 0x00); /* PAM2 */
 105    g_assert_cmpint(qpci_config_readb(dev, 0x5C), ==, 0x00); /* PAM3 */
 106    g_assert_cmpint(qpci_config_readb(dev, 0x5D), ==, 0x00); /* PAM4 */
 107    g_assert_cmpint(qpci_config_readb(dev, 0x5E), ==, 0x00); /* PAM5 */
 108    g_assert_cmpint(qpci_config_readb(dev, 0x5F), ==, 0x00); /* PAM6 */
 109#ifndef BROKEN
 110    /* 3.2.19 */
 111    g_assert_cmpint(qpci_config_readb(dev, 0x60), ==, 0x01); /* DRB0 */
 112    g_assert_cmpint(qpci_config_readb(dev, 0x61), ==, 0x01); /* DRB1 */
 113    g_assert_cmpint(qpci_config_readb(dev, 0x62), ==, 0x01); /* DRB2 */
 114    g_assert_cmpint(qpci_config_readb(dev, 0x63), ==, 0x01); /* DRB3 */
 115    g_assert_cmpint(qpci_config_readb(dev, 0x64), ==, 0x01); /* DRB4 */
 116    g_assert_cmpint(qpci_config_readb(dev, 0x65), ==, 0x01); /* DRB5 */
 117    g_assert_cmpint(qpci_config_readb(dev, 0x66), ==, 0x01); /* DRB6 */
 118    g_assert_cmpint(qpci_config_readb(dev, 0x67), ==, 0x01); /* DRB7 */
 119#endif
 120    /* 3.2.20 */
 121    g_assert_cmpint(qpci_config_readb(dev, 0x68), ==, 0x00); /* FDHC */
 122    /* 3.2.21 */
 123    g_assert_cmpint(qpci_config_readb(dev, 0x70), ==, 0x00); /* MTT */
 124#ifndef BROKEN
 125    /* 3.2.22 */
 126    g_assert_cmpint(qpci_config_readb(dev, 0x71), ==, 0x10); /* CLT */
 127#endif
 128    /* 3.2.23 */
 129    g_assert_cmpint(qpci_config_readb(dev, 0x72), ==, 0x02); /* SMRAM */
 130    /* 3.2.24 */
 131    g_assert_cmpint(qpci_config_readb(dev, 0x90), ==, 0x00); /* ERRCMD */
 132    /* 3.2.25 */
 133    g_assert_cmpint(qpci_config_readb(dev, 0x91), ==, 0x00); /* ERRSTS */
 134    /* 3.2.26 */
 135    g_assert_cmpint(qpci_config_readb(dev, 0x93), ==, 0x00); /* TRC */
 136
 137    qtest_end();
 138}
 139
 140#define PAM_RE 1
 141#define PAM_WE 2
 142
 143static void pam_set(QPCIDevice *dev, int index, int flags)
 144{
 145    int regno = 0x59 + (index / 2);
 146    uint8_t reg;
 147
 148    reg = qpci_config_readb(dev, regno);
 149    if (index & 1) {
 150        reg = (reg & 0x0F) | (flags << 4);
 151    } else {
 152        reg = (reg & 0xF0) | flags;
 153    }
 154    qpci_config_writeb(dev, regno, reg);
 155}
 156
 157static gboolean verify_area(uint32_t start, uint32_t end, uint8_t value)
 158{
 159    uint32_t size = end - start + 1;
 160    gboolean ret = TRUE;
 161    uint8_t *data;
 162    int i;
 163
 164    data = g_malloc0(size);
 165    memread(start, data, size);
 166
 167    g_test_message("verify_area: data[0] = 0x%x", data[0]);
 168
 169    for (i = 0; i < size; i++) {
 170        if (data[i] != value) {
 171            ret = FALSE;
 172            break;
 173        }
 174    }
 175
 176    g_free(data);
 177
 178    return ret;
 179}
 180
 181static void write_area(uint32_t start, uint32_t end, uint8_t value)
 182{
 183    uint32_t size = end - start + 1;
 184    uint8_t *data;
 185
 186    data = g_malloc(size);
 187    memset(data, value, size);
 188    memwrite(start, data, size);
 189
 190    g_free(data);
 191}
 192
 193static void test_i440fx_pam(gconstpointer opaque)
 194{
 195    const TestData *s = opaque;
 196    QPCIBus *bus;
 197    QPCIDevice *dev;
 198    int i;
 199    static struct {
 200        uint32_t start;
 201        uint32_t end;
 202    } pam_area[] = {
 203        { 0, 0 },             /* Reserved */
 204        { 0xF0000, 0xFFFFF }, /* BIOS Area */
 205        { 0xC0000, 0xC3FFF }, /* Option ROM */
 206        { 0xC4000, 0xC7FFF }, /* Option ROM */
 207        { 0xC8000, 0xCBFFF }, /* Option ROM */
 208        { 0xCC000, 0xCFFFF }, /* Option ROM */
 209        { 0xD0000, 0xD3FFF }, /* Option ROM */
 210        { 0xD4000, 0xD7FFF }, /* Option ROM */
 211        { 0xD8000, 0xDBFFF }, /* Option ROM */
 212        { 0xDC000, 0xDFFFF }, /* Option ROM */
 213        { 0xE0000, 0xE3FFF }, /* BIOS Extension */
 214        { 0xE4000, 0xE7FFF }, /* BIOS Extension */
 215        { 0xE8000, 0xEBFFF }, /* BIOS Extension */
 216        { 0xEC000, 0xEFFFF }, /* BIOS Extension */
 217    };
 218
 219    bus = test_start_get_bus(s);
 220    dev = qpci_device_find(bus, QPCI_DEVFN(0, 0));
 221    g_assert(dev != NULL);
 222
 223    for (i = 0; i < ARRAY_SIZE(pam_area); i++) {
 224        if (pam_area[i].start == pam_area[i].end) {
 225            continue;
 226        }
 227
 228        g_test_message("Checking area 0x%05x..0x%05x",
 229                       pam_area[i].start, pam_area[i].end);
 230        /* Switch to RE for the area */
 231        pam_set(dev, i, PAM_RE);
 232        /* Verify the RAM is all zeros */
 233        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0));
 234
 235        /* Switch to WE for the area */
 236        pam_set(dev, i, PAM_RE | PAM_WE);
 237        /* Write out a non-zero mask to the full area */
 238        write_area(pam_area[i].start, pam_area[i].end, 0x42);
 239
 240#ifndef BROKEN
 241        /* QEMU only supports a limited form of PAM */
 242
 243        /* Switch to !RE for the area */
 244        pam_set(dev, i, PAM_WE);
 245        /* Verify the area is not our mask */
 246        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 247#endif
 248
 249        /* Verify the area is our new mask */
 250        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x42));
 251
 252        /* Write out a new mask */
 253        write_area(pam_area[i].start, pam_area[i].end, 0x82);
 254
 255#ifndef BROKEN
 256        /* QEMU only supports a limited form of PAM */
 257
 258        /* Verify the area is not our mask */
 259        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 260
 261        /* Switch to RE for the area */
 262        pam_set(dev, i, PAM_RE | PAM_WE);
 263#endif
 264        /* Verify the area is our new mask */
 265        g_assert(verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 266
 267        /* Reset area */
 268        pam_set(dev, i, 0);
 269
 270        /* Verify the area is not our new mask */
 271        g_assert(!verify_area(pam_area[i].start, pam_area[i].end, 0x82));
 272    }
 273    qtest_end();
 274}
 275
 276#define BLOB_SIZE ((size_t)65536)
 277#define ISA_BIOS_MAXSZ ((size_t)(128 * 1024))
 278
 279/* Create a blob file, and return its absolute pathname as a dynamically
 280 * allocated string.
 281 * The file is closed before the function returns.
 282 * In case of error, NULL is returned. The function prints the error message.
 283 */
 284static char *create_blob_file(void)
 285{
 286    int ret, fd;
 287    char *pathname;
 288    GError *error = NULL;
 289
 290    ret = -1;
 291    fd = g_file_open_tmp("blob_XXXXXX", &pathname, &error);
 292    if (fd == -1) {
 293        fprintf(stderr, "unable to create blob file: %s\n", error->message);
 294        g_error_free(error);
 295    } else {
 296        if (ftruncate(fd, BLOB_SIZE) == -1) {
 297            fprintf(stderr, "ftruncate(\"%s\", %zu): %s\n", pathname,
 298                    BLOB_SIZE, strerror(errno));
 299        } else {
 300            void *buf;
 301
 302            buf = mmap(NULL, BLOB_SIZE, PROT_WRITE, MAP_SHARED, fd, 0);
 303            if (buf == MAP_FAILED) {
 304                fprintf(stderr, "mmap(\"%s\", %zu): %s\n", pathname, BLOB_SIZE,
 305                        strerror(errno));
 306            } else {
 307                size_t i;
 308
 309                for (i = 0; i < BLOB_SIZE; ++i) {
 310                    ((uint8_t *)buf)[i] = i;
 311                }
 312                munmap(buf, BLOB_SIZE);
 313                ret = 0;
 314            }
 315        }
 316        close(fd);
 317        if (ret == -1) {
 318            unlink(pathname);
 319            g_free(pathname);
 320        }
 321    }
 322
 323    return ret == -1 ? NULL : pathname;
 324}
 325
 326static void test_i440fx_firmware(FirmwareTestFixture *fixture,
 327                                 gconstpointer user_data)
 328{
 329    char *fw_pathname, *cmdline;
 330    uint8_t *buf;
 331    size_t i, isa_bios_size;
 332
 333    fw_pathname = create_blob_file();
 334    g_assert(fw_pathname != NULL);
 335
 336    /* Better hope the user didn't put metacharacters in TMPDIR and co. */
 337    cmdline = g_strdup_printf("-S %s%s", fixture->is_bios
 338                                         ? "-bios "
 339                                         : "-drive if=pflash,format=raw,file=",
 340                              fw_pathname);
 341    g_test_message("qemu cmdline: %s", cmdline);
 342    qtest_start(cmdline);
 343    g_free(cmdline);
 344
 345    /* QEMU has loaded the firmware (because qtest_start() only returns after
 346     * the QMP handshake completes). We must unlink the firmware blob right
 347     * here, because any assertion firing below would leak it in the
 348     * filesystem. This is also the reason why we recreate the blob every time
 349     * this function is invoked.
 350     */
 351    unlink(fw_pathname);
 352    g_free(fw_pathname);
 353
 354    /* check below 4G */
 355    buf = g_malloc0(BLOB_SIZE);
 356    memread(0x100000000ULL - BLOB_SIZE, buf, BLOB_SIZE);
 357    for (i = 0; i < BLOB_SIZE; ++i) {
 358        g_assert_cmphex(buf[i], ==, (uint8_t)i);
 359    }
 360
 361    /* check in ISA space too */
 362    memset(buf, 0, BLOB_SIZE);
 363    isa_bios_size = ISA_BIOS_MAXSZ < BLOB_SIZE ? ISA_BIOS_MAXSZ : BLOB_SIZE;
 364    memread(0x100000 - isa_bios_size, buf, isa_bios_size);
 365    for (i = 0; i < isa_bios_size; ++i) {
 366        g_assert_cmphex(buf[i], ==,
 367                        (uint8_t)((BLOB_SIZE - isa_bios_size) + i));
 368    }
 369
 370    g_free(buf);
 371    qtest_end();
 372}
 373
 374static void add_firmware_test(const char *testpath,
 375                              void (*setup_fixture)(FirmwareTestFixture *f,
 376                                                    gconstpointer test_data))
 377{
 378    qtest_add(testpath, FirmwareTestFixture, NULL, setup_fixture,
 379              test_i440fx_firmware, NULL);
 380}
 381
 382static void request_bios(FirmwareTestFixture *fixture,
 383                         gconstpointer user_data)
 384{
 385    fixture->is_bios = true;
 386}
 387
 388static void request_pflash(FirmwareTestFixture *fixture,
 389                           gconstpointer user_data)
 390{
 391    fixture->is_bios = false;
 392}
 393
 394int main(int argc, char **argv)
 395{
 396    TestData data;
 397
 398    g_test_init(&argc, &argv, NULL);
 399
 400    data.num_cpus = 1;
 401
 402    qtest_add_data_func("i440fx/defaults", &data, test_i440fx_defaults);
 403    qtest_add_data_func("i440fx/pam", &data, test_i440fx_pam);
 404    add_firmware_test("i440fx/firmware/bios", request_bios);
 405    add_firmware_test("i440fx/firmware/pflash", request_pflash);
 406
 407    return g_test_run();
 408}
 409