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8#include "qemu/osdep.h"
9#include "libqtest.h"
10#include "libqos/pci-spapr.h"
11#include "libqos/rtas.h"
12
13#include "hw/pci/pci_regs.h"
14
15#include "qemu-common.h"
16#include "qemu/host-utils.h"
17
18
19
20
21typedef struct QPCIWindow {
22 uint64_t pci_base;
23 uint64_t size;
24} QPCIWindow;
25
26typedef struct QPCIBusSPAPR {
27 QPCIBus bus;
28 QGuestAllocator *alloc;
29
30 uint64_t buid;
31
32 uint64_t pio_cpu_base;
33 QPCIWindow pio;
34
35 uint64_t mmio32_cpu_base;
36 QPCIWindow mmio32;
37} QPCIBusSPAPR;
38
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42
43
44
45static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr)
46{
47 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
48 return readb(s->pio_cpu_base + addr);
49}
50
51static void qpci_spapr_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
52{
53 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
54 writeb(s->pio_cpu_base + addr, val);
55}
56
57static uint16_t qpci_spapr_pio_readw(QPCIBus *bus, uint32_t addr)
58{
59 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
60 return bswap16(readw(s->pio_cpu_base + addr));
61}
62
63static void qpci_spapr_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
64{
65 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
66 writew(s->pio_cpu_base + addr, bswap16(val));
67}
68
69static uint32_t qpci_spapr_pio_readl(QPCIBus *bus, uint32_t addr)
70{
71 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
72 return bswap32(readl(s->pio_cpu_base + addr));
73}
74
75static void qpci_spapr_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
76{
77 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
78 writel(s->pio_cpu_base + addr, bswap32(val));
79}
80
81static uint64_t qpci_spapr_pio_readq(QPCIBus *bus, uint32_t addr)
82{
83 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
84 return bswap64(readq(s->pio_cpu_base + addr));
85}
86
87static void qpci_spapr_pio_writeq(QPCIBus *bus, uint32_t addr, uint64_t val)
88{
89 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
90 writeq(s->pio_cpu_base + addr, bswap64(val));
91}
92
93static void qpci_spapr_memread(QPCIBus *bus, uint32_t addr,
94 void *buf, size_t len)
95{
96 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
97 memread(s->mmio32_cpu_base + addr, buf, len);
98}
99
100static void qpci_spapr_memwrite(QPCIBus *bus, uint32_t addr,
101 const void *buf, size_t len)
102{
103 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
104 memwrite(s->mmio32_cpu_base + addr, buf, len);
105}
106
107static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
108{
109 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
110 uint32_t config_addr = (devfn << 8) | offset;
111 return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 1);
112}
113
114static uint16_t qpci_spapr_config_readw(QPCIBus *bus, int devfn, uint8_t offset)
115{
116 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
117 uint32_t config_addr = (devfn << 8) | offset;
118 return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 2);
119}
120
121static uint32_t qpci_spapr_config_readl(QPCIBus *bus, int devfn, uint8_t offset)
122{
123 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
124 uint32_t config_addr = (devfn << 8) | offset;
125 return qrtas_ibm_read_pci_config(s->alloc, s->buid, config_addr, 4);
126}
127
128static void qpci_spapr_config_writeb(QPCIBus *bus, int devfn, uint8_t offset,
129 uint8_t value)
130{
131 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
132 uint32_t config_addr = (devfn << 8) | offset;
133 qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 1, value);
134}
135
136static void qpci_spapr_config_writew(QPCIBus *bus, int devfn, uint8_t offset,
137 uint16_t value)
138{
139 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
140 uint32_t config_addr = (devfn << 8) | offset;
141 qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 2, value);
142}
143
144static void qpci_spapr_config_writel(QPCIBus *bus, int devfn, uint8_t offset,
145 uint32_t value)
146{
147 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
148 uint32_t config_addr = (devfn << 8) | offset;
149 qrtas_ibm_write_pci_config(s->alloc, s->buid, config_addr, 4, value);
150}
151
152#define SPAPR_PCI_BASE (1ULL << 45)
153
154#define SPAPR_PCI_MMIO32_WIN_SIZE 0x80000000
155#define SPAPR_PCI_IO_WIN_SIZE 0x10000
156
157QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
158{
159 QPCIBusSPAPR *ret;
160
161 ret = g_malloc(sizeof(*ret));
162
163 ret->alloc = alloc;
164
165 ret->bus.pio_readb = qpci_spapr_pio_readb;
166 ret->bus.pio_readw = qpci_spapr_pio_readw;
167 ret->bus.pio_readl = qpci_spapr_pio_readl;
168 ret->bus.pio_readq = qpci_spapr_pio_readq;
169
170 ret->bus.pio_writeb = qpci_spapr_pio_writeb;
171 ret->bus.pio_writew = qpci_spapr_pio_writew;
172 ret->bus.pio_writel = qpci_spapr_pio_writel;
173 ret->bus.pio_writeq = qpci_spapr_pio_writeq;
174
175 ret->bus.memread = qpci_spapr_memread;
176 ret->bus.memwrite = qpci_spapr_memwrite;
177
178 ret->bus.config_readb = qpci_spapr_config_readb;
179 ret->bus.config_readw = qpci_spapr_config_readw;
180 ret->bus.config_readl = qpci_spapr_config_readl;
181
182 ret->bus.config_writeb = qpci_spapr_config_writeb;
183 ret->bus.config_writew = qpci_spapr_config_writew;
184 ret->bus.config_writel = qpci_spapr_config_writel;
185
186
187
188
189 ret->buid = 0x800000020000000ULL;
190
191 ret->pio_cpu_base = SPAPR_PCI_BASE;
192 ret->pio.pci_base = 0;
193 ret->pio.size = SPAPR_PCI_IO_WIN_SIZE;
194
195
196 ret->mmio32_cpu_base = SPAPR_PCI_BASE + SPAPR_PCI_MMIO32_WIN_SIZE;
197 ret->mmio32.pci_base = 0x80000000;
198 ret->mmio32.size = SPAPR_PCI_MMIO32_WIN_SIZE;
199
200 ret->bus.pio_alloc_ptr = 0xc000;
201 ret->bus.mmio_alloc_ptr = ret->mmio32.pci_base;
202 ret->bus.mmio_limit = ret->mmio32.pci_base + ret->mmio32.size;
203
204 return &ret->bus;
205}
206
207void qpci_free_spapr(QPCIBus *bus)
208{
209 QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
210
211 g_free(s);
212}
213