LXR qemu/tests/tcg/mips/mips32-dsp/extrv_s

   1#include<stdio.h>
   2#include<assert.h>
   3
   4int main()
   5{
   6    int rt, rs, ach, acl, dsp;
   7    int result;
   8
   9    ach = 0x05;
  10    acl = 0xB4CB;
  11    dsp = 0x07;
  12    rs  = 0x03;
  13    result = 0x00007FFF;
  14
  15    __asm
  16        ("wrdsp %1, 0x01\n\t"
  17         "mthi %3, $ac1\n\t"
  18         "mtlo %4, $ac1\n\t"
  19         "extrv_s.h %0, $ac1, %2\n\t"
  20         "rddsp %1\n\t"
  21         : "=r"(rt), "+r"(dsp)
  22         : "r"(rs), "r"(ach), "r"(acl)
  23        );
  24    dsp = (dsp >> 23) & 0x01;
  25    assert(dsp == 1);
  26    assert(result == rt);
  27
  28    rs = 0x08;
  29    ach = 0xffffffff;
  30    acl = 0x12344321;
  31    result = 0xFFFF8000;
  32    __asm
  33        ("wrdsp %1, 0x01\n\t"
  34         "mthi %3, $ac1\n\t"
  35         "mtlo %4, $ac1\n\t"
  36         "extrv_s.h %0, $ac1, %2\n\t"
  37         "rddsp %1\n\t"
  38         : "=r"(rt), "+r"(dsp)
  39         : "r"(rs), "r"(ach), "r"(acl)
  40        );
  41    dsp = (dsp >> 23) & 0x01;
  42    assert(dsp == 1);
  43    assert(result == rt);
  44
  45    /* Clear dsp */
  46    dsp = 0;
  47    __asm
  48        ("wrdsp %0\n\t"
  49         :
  50         : "r"(dsp)
  51        );
  52
  53    rs = 0x04;
  54    ach = 0x00;
  55    acl = 0x4321;
  56    result = 0x432;
  57    __asm
  58        ("wrdsp %1, 0x01\n\t"
  59         "mthi %3, $ac1\n\t"
  60         "mtlo %4, $ac1\n\t"
  61         "extrv_s.h %0, $ac1, %2\n\t"
  62         "rddsp %1\n\t"
  63         : "=r"(rt), "+r"(dsp)
  64         : "r"(rs), "r"(ach), "r"(acl)
  65        );
  66    dsp = (dsp >> 23) & 0x01;
  67    assert(dsp == 0);
  68    assert(result == rt);
  69
  70    rs = 0x1C;
  71    ach = 0x123;
  72    acl = 0x87654321;
  73    result = 0x1238;
  74    __asm
  75        ("wrdsp %1, 0x01\n\t"
  76         "mthi %3, $ac1\n\t"
  77         "mtlo %4, $ac1\n\t"
  78         "extrv_s.h %0, $ac1, %2\n\t"
  79         "rddsp %1\n\t"
  80         : "=r"(rt), "+r"(dsp)
  81         : "r"(rs), "r"(ach), "r"(acl)
  82        );
  83    dsp = (dsp >> 23) & 0x01;
  84    assert(dsp == 0);
  85    assert(result == rt);
  86
  87    return 0;
  88}
  89