LXR qemu/hw/misc/arm

   1/*
   2 * ARM dummy L210, L220, PL310 cache controller.
   3 *
   4 * Copyright (c) 2010-2012 Calxeda
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms and conditions of the GNU General Public License,
   8 * version 2 or any later version, as published by the Free Software
   9 * Foundation.
  10 *
  11 * This program is distributed in the hope it will be useful, but WITHOUT
  12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  13 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  14 * more details.
  15 *
  16 * You should have received a copy of the GNU General Public License along with
  17 * this program.  If not, see <http://www.gnu.org/licenses/>.
  18 *
  19 */
  20
  21#include "qemu/osdep.h"
  22#include "hw/sysbus.h"
  23#include "qemu/log.h"
  24
  25/* L2C-310 r3p2 */
  26#define CACHE_ID 0x410000c8
  27
  28#define TYPE_ARM_L2X0 "l2x0"
  29#define ARM_L2X0(obj) OBJECT_CHECK(L2x0State, (obj), TYPE_ARM_L2X0)
  30
  31typedef struct L2x0State {
  32    SysBusDevice parent_obj;
  33
  34    MemoryRegion iomem;
  35    uint32_t cache_type;
  36    uint32_t ctrl;
  37    uint32_t aux_ctrl;
  38    uint32_t data_ctrl;
  39    uint32_t tag_ctrl;
  40    uint32_t filter_start;
  41    uint32_t filter_end;
  42} L2x0State;
  43
  44static const VMStateDescription vmstate_l2x0 = {
  45    .name = "l2x0",
  46    .version_id = 1,
  47    .minimum_version_id = 1,
  48    .fields = (VMStateField[]) {
  49        VMSTATE_UINT32(ctrl, L2x0State),
  50        VMSTATE_UINT32(aux_ctrl, L2x0State),
  51        VMSTATE_UINT32(data_ctrl, L2x0State),
  52        VMSTATE_UINT32(tag_ctrl, L2x0State),
  53        VMSTATE_UINT32(filter_start, L2x0State),
  54        VMSTATE_UINT32(filter_end, L2x0State),
  55        VMSTATE_END_OF_LIST()
  56    }
  57};
  58
  59
  60static uint64_t l2x0_priv_read(void *opaque, hwaddr offset,
  61                               unsigned size)
  62{
  63    uint32_t cache_data;
  64    L2x0State *s = (L2x0State *)opaque;
  65    offset &= 0xfff;
  66    if (offset >= 0x730 && offset < 0x800) {
  67        return 0; /* cache ops complete */
  68    }
  69    switch (offset) {
  70    case 0:
  71        return CACHE_ID;
  72    case 0x4:
  73        /* aux_ctrl values affect cache_type values */
  74        cache_data = (s->aux_ctrl & (7 << 17)) >> 15;
  75        cache_data |= (s->aux_ctrl & (1 << 16)) >> 16;
  76        return s->cache_type |= (cache_data << 18) | (cache_data << 6);
  77    case 0x100:
  78        return s->ctrl;
  79    case 0x104:
  80        return s->aux_ctrl;
  81    case 0x108:
  82        return s->tag_ctrl;
  83    case 0x10C:
  84        return s->data_ctrl;
  85    case 0xC00:
  86        return s->filter_start;
  87    case 0xC04:
  88        return s->filter_end;
  89    case 0xF40:
  90        return 0;
  91    case 0xF60:
  92        return 0;
  93    case 0xF80:
  94        return 0;
  95    default:
  96        qemu_log_mask(LOG_GUEST_ERROR,
  97                      "l2x0_priv_read: Bad offset %x\n", (int)offset);
  98        break;
  99    }
 100    return 0;
 101}
 102
 103static void l2x0_priv_write(void *opaque, hwaddr offset,
 104                            uint64_t value, unsigned size)
 105{
 106    L2x0State *s = (L2x0State *)opaque;
 107    offset &= 0xfff;
 108    if (offset >= 0x730 && offset < 0x800) {
 109        /* ignore */
 110        return;
 111    }
 112    switch (offset) {
 113    case 0x100:
 114        s->ctrl = value & 1;
 115        break;
 116    case 0x104:
 117        s->aux_ctrl = value;
 118        break;
 119    case 0x108:
 120        s->tag_ctrl = value;
 121        break;
 122    case 0x10C:
 123        s->data_ctrl = value;
 124        break;
 125    case 0xC00:
 126        s->filter_start = value;
 127        break;
 128    case 0xC04:
 129        s->filter_end = value;
 130        break;
 131    case 0xF40:
 132        return;
 133    case 0xF60:
 134        return;
 135    case 0xF80:
 136        return;
 137    default:
 138        qemu_log_mask(LOG_GUEST_ERROR,
 139                      "l2x0_priv_write: Bad offset %x\n", (int)offset);
 140        break;
 141    }
 142}
 143
 144static void l2x0_priv_reset(DeviceState *dev)
 145{
 146    L2x0State *s = ARM_L2X0(dev);
 147
 148    s->ctrl = 0;
 149    s->aux_ctrl = 0x02020000;
 150    s->tag_ctrl = 0;
 151    s->data_ctrl = 0;
 152    s->filter_start = 0;
 153    s->filter_end = 0;
 154}
 155
 156static const MemoryRegionOps l2x0_mem_ops = {
 157    .read = l2x0_priv_read,
 158    .write = l2x0_priv_write,
 159    .endianness = DEVICE_NATIVE_ENDIAN,
 160 };
 161
 162static void l2x0_priv_init(Object *obj)
 163{
 164    L2x0State *s = ARM_L2X0(obj);
 165    SysBusDevice *dev = SYS_BUS_DEVICE(obj);
 166
 167    memory_region_init_io(&s->iomem, obj, &l2x0_mem_ops, s,
 168                          "l2x0_cc", 0x1000);
 169    sysbus_init_mmio(dev, &s->iomem);
 170}
 171
 172static Property l2x0_properties[] = {
 173    DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100),
 174    DEFINE_PROP_END_OF_LIST(),
 175};
 176
 177static void l2x0_class_init(ObjectClass *klass, void *data)
 178{
 179    DeviceClass *dc = DEVICE_CLASS(klass);
 180
 181    dc->vmsd = &vmstate_l2x0;
 182    dc->props = l2x0_properties;
 183    dc->reset = l2x0_priv_reset;
 184}
 185
 186static const TypeInfo l2x0_info = {
 187    .name = TYPE_ARM_L2X0,
 188    .parent = TYPE_SYS_BUS_DEVICE,
 189    .instance_size = sizeof(L2x0State),
 190    .instance_init = l2x0_priv_init,
 191    .class_init = l2x0_class_init,
 192};
 193
 194static void l2x0_register_types(void)
 195{
 196    type_register_static(&l2x0_info);
 197}
 198
 199type_init(l2x0_register_types)
 200