qemu/hw/misc/xilinx_zynqmp_pmu_global.c
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   1/*
   2 * QEMU model of the PMU_GLOBAL
   3 *
   4 * Copyright (c) 2014 Xilinx Inc.
   5 *
   6 * Partly autogenerated by xregqemu.py 2014-09-01.
   7 * Written by Edgar E. Iglesias.
   8 *
   9 * Permission is hereby granted, free of charge, to any person obtaining a copy
  10 * of this software and associated documentation files (the "Software"), to deal
  11 * in the Software without restriction, including without limitation the rights
  12 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  13 * copies of the Software, and to permit persons to whom the Software is
  14 * furnished to do so, subject to the following conditions:
  15 *
  16 * The above copyright notice and this permission notice shall be included in
  17 * all copies or substantial portions of the Software.
  18 *
  19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  24 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  25 * THE SOFTWARE.
  26 */
  27
  28#include "qemu/osdep.h"
  29#include "hw/sysbus.h"
  30#include "hw/register-dep.h"
  31#include "qemu/bitops.h"
  32#include "qemu/log.h"
  33
  34#include "hw/fdt_generic_util.h"
  35
  36#ifndef XILINX_PMU_GLOBAL_ERR_DEBUG
  37#define XILINX_PMU_GLOBAL_ERR_DEBUG 0
  38#endif
  39
  40#define TYPE_XILINX_PMU_GLOBAL "xlnx,pmu_global"
  41
  42#define XILINX_PMU_GLOBAL(obj) \
  43     OBJECT_CHECK(PMU_GLOBAL, (obj), TYPE_XILINX_PMU_GLOBAL)
  44
  45DEP_REG32(GLOBAL_CNTRL, 0x0)
  46    DEP_FIELD(GLOBAL_CNTRL, MB_SLEEP, 1, 16)
  47    DEP_FIELD(GLOBAL_CNTRL, WRITE_QOS, 4, 12)
  48    DEP_FIELD(GLOBAL_CNTRL, READ_QOS, 4, 8)
  49    DEP_FIELD(GLOBAL_CNTRL, FW_IS_PRESENT, 1, 4)
  50    DEP_FIELD(GLOBAL_CNTRL, COHERENT, 1, 2)
  51    DEP_FIELD(GLOBAL_CNTRL, SLVERR_ENABLE, 1, 1)
  52    DEP_FIELD(GLOBAL_CNTRL, DONT_SLEEP, 1, 0)
  53DEP_REG32(PS_CNTRL, 0x4)
  54    DEP_FIELD(PS_CNTRL, PROG_GATE_STATUS, 1, 16)
  55    DEP_FIELD(PS_CNTRL, PROG_ENABLE, 1, 1)
  56    DEP_FIELD(PS_CNTRL, PROG_GATE, 1, 0)
  57DEP_REG32(APU_PWR_STATUS_INIT, 0x8)
  58    DEP_FIELD(APU_PWR_STATUS_INIT, ACPU3, 1, 3)
  59    DEP_FIELD(APU_PWR_STATUS_INIT, ACPU2, 1, 2)
  60    DEP_FIELD(APU_PWR_STATUS_INIT, ACPU1, 1, 1)
  61    DEP_FIELD(APU_PWR_STATUS_INIT, ACPU0, 1, 0)
  62DEP_REG32(ADDR_ERROR_STATUS, 0x10)
  63    DEP_FIELD(ADDR_ERROR_STATUS, STATUS, 1, 0)
  64DEP_REG32(ADDR_ERROR_INT_MASK, 0x14)
  65    DEP_FIELD(ADDR_ERROR_INT_MASK, MASK, 1, 0)
  66DEP_REG32(ADDR_ERROR_INT_EN, 0x18)
  67    DEP_FIELD(ADDR_ERROR_INT_EN, ENABLE, 1, 0)
  68DEP_REG32(ADDR_ERROR_INT_DIS, 0x1c)
  69    DEP_FIELD(ADDR_ERROR_INT_DIS, DISABLE, 1, 0)
  70DEP_REG32(GLOBAL_GEN_STORAGE0, 0x30)
  71DEP_REG32(GLOBAL_GEN_STORAGE1, 0x34)
  72DEP_REG32(GLOBAL_GEN_STORAGE2, 0x38)
  73DEP_REG32(GLOBAL_GEN_STORAGE3, 0x3c)
  74DEP_REG32(GLOBAL_GEN_STORAGE4, 0x40)
  75DEP_REG32(GLOBAL_GEN_STORAGE5, 0x44)
  76DEP_REG32(GLOBAL_GEN_STORAGE6, 0x48)
  77DEP_REG32(PERS_GLOB_GEN_STORAGE0, 0x50)
  78DEP_REG32(PERS_GLOB_GEN_STORAGE1, 0x54)
  79DEP_REG32(PERS_GLOB_GEN_STORAGE2, 0x58)
  80DEP_REG32(PERS_GLOB_GEN_STORAGE3, 0x5c)
  81DEP_REG32(PERS_GLOB_GEN_STORAGE4, 0x60)
  82DEP_REG32(PERS_GLOB_GEN_STORAGE5, 0x64)
  83DEP_REG32(PERS_GLOB_GEN_STORAGE6, 0x68)
  84DEP_REG32(PERS_GLOB_GEN_STORAGE7, 0x6c)
  85DEP_REG32(DDR_CNTRL, 0x70)
  86    DEP_FIELD(DDR_CNTRL, RET, 1, 0)
  87DEP_REG32(PWR_STATE, 0x100)
  88    DEP_FIELD(PWR_STATE, PL, 1, 23)
  89    DEP_FIELD(PWR_STATE, FP, 1, 22)
  90    DEP_FIELD(PWR_STATE, USB1, 1, 21)
  91    DEP_FIELD(PWR_STATE, USB0, 1, 20)
  92    DEP_FIELD(PWR_STATE, OCM_BANK3, 1, 19)
  93    DEP_FIELD(PWR_STATE, OCM_BANK2, 1, 18)
  94    DEP_FIELD(PWR_STATE, OCM_BANK1, 1, 17)
  95    DEP_FIELD(PWR_STATE, OCM_BANK0, 1, 16)
  96    DEP_FIELD(PWR_STATE, TCM1B, 1, 15)
  97    DEP_FIELD(PWR_STATE, TCM1A, 1, 14)
  98    DEP_FIELD(PWR_STATE, TCM0B, 1, 13)
  99    DEP_FIELD(PWR_STATE, TCM0A, 1, 12)
 100    DEP_FIELD(PWR_STATE, R5_1, 1, 11)
 101    DEP_FIELD(PWR_STATE, R5_0, 1, 10)
 102    DEP_FIELD(PWR_STATE, L2_BANK0, 1, 7)
 103    DEP_FIELD(PWR_STATE, PP1, 1, 5)
 104    DEP_FIELD(PWR_STATE, PP0, 1, 4)
 105    DEP_FIELD(PWR_STATE, ACPU3, 1, 3)
 106    DEP_FIELD(PWR_STATE, ACPU2, 1, 2)
 107    DEP_FIELD(PWR_STATE, ACPU1, 1, 1)
 108    DEP_FIELD(PWR_STATE, ACPU0, 1, 0)
 109DEP_REG32(AUX_PWR_STATE, 0x104)
 110    DEP_FIELD(AUX_PWR_STATE, ACPU3_EMULATION, 1, 31)
 111    DEP_FIELD(AUX_PWR_STATE, ACPU2_EMULATION, 1, 30)
 112    DEP_FIELD(AUX_PWR_STATE, ACPU1_EMULATION, 1, 29)
 113    DEP_FIELD(AUX_PWR_STATE, ACPU0_EMULATION, 1, 28)
 114    DEP_FIELD(AUX_PWR_STATE, RPU_EMULATION, 1, 27)
 115    DEP_FIELD(AUX_PWR_STATE, OCM_BANK3, 1, 19)
 116    DEP_FIELD(AUX_PWR_STATE, OCM_BANK2, 1, 18)
 117    DEP_FIELD(AUX_PWR_STATE, OCM_BANK1, 1, 17)
 118    DEP_FIELD(AUX_PWR_STATE, OCM_BANK0, 1, 16)
 119    DEP_FIELD(AUX_PWR_STATE, TCM1B, 1, 15)
 120    DEP_FIELD(AUX_PWR_STATE, TCM1A, 1, 14)
 121    DEP_FIELD(AUX_PWR_STATE, TCM0B, 1, 13)
 122    DEP_FIELD(AUX_PWR_STATE, TCM0A, 1, 12)
 123    DEP_FIELD(AUX_PWR_STATE, L2_BANK0, 1, 7)
 124DEP_REG32(RAM_RET_CNTRL, 0x108)
 125    DEP_FIELD(RAM_RET_CNTRL, OCM_BANK3, 1, 19)
 126    DEP_FIELD(RAM_RET_CNTRL, OCM_BANK2, 1, 18)
 127    DEP_FIELD(RAM_RET_CNTRL, OCM_BANK1, 1, 17)
 128    DEP_FIELD(RAM_RET_CNTRL, OCM_BANK0, 1, 16)
 129    DEP_FIELD(RAM_RET_CNTRL, TCM1B, 1, 15)
 130    DEP_FIELD(RAM_RET_CNTRL, TCM1A, 1, 14)
 131    DEP_FIELD(RAM_RET_CNTRL, TCM0B, 1, 13)
 132    DEP_FIELD(RAM_RET_CNTRL, TCM0A, 1, 12)
 133    DEP_FIELD(RAM_RET_CNTRL, L2_BANK0, 1, 7)
 134DEP_REG32(PWR_SUPPLY_STATUS, 0x10c)
 135    DEP_FIELD(PWR_SUPPLY_STATUS, VCC_INT, 1, 1)
 136    DEP_FIELD(PWR_SUPPLY_STATUS, VCC_PSINTFP, 1, 0)
 137DEP_REG32(REQ_PWRUP_STATUS, 0x110)
 138    DEP_FIELD(REQ_PWRUP_STATUS, PL, 1, 23)
 139    DEP_FIELD(REQ_PWRUP_STATUS, FP, 1, 22)
 140    DEP_FIELD(REQ_PWRUP_STATUS, USB1, 1, 21)
 141    DEP_FIELD(REQ_PWRUP_STATUS, USB0, 1, 20)
 142    DEP_FIELD(REQ_PWRUP_STATUS, OCM_BANK3, 1, 19)
 143    DEP_FIELD(REQ_PWRUP_STATUS, OCM_BANK2, 1, 18)
 144    DEP_FIELD(REQ_PWRUP_STATUS, OCM_BANK1, 1, 17)
 145    DEP_FIELD(REQ_PWRUP_STATUS, OCM_BANK0, 1, 16)
 146    DEP_FIELD(REQ_PWRUP_STATUS, TCM1B, 1, 15)
 147    DEP_FIELD(REQ_PWRUP_STATUS, TCM1A, 1, 14)
 148    DEP_FIELD(REQ_PWRUP_STATUS, TCM0B, 1, 13)
 149    DEP_FIELD(REQ_PWRUP_STATUS, TCM0A, 1, 12)
 150    DEP_FIELD(REQ_PWRUP_STATUS, RPU, 1, 10)
 151    DEP_FIELD(REQ_PWRUP_STATUS, L2_BANK0, 1, 7)
 152    DEP_FIELD(REQ_PWRUP_STATUS, PP1, 1, 5)
 153    DEP_FIELD(REQ_PWRUP_STATUS, PP0, 1, 4)
 154    DEP_FIELD(REQ_PWRUP_STATUS, ACPU3, 1, 3)
 155    DEP_FIELD(REQ_PWRUP_STATUS, ACPU2, 1, 2)
 156    DEP_FIELD(REQ_PWRUP_STATUS, ACPU1, 1, 1)
 157    DEP_FIELD(REQ_PWRUP_STATUS, ACPU0, 1, 0)
 158DEP_REG32(REQ_PWRUP_INT_MASK, 0x114)
 159    DEP_FIELD(REQ_PWRUP_INT_MASK, PL, 1, 23)
 160    DEP_FIELD(REQ_PWRUP_INT_MASK, FP, 1, 22)
 161    DEP_FIELD(REQ_PWRUP_INT_MASK, USB1, 1, 21)
 162    DEP_FIELD(REQ_PWRUP_INT_MASK, USB0, 1, 20)
 163    DEP_FIELD(REQ_PWRUP_INT_MASK, OCM_BANK3, 1, 19)
 164    DEP_FIELD(REQ_PWRUP_INT_MASK, OCM_BANK2, 1, 18)
 165    DEP_FIELD(REQ_PWRUP_INT_MASK, OCM_BANK1, 1, 17)
 166    DEP_FIELD(REQ_PWRUP_INT_MASK, OCM_BANK0, 1, 16)
 167    DEP_FIELD(REQ_PWRUP_INT_MASK, TCM1B, 1, 15)
 168    DEP_FIELD(REQ_PWRUP_INT_MASK, TCM1A, 1, 14)
 169    DEP_FIELD(REQ_PWRUP_INT_MASK, TCM0B, 1, 13)
 170    DEP_FIELD(REQ_PWRUP_INT_MASK, TCM0A, 1, 12)
 171    DEP_FIELD(REQ_PWRUP_INT_MASK, RPU, 1, 10)
 172    DEP_FIELD(REQ_PWRUP_INT_MASK, L2_BANK0, 1, 7)
 173    DEP_FIELD(REQ_PWRUP_INT_MASK, PP1, 1, 5)
 174    DEP_FIELD(REQ_PWRUP_INT_MASK, PP0, 1, 4)
 175    DEP_FIELD(REQ_PWRUP_INT_MASK, ACPU3, 1, 3)
 176    DEP_FIELD(REQ_PWRUP_INT_MASK, ACPU2, 1, 2)
 177    DEP_FIELD(REQ_PWRUP_INT_MASK, ACPU1, 1, 1)
 178    DEP_FIELD(REQ_PWRUP_INT_MASK, ACPU0, 1, 0)
 179DEP_REG32(REQ_PWRUP_INT_EN, 0x118)
 180    DEP_FIELD(REQ_PWRUP_INT_EN, PL, 1, 23)
 181    DEP_FIELD(REQ_PWRUP_INT_EN, FP, 1, 22)
 182    DEP_FIELD(REQ_PWRUP_INT_EN, USB1, 1, 21)
 183    DEP_FIELD(REQ_PWRUP_INT_EN, USB0, 1, 20)
 184    DEP_FIELD(REQ_PWRUP_INT_EN, OCM_BANK3, 1, 19)
 185    DEP_FIELD(REQ_PWRUP_INT_EN, OCM_BANK2, 1, 18)
 186    DEP_FIELD(REQ_PWRUP_INT_EN, OCM_BANK1, 1, 17)
 187    DEP_FIELD(REQ_PWRUP_INT_EN, OCM_BANK0, 1, 16)
 188    DEP_FIELD(REQ_PWRUP_INT_EN, TCM1B, 1, 15)
 189    DEP_FIELD(REQ_PWRUP_INT_EN, TCM1A, 1, 14)
 190    DEP_FIELD(REQ_PWRUP_INT_EN, TCM0B, 1, 13)
 191    DEP_FIELD(REQ_PWRUP_INT_EN, TCM0A, 1, 12)
 192    DEP_FIELD(REQ_PWRUP_INT_EN, RPU, 1, 10)
 193    DEP_FIELD(REQ_PWRUP_INT_EN, L2_BANK0, 1, 7)
 194    DEP_FIELD(REQ_PWRUP_INT_EN, PP1, 1, 5)
 195    DEP_FIELD(REQ_PWRUP_INT_EN, PP0, 1, 4)
 196    DEP_FIELD(REQ_PWRUP_INT_EN, ACPU3, 1, 3)
 197    DEP_FIELD(REQ_PWRUP_INT_EN, ACPU2, 1, 2)
 198    DEP_FIELD(REQ_PWRUP_INT_EN, ACPU1, 1, 1)
 199    DEP_FIELD(REQ_PWRUP_INT_EN, ACPU0, 1, 0)
 200DEP_REG32(REQ_PWRUP_INT_DIS, 0x11c)
 201    DEP_FIELD(REQ_PWRUP_INT_DIS, PL, 1, 23)
 202    DEP_FIELD(REQ_PWRUP_INT_DIS, FP, 1, 22)
 203    DEP_FIELD(REQ_PWRUP_INT_DIS, USB1, 1, 21)
 204    DEP_FIELD(REQ_PWRUP_INT_DIS, USB0, 1, 20)
 205    DEP_FIELD(REQ_PWRUP_INT_DIS, OCM_BANK3, 1, 19)
 206    DEP_FIELD(REQ_PWRUP_INT_DIS, OCM_BANK2, 1, 18)
 207    DEP_FIELD(REQ_PWRUP_INT_DIS, OCM_BANK1, 1, 17)
 208    DEP_FIELD(REQ_PWRUP_INT_DIS, OCM_BANK0, 1, 16)
 209    DEP_FIELD(REQ_PWRUP_INT_DIS, TCM1B, 1, 15)
 210    DEP_FIELD(REQ_PWRUP_INT_DIS, TCM1A, 1, 14)
 211    DEP_FIELD(REQ_PWRUP_INT_DIS, TCM0B, 1, 13)
 212    DEP_FIELD(REQ_PWRUP_INT_DIS, TCM0A, 1, 12)
 213    DEP_FIELD(REQ_PWRUP_INT_DIS, RPU, 1, 10)
 214    DEP_FIELD(REQ_PWRUP_INT_DIS, L2_BANK0, 1, 7)
 215    DEP_FIELD(REQ_PWRUP_INT_DIS, PP1, 1, 5)
 216    DEP_FIELD(REQ_PWRUP_INT_DIS, PP0, 1, 4)
 217    DEP_FIELD(REQ_PWRUP_INT_DIS, ACPU3, 1, 3)
 218    DEP_FIELD(REQ_PWRUP_INT_DIS, ACPU2, 1, 2)
 219    DEP_FIELD(REQ_PWRUP_INT_DIS, ACPU1, 1, 1)
 220    DEP_FIELD(REQ_PWRUP_INT_DIS, ACPU0, 1, 0)
 221DEP_REG32(REQ_PWRUP_TRIG, 0x120)
 222    DEP_FIELD(REQ_PWRUP_TRIG, PL, 1, 23)
 223    DEP_FIELD(REQ_PWRUP_TRIG, FP, 1, 22)
 224    DEP_FIELD(REQ_PWRUP_TRIG, USB1, 1, 21)
 225    DEP_FIELD(REQ_PWRUP_TRIG, USB0, 1, 20)
 226    DEP_FIELD(REQ_PWRUP_TRIG, OCM_BANK3, 1, 19)
 227    DEP_FIELD(REQ_PWRUP_TRIG, OCM_BANK2, 1, 18)
 228    DEP_FIELD(REQ_PWRUP_TRIG, OCM_BANK1, 1, 17)
 229    DEP_FIELD(REQ_PWRUP_TRIG, OCM_BANK0, 1, 16)
 230    DEP_FIELD(REQ_PWRUP_TRIG, TCM1B, 1, 15)
 231    DEP_FIELD(REQ_PWRUP_TRIG, TCM1A, 1, 14)
 232    DEP_FIELD(REQ_PWRUP_TRIG, TCM0B, 1, 13)
 233    DEP_FIELD(REQ_PWRUP_TRIG, TCM0A, 1, 12)
 234    DEP_FIELD(REQ_PWRUP_TRIG, RPU, 1, 10)
 235    DEP_FIELD(REQ_PWRUP_TRIG, L2_BANK0, 1, 7)
 236    DEP_FIELD(REQ_PWRUP_TRIG, PP1, 1, 5)
 237    DEP_FIELD(REQ_PWRUP_TRIG, PP0, 1, 4)
 238    DEP_FIELD(REQ_PWRUP_TRIG, ACPU3, 1, 3)
 239    DEP_FIELD(REQ_PWRUP_TRIG, ACPU2, 1, 2)
 240    DEP_FIELD(REQ_PWRUP_TRIG, ACPU1, 1, 1)
 241    DEP_FIELD(REQ_PWRUP_TRIG, ACPU0, 1, 0)
 242DEP_REG32(REQ_PWRDWN_STATUS, 0x210)
 243    DEP_FIELD(REQ_PWRDWN_STATUS, PL, 1, 23)
 244    DEP_FIELD(REQ_PWRDWN_STATUS, FP, 1, 22)
 245    DEP_FIELD(REQ_PWRDWN_STATUS, USB1, 1, 21)
 246    DEP_FIELD(REQ_PWRDWN_STATUS, USB0, 1, 20)
 247    DEP_FIELD(REQ_PWRDWN_STATUS, OCM_BANK3, 1, 19)
 248    DEP_FIELD(REQ_PWRDWN_STATUS, OCM_BANK2, 1, 18)
 249    DEP_FIELD(REQ_PWRDWN_STATUS, OCM_BANK1, 1, 17)
 250    DEP_FIELD(REQ_PWRDWN_STATUS, OCM_BANK0, 1, 16)
 251    DEP_FIELD(REQ_PWRDWN_STATUS, TCM1B, 1, 15)
 252    DEP_FIELD(REQ_PWRDWN_STATUS, TCM1A, 1, 14)
 253    DEP_FIELD(REQ_PWRDWN_STATUS, TCM0B, 1, 13)
 254    DEP_FIELD(REQ_PWRDWN_STATUS, TCM0A, 1, 12)
 255    DEP_FIELD(REQ_PWRDWN_STATUS, RPU, 1, 10)
 256    DEP_FIELD(REQ_PWRDWN_STATUS, L2_BANK0, 1, 7)
 257    DEP_FIELD(REQ_PWRDWN_STATUS, PP1, 1, 5)
 258    DEP_FIELD(REQ_PWRDWN_STATUS, PP0, 1, 4)
 259    DEP_FIELD(REQ_PWRDWN_STATUS, ACPU3, 1, 3)
 260    DEP_FIELD(REQ_PWRDWN_STATUS, ACPU2, 1, 2)
 261    DEP_FIELD(REQ_PWRDWN_STATUS, ACPU1, 1, 1)
 262    DEP_FIELD(REQ_PWRDWN_STATUS, ACPU0, 1, 0)
 263DEP_REG32(REQ_PWRDWN_INT_MASK, 0x214)
 264    DEP_FIELD(REQ_PWRDWN_INT_MASK, PL, 1, 23)
 265    DEP_FIELD(REQ_PWRDWN_INT_MASK, FP, 1, 22)
 266    DEP_FIELD(REQ_PWRDWN_INT_MASK, USB1, 1, 21)
 267    DEP_FIELD(REQ_PWRDWN_INT_MASK, USB0, 1, 20)
 268    DEP_FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK3, 1, 19)
 269    DEP_FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK2, 1, 18)
 270    DEP_FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK1, 1, 17)
 271    DEP_FIELD(REQ_PWRDWN_INT_MASK, OCM_BANK0, 1, 16)
 272    DEP_FIELD(REQ_PWRDWN_INT_MASK, TCM1B, 1, 15)
 273    DEP_FIELD(REQ_PWRDWN_INT_MASK, TCM1A, 1, 14)
 274    DEP_FIELD(REQ_PWRDWN_INT_MASK, TCM0B, 1, 13)
 275    DEP_FIELD(REQ_PWRDWN_INT_MASK, TCM0A, 1, 12)
 276    DEP_FIELD(REQ_PWRDWN_INT_MASK, RPU, 1, 10)
 277    DEP_FIELD(REQ_PWRDWN_INT_MASK, L2_BANK0, 1, 7)
 278    DEP_FIELD(REQ_PWRDWN_INT_MASK, PP1, 1, 5)
 279    DEP_FIELD(REQ_PWRDWN_INT_MASK, PP0, 1, 4)
 280    DEP_FIELD(REQ_PWRDWN_INT_MASK, ACPU3, 1, 3)
 281    DEP_FIELD(REQ_PWRDWN_INT_MASK, ACPU2, 1, 2)
 282    DEP_FIELD(REQ_PWRDWN_INT_MASK, ACPU1, 1, 1)
 283    DEP_FIELD(REQ_PWRDWN_INT_MASK, ACPU0, 1, 0)
 284DEP_REG32(REQ_PWRDWN_INT_EN, 0x218)
 285    DEP_FIELD(REQ_PWRDWN_INT_EN, PL, 1, 23)
 286    DEP_FIELD(REQ_PWRDWN_INT_EN, FP, 1, 22)
 287    DEP_FIELD(REQ_PWRDWN_INT_EN, USB1, 1, 21)
 288    DEP_FIELD(REQ_PWRDWN_INT_EN, USB0, 1, 20)
 289    DEP_FIELD(REQ_PWRDWN_INT_EN, OCM_BANK3, 1, 19)
 290    DEP_FIELD(REQ_PWRDWN_INT_EN, OCM_BANK2, 1, 18)
 291    DEP_FIELD(REQ_PWRDWN_INT_EN, OCM_BANK1, 1, 17)
 292    DEP_FIELD(REQ_PWRDWN_INT_EN, OCM_BANK0, 1, 16)
 293    DEP_FIELD(REQ_PWRDWN_INT_EN, TCM1B, 1, 15)
 294    DEP_FIELD(REQ_PWRDWN_INT_EN, TCM1A, 1, 14)
 295    DEP_FIELD(REQ_PWRDWN_INT_EN, TCM0B, 1, 13)
 296    DEP_FIELD(REQ_PWRDWN_INT_EN, TCM0A, 1, 12)
 297    DEP_FIELD(REQ_PWRDWN_INT_EN, RPU, 1, 10)
 298    DEP_FIELD(REQ_PWRDWN_INT_EN, L2_BANK0, 1, 7)
 299    DEP_FIELD(REQ_PWRDWN_INT_EN, PP1, 1, 5)
 300    DEP_FIELD(REQ_PWRDWN_INT_EN, PP0, 1, 4)
 301    DEP_FIELD(REQ_PWRDWN_INT_EN, ACPU3, 1, 3)
 302    DEP_FIELD(REQ_PWRDWN_INT_EN, ACPU2, 1, 2)
 303    DEP_FIELD(REQ_PWRDWN_INT_EN, ACPU1, 1, 1)
 304    DEP_FIELD(REQ_PWRDWN_INT_EN, ACPU0, 1, 0)
 305DEP_REG32(REQ_PWRDWN_INT_DIS, 0x21c)
 306    DEP_FIELD(REQ_PWRDWN_INT_DIS, PL, 1, 23)
 307    DEP_FIELD(REQ_PWRDWN_INT_DIS, FP, 1, 22)
 308    DEP_FIELD(REQ_PWRDWN_INT_DIS, USB1, 1, 21)
 309    DEP_FIELD(REQ_PWRDWN_INT_DIS, USB0, 1, 20)
 310    DEP_FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK3, 1, 19)
 311    DEP_FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK2, 1, 18)
 312    DEP_FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK1, 1, 17)
 313    DEP_FIELD(REQ_PWRDWN_INT_DIS, OCM_BANK0, 1, 16)
 314    DEP_FIELD(REQ_PWRDWN_INT_DIS, TCM1B, 1, 15)
 315    DEP_FIELD(REQ_PWRDWN_INT_DIS, TCM1A, 1, 14)
 316    DEP_FIELD(REQ_PWRDWN_INT_DIS, TCM0B, 1, 13)
 317    DEP_FIELD(REQ_PWRDWN_INT_DIS, TCM0A, 1, 12)
 318    DEP_FIELD(REQ_PWRDWN_INT_DIS, RPU, 1, 10)
 319    DEP_FIELD(REQ_PWRDWN_INT_DIS, L2_BANK0, 1, 7)
 320    DEP_FIELD(REQ_PWRDWN_INT_DIS, PP1, 1, 5)
 321    DEP_FIELD(REQ_PWRDWN_INT_DIS, PP0, 1, 4)
 322    DEP_FIELD(REQ_PWRDWN_INT_DIS, ACPU3, 1, 3)
 323    DEP_FIELD(REQ_PWRDWN_INT_DIS, ACPU2, 1, 2)
 324    DEP_FIELD(REQ_PWRDWN_INT_DIS, ACPU1, 1, 1)
 325    DEP_FIELD(REQ_PWRDWN_INT_DIS, ACPU0, 1, 0)
 326DEP_REG32(REQ_PWRDWN_TRIG, 0x220)
 327    DEP_FIELD(REQ_PWRDWN_TRIG, PL, 1, 23)
 328    DEP_FIELD(REQ_PWRDWN_TRIG, FP, 1, 22)
 329    DEP_FIELD(REQ_PWRDWN_TRIG, USB1, 1, 21)
 330    DEP_FIELD(REQ_PWRDWN_TRIG, USB0, 1, 20)
 331    DEP_FIELD(REQ_PWRDWN_TRIG, OCM_BANK3, 1, 19)
 332    DEP_FIELD(REQ_PWRDWN_TRIG, OCM_BANK2, 1, 18)
 333    DEP_FIELD(REQ_PWRDWN_TRIG, OCM_BANK1, 1, 17)
 334    DEP_FIELD(REQ_PWRDWN_TRIG, OCM_BANK0, 1, 16)
 335    DEP_FIELD(REQ_PWRDWN_TRIG, TCM1B, 1, 15)
 336    DEP_FIELD(REQ_PWRDWN_TRIG, TCM1A, 1, 14)
 337    DEP_FIELD(REQ_PWRDWN_TRIG, TCM0B, 1, 13)
 338    DEP_FIELD(REQ_PWRDWN_TRIG, TCM0A, 1, 12)
 339    DEP_FIELD(REQ_PWRDWN_TRIG, RPU, 1, 10)
 340    DEP_FIELD(REQ_PWRDWN_TRIG, L2_BANK0, 1, 7)
 341    DEP_FIELD(REQ_PWRDWN_TRIG, PP1, 1, 5)
 342    DEP_FIELD(REQ_PWRDWN_TRIG, PP0, 1, 4)
 343    DEP_FIELD(REQ_PWRDWN_TRIG, ACPU3, 1, 3)
 344    DEP_FIELD(REQ_PWRDWN_TRIG, ACPU2, 1, 2)
 345    DEP_FIELD(REQ_PWRDWN_TRIG, ACPU1, 1, 1)
 346    DEP_FIELD(REQ_PWRDWN_TRIG, ACPU0, 1, 0)
 347DEP_REG32(REQ_ISO_STATUS, 0x310)
 348    DEP_FIELD(REQ_ISO_STATUS, FP_LOCKED, 1, 4)
 349    DEP_FIELD(REQ_ISO_STATUS, PL, 1, 1)
 350    DEP_FIELD(REQ_ISO_STATUS, FP, 1, 0)
 351DEP_REG32(REQ_ISO_INT_MASK, 0x314)
 352    DEP_FIELD(REQ_ISO_INT_MASK, FP_LOCKED, 1, 4)
 353    DEP_FIELD(REQ_ISO_INT_MASK, PL, 1, 1)
 354    DEP_FIELD(REQ_ISO_INT_MASK, FP, 1, 0)
 355DEP_REG32(REQ_ISO_INT_EN, 0x318)
 356    DEP_FIELD(REQ_ISO_INT_EN, FP_LOCKED, 1, 4)
 357    DEP_FIELD(REQ_ISO_INT_EN, PL, 1, 1)
 358    DEP_FIELD(REQ_ISO_INT_EN, FP, 1, 0)
 359DEP_REG32(REQ_ISO_INT_DIS, 0x31c)
 360    DEP_FIELD(REQ_ISO_INT_DIS, FP_LOCKED, 1, 4)
 361    DEP_FIELD(REQ_ISO_INT_DIS, PL, 1, 1)
 362    DEP_FIELD(REQ_ISO_INT_DIS, FP, 1, 0)
 363DEP_REG32(REQ_ISO_TRIG, 0x320)
 364    DEP_FIELD(REQ_ISO_TRIG, FP_LOCKED, 1, 4)
 365    DEP_FIELD(REQ_ISO_TRIG, PL, 1, 1)
 366    DEP_FIELD(REQ_ISO_TRIG, FP, 1, 0)
 367DEP_REG32(REQ_SWRST_STATUS, 0x410)
 368    DEP_FIELD(REQ_SWRST_STATUS, PL, 1, 31)
 369    DEP_FIELD(REQ_SWRST_STATUS, FP, 1, 30)
 370    DEP_FIELD(REQ_SWRST_STATUS, LP, 1, 29)
 371    DEP_FIELD(REQ_SWRST_STATUS, PS_ONLY, 1, 28)
 372    DEP_FIELD(REQ_SWRST_STATUS, IOU, 1, 27)
 373    DEP_FIELD(REQ_SWRST_STATUS, USB1, 1, 25)
 374    DEP_FIELD(REQ_SWRST_STATUS, USB0, 1, 24)
 375    DEP_FIELD(REQ_SWRST_STATUS, GEM3, 1, 23)
 376    DEP_FIELD(REQ_SWRST_STATUS, GEM2, 1, 22)
 377    DEP_FIELD(REQ_SWRST_STATUS, GEM1, 1, 21)
 378    DEP_FIELD(REQ_SWRST_STATUS, GEM0, 1, 20)
 379    DEP_FIELD(REQ_SWRST_STATUS, LS_R5, 1, 18)
 380    DEP_FIELD(REQ_SWRST_STATUS, R5_1, 1, 17)
 381    DEP_FIELD(REQ_SWRST_STATUS, R5_0, 1, 16)
 382    DEP_FIELD(REQ_SWRST_STATUS, DISPLAY_PORT, 1, 12)
 383    DEP_FIELD(REQ_SWRST_STATUS, SATA, 1, 10)
 384    DEP_FIELD(REQ_SWRST_STATUS, PCIE, 1, 9)
 385    DEP_FIELD(REQ_SWRST_STATUS, GPU, 1, 8)
 386    DEP_FIELD(REQ_SWRST_STATUS, PP1, 1, 7)
 387    DEP_FIELD(REQ_SWRST_STATUS, PP0, 1, 6)
 388    DEP_FIELD(REQ_SWRST_STATUS, APU, 1, 4)
 389    DEP_FIELD(REQ_SWRST_STATUS, ACPU3, 1, 3)
 390    DEP_FIELD(REQ_SWRST_STATUS, ACPU2, 1, 2)
 391    DEP_FIELD(REQ_SWRST_STATUS, ACPU1, 1, 1)
 392    DEP_FIELD(REQ_SWRST_STATUS, ACPU0, 1, 0)
 393DEP_REG32(REQ_SWRST_INT_MASK, 0x414)
 394    DEP_FIELD(REQ_SWRST_INT_MASK, PL, 1, 31)
 395    DEP_FIELD(REQ_SWRST_INT_MASK, FP, 1, 30)
 396    DEP_FIELD(REQ_SWRST_INT_MASK, LP, 1, 29)
 397    DEP_FIELD(REQ_SWRST_INT_MASK, PS_ONLY, 1, 28)
 398    DEP_FIELD(REQ_SWRST_INT_MASK, IOU, 1, 27)
 399    DEP_FIELD(REQ_SWRST_INT_MASK, USB1, 1, 25)
 400    DEP_FIELD(REQ_SWRST_INT_MASK, USB0, 1, 24)
 401    DEP_FIELD(REQ_SWRST_INT_MASK, GEM3, 1, 23)
 402    DEP_FIELD(REQ_SWRST_INT_MASK, GEM2, 1, 22)
 403    DEP_FIELD(REQ_SWRST_INT_MASK, GEM1, 1, 21)
 404    DEP_FIELD(REQ_SWRST_INT_MASK, GEM0, 1, 20)
 405    DEP_FIELD(REQ_SWRST_INT_MASK, LS_R5, 1, 18)
 406    DEP_FIELD(REQ_SWRST_INT_MASK, R5_1, 1, 17)
 407    DEP_FIELD(REQ_SWRST_INT_MASK, R5_0, 1, 16)
 408    DEP_FIELD(REQ_SWRST_INT_MASK, DISPLAY_PORT, 1, 12)
 409    DEP_FIELD(REQ_SWRST_INT_MASK, SATA, 1, 10)
 410    DEP_FIELD(REQ_SWRST_INT_MASK, PCIE, 1, 9)
 411    DEP_FIELD(REQ_SWRST_INT_MASK, GPU, 1, 8)
 412    DEP_FIELD(REQ_SWRST_INT_MASK, PP1, 1, 7)
 413    DEP_FIELD(REQ_SWRST_INT_MASK, PP0, 1, 6)
 414    DEP_FIELD(REQ_SWRST_INT_MASK, APU, 1, 4)
 415    DEP_FIELD(REQ_SWRST_INT_MASK, ACPU3, 1, 3)
 416    DEP_FIELD(REQ_SWRST_INT_MASK, ACPU2, 1, 2)
 417    DEP_FIELD(REQ_SWRST_INT_MASK, ACPU1, 1, 1)
 418    DEP_FIELD(REQ_SWRST_INT_MASK, ACPU0, 1, 0)
 419DEP_REG32(REQ_SWRST_INT_EN, 0x418)
 420    DEP_FIELD(REQ_SWRST_INT_EN, PL, 1, 31)
 421    DEP_FIELD(REQ_SWRST_INT_EN, FP, 1, 30)
 422    DEP_FIELD(REQ_SWRST_INT_EN, LP, 1, 29)
 423    DEP_FIELD(REQ_SWRST_INT_EN, PS_ONLY, 1, 28)
 424    DEP_FIELD(REQ_SWRST_INT_EN, IOU, 1, 27)
 425    DEP_FIELD(REQ_SWRST_INT_EN, USB1, 1, 25)
 426    DEP_FIELD(REQ_SWRST_INT_EN, USB0, 1, 24)
 427    DEP_FIELD(REQ_SWRST_INT_EN, GEM3, 1, 23)
 428    DEP_FIELD(REQ_SWRST_INT_EN, GEM2, 1, 22)
 429    DEP_FIELD(REQ_SWRST_INT_EN, GEM1, 1, 21)
 430    DEP_FIELD(REQ_SWRST_INT_EN, GEM0, 1, 20)
 431    DEP_FIELD(REQ_SWRST_INT_EN, LS_R5, 1, 18)
 432    DEP_FIELD(REQ_SWRST_INT_EN, R5_1, 1, 17)
 433    DEP_FIELD(REQ_SWRST_INT_EN, R5_0, 1, 16)
 434    DEP_FIELD(REQ_SWRST_INT_EN, DISPLAY_PORT, 1, 12)
 435    DEP_FIELD(REQ_SWRST_INT_EN, SATA, 1, 10)
 436    DEP_FIELD(REQ_SWRST_INT_EN, PCIE, 1, 9)
 437    DEP_FIELD(REQ_SWRST_INT_EN, GPU, 1, 8)
 438    DEP_FIELD(REQ_SWRST_INT_EN, PP1, 1, 7)
 439    DEP_FIELD(REQ_SWRST_INT_EN, PP0, 1, 6)
 440    DEP_FIELD(REQ_SWRST_INT_EN, APU, 1, 4)
 441    DEP_FIELD(REQ_SWRST_INT_EN, ACPU3, 1, 3)
 442    DEP_FIELD(REQ_SWRST_INT_EN, ACPU2, 1, 2)
 443    DEP_FIELD(REQ_SWRST_INT_EN, ACPU1, 1, 1)
 444    DEP_FIELD(REQ_SWRST_INT_EN, ACPU0, 1, 0)
 445DEP_REG32(REQ_SWRST_INT_DIS, 0x41c)
 446    DEP_FIELD(REQ_SWRST_INT_DIS, PL, 1, 31)
 447    DEP_FIELD(REQ_SWRST_INT_DIS, FP, 1, 30)
 448    DEP_FIELD(REQ_SWRST_INT_DIS, LP, 1, 29)
 449    DEP_FIELD(REQ_SWRST_INT_DIS, PS_ONLY, 1, 28)
 450    DEP_FIELD(REQ_SWRST_INT_DIS, IOU, 1, 27)
 451    DEP_FIELD(REQ_SWRST_INT_DIS, USB1, 1, 25)
 452    DEP_FIELD(REQ_SWRST_INT_DIS, USB0, 1, 24)
 453    DEP_FIELD(REQ_SWRST_INT_DIS, GEM3, 1, 23)
 454    DEP_FIELD(REQ_SWRST_INT_DIS, GEM2, 1, 22)
 455    DEP_FIELD(REQ_SWRST_INT_DIS, GEM1, 1, 21)
 456    DEP_FIELD(REQ_SWRST_INT_DIS, GEM0, 1, 20)
 457    DEP_FIELD(REQ_SWRST_INT_DIS, LS_R5, 1, 18)
 458    DEP_FIELD(REQ_SWRST_INT_DIS, R5_1, 1, 17)
 459    DEP_FIELD(REQ_SWRST_INT_DIS, R5_0, 1, 16)
 460    DEP_FIELD(REQ_SWRST_INT_DIS, DISPLAY_PORT, 1, 12)
 461    DEP_FIELD(REQ_SWRST_INT_DIS, SATA, 1, 10)
 462    DEP_FIELD(REQ_SWRST_INT_DIS, PCIE, 1, 9)
 463    DEP_FIELD(REQ_SWRST_INT_DIS, GPU, 1, 8)
 464    DEP_FIELD(REQ_SWRST_INT_DIS, PP1, 1, 7)
 465    DEP_FIELD(REQ_SWRST_INT_DIS, PP0, 1, 6)
 466    DEP_FIELD(REQ_SWRST_INT_DIS, APU, 1, 4)
 467    DEP_FIELD(REQ_SWRST_INT_DIS, ACPU3, 1, 3)
 468    DEP_FIELD(REQ_SWRST_INT_DIS, ACPU2, 1, 2)
 469    DEP_FIELD(REQ_SWRST_INT_DIS, ACPU1, 1, 1)
 470    DEP_FIELD(REQ_SWRST_INT_DIS, ACPU0, 1, 0)
 471DEP_REG32(REQ_SWRST_TRIG, 0x420)
 472    DEP_FIELD(REQ_SWRST_TRIG, PL, 1, 31)
 473    DEP_FIELD(REQ_SWRST_TRIG, FP, 1, 30)
 474    DEP_FIELD(REQ_SWRST_TRIG, LP, 1, 29)
 475    DEP_FIELD(REQ_SWRST_TRIG, PS_ONLY, 1, 28)
 476    DEP_FIELD(REQ_SWRST_TRIG, IOU, 1, 27)
 477    DEP_FIELD(REQ_SWRST_TRIG, USB1, 1, 25)
 478    DEP_FIELD(REQ_SWRST_TRIG, USB0, 1, 24)
 479    DEP_FIELD(REQ_SWRST_TRIG, GEM3, 1, 23)
 480    DEP_FIELD(REQ_SWRST_TRIG, GEM2, 1, 22)
 481    DEP_FIELD(REQ_SWRST_TRIG, GEM1, 1, 21)
 482    DEP_FIELD(REQ_SWRST_TRIG, GEM0, 1, 20)
 483    DEP_FIELD(REQ_SWRST_TRIG, LS_R5, 1, 18)
 484    DEP_FIELD(REQ_SWRST_TRIG, R5_1, 1, 17)
 485    DEP_FIELD(REQ_SWRST_TRIG, R5_0, 1, 16)
 486    DEP_FIELD(REQ_SWRST_TRIG, DISPLAY_PORT, 1, 12)
 487    DEP_FIELD(REQ_SWRST_TRIG, SATA, 1, 10)
 488    DEP_FIELD(REQ_SWRST_TRIG, PCIE, 1, 9)
 489    DEP_FIELD(REQ_SWRST_TRIG, GPU, 1, 8)
 490    DEP_FIELD(REQ_SWRST_TRIG, PP1, 1, 7)
 491    DEP_FIELD(REQ_SWRST_TRIG, PP0, 1, 6)
 492    DEP_FIELD(REQ_SWRST_TRIG, APU, 1, 4)
 493    DEP_FIELD(REQ_SWRST_TRIG, ACPU3, 1, 3)
 494    DEP_FIELD(REQ_SWRST_TRIG, ACPU2, 1, 2)
 495    DEP_FIELD(REQ_SWRST_TRIG, ACPU1, 1, 1)
 496    DEP_FIELD(REQ_SWRST_TRIG, ACPU0, 1, 0)
 497DEP_REG32(REQ_AUX_STATUS, 0x510)
 498    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_10, 1, 17)
 499    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_9, 1, 16)
 500    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_8, 1, 13)
 501    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_7, 1, 12)
 502    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_6, 1, 10)
 503    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_5, 1, 7)
 504    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_4, 1, 6)
 505    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_3, 1, 3)
 506    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_2, 1, 2)
 507    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_1, 1, 1)
 508    DEP_FIELD(REQ_AUX_STATUS, SERV_REQ_0, 1, 0)
 509DEP_REG32(REQ_AUX_INT_MASK, 0x514)
 510    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_10, 1, 17)
 511    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_9, 1, 16)
 512    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_8, 1, 13)
 513    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_7, 1, 12)
 514    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_6, 1, 10)
 515    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_5, 1, 7)
 516    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_4, 1, 6)
 517    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_3, 1, 3)
 518    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_2, 1, 2)
 519    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_1, 1, 1)
 520    DEP_FIELD(REQ_AUX_MASK, SERV_REQ_0, 1, 0)
 521DEP_REG32(REQ_AUX_INT_EN, 0x518)
 522    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_10, 1, 17)
 523    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_9, 1, 16)
 524    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_8, 1, 13)
 525    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_7, 1, 12)
 526    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_6, 1, 10)
 527    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_5, 1, 7)
 528    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_4, 1, 6)
 529    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_3, 1, 3)
 530    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_2, 1, 2)
 531    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_1, 1, 1)
 532    DEP_FIELD(REQ_AUX_INT_EN, SERV_REQ_0, 1, 0)
 533DEP_REG32(REQ_AUX_INT_DIS, 0x51c)
 534    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_10, 1, 17)
 535    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_9, 1, 16)
 536    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_8, 1, 13)
 537    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_7, 1, 12)
 538    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_6, 1, 10)
 539    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_5, 1, 7)
 540    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_4, 1, 6)
 541    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_3, 1, 3)
 542    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_2, 1, 2)
 543    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_1, 1, 1)
 544    DEP_FIELD(REQ_AUX_INT_DIS, SERV_REQ_0, 1, 0)
 545DEP_REG32(REQ_AUX_TRIG, 0x520)
 546    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_10, 1, 17)
 547    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_9, 1, 16)
 548    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_8, 1, 13)
 549    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_7, 1, 12)
 550    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_6, 1, 10)
 551    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_5, 1, 7)
 552    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_4, 1, 6)
 553    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_3, 1, 3)
 554    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_2, 1, 2)
 555    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_1, 1, 1)
 556    DEP_FIELD(REQ_AUX_TRIG, SERV_REQ_0, 1, 0)
 557DEP_REG32(LOGCLR_STATUS, 0x524)
 558    DEP_FIELD(LOGCLR_STATUS, FP, 1, 17)
 559    DEP_FIELD(LOGCLR_STATUS, LP, 1, 16)
 560    DEP_FIELD(LOGCLR_STATUS, USB1, 1, 13)
 561    DEP_FIELD(LOGCLR_STATUS, USB0, 1, 12)
 562    DEP_FIELD(LOGCLR_STATUS, RPU, 1, 10)
 563    DEP_FIELD(LOGCLR_STATUS, PP1, 1, 7)
 564    DEP_FIELD(LOGCLR_STATUS, PP0, 1, 6)
 565    DEP_FIELD(LOGCLR_STATUS, ACPU3, 1, 3)
 566    DEP_FIELD(LOGCLR_STATUS, ACPU2, 1, 2)
 567    DEP_FIELD(LOGCLR_STATUS, ACPU1, 1, 1)
 568    DEP_FIELD(LOGCLR_STATUS, ACPU0, 1, 0)
 569DEP_REG32(CSU_BR_ERROR, 0x528)
 570    DEP_FIELD(CSU_BR_ERROR, BR_ERROR, 1, 31)
 571    DEP_FIELD(CSU_BR_ERROR, ERR_TYPE, 16, 0)
 572DEP_REG32(MB_FAULT_STATUS, 0x52c)
 573    DEP_FIELD(MB_FAULT_STATUS, R_FFAIL, 8, 24)
 574    DEP_FIELD(MB_FAULT_STATUS, R_SLEEP_RST, 1, 19)
 575    DEP_FIELD(MB_FAULT_STATUS, R_LSFAIL, 3, 16)
 576    DEP_FIELD(MB_FAULT_STATUS, N_FFAIL, 8, 8)
 577    DEP_FIELD(MB_FAULT_STATUS, N_SLEEP_RST, 1, 3)
 578    DEP_FIELD(MB_FAULT_STATUS, N_LSFAIL, 3, 0)
 579DEP_REG32(ERROR_STATUS_1, 0x530)
 580    DEP_FIELD(ERROR_STATUS_1, AUX3, 1, 31)
 581    DEP_FIELD(ERROR_STATUS_1, AUX2, 1, 30)
 582    DEP_FIELD(ERROR_STATUS_1, AUX1, 1, 29)
 583    DEP_FIELD(ERROR_STATUS_1, AUX0, 1, 28)
 584    DEP_FIELD(ERROR_STATUS_1, DFT, 1, 27)
 585    DEP_FIELD(ERROR_STATUS_1, CLK_MON, 1, 26)
 586    DEP_FIELD(ERROR_STATUS_1, XMPU, 2, 24)
 587    DEP_FIELD(ERROR_STATUS_1, PWR_SUPPLY, 8, 16)
 588    DEP_FIELD(ERROR_STATUS_1, FPD_SWDT, 1, 13)
 589    DEP_FIELD(ERROR_STATUS_1, LPD_SWDT, 1, 12)
 590    DEP_FIELD(ERROR_STATUS_1, RPU_CCF, 1, 9)
 591    DEP_FIELD(ERROR_STATUS_1, RPU_LS, 2, 6)
 592    DEP_FIELD(ERROR_STATUS_1, FPD_TEMP, 1, 5)
 593    DEP_FIELD(ERROR_STATUS_1, LPD_TEMP, 1, 4)
 594    DEP_FIELD(ERROR_STATUS_1, RPU1, 1, 3)
 595    DEP_FIELD(ERROR_STATUS_1, RPU0, 1, 2)
 596    DEP_FIELD(ERROR_STATUS_1, OCM_ECC, 1, 1)
 597    DEP_FIELD(ERROR_STATUS_1, DDR_ECC, 1, 0)
 598DEP_REG32(ERROR_INT_MASK_1, 0x534)
 599    DEP_FIELD(ERROR_INT_MASK_1, AUX3, 1, 31)
 600    DEP_FIELD(ERROR_INT_MASK_1, AUX2, 1, 30)
 601    DEP_FIELD(ERROR_INT_MASK_1, AUX1, 1, 29)
 602    DEP_FIELD(ERROR_INT_MASK_1, AUX0, 1, 28)
 603    DEP_FIELD(ERROR_INT_MASK_1, DFT, 1, 27)
 604    DEP_FIELD(ERROR_INT_MASK_1, CLK_MON, 1, 26)
 605    DEP_FIELD(ERROR_INT_MASK_1, XMPU, 2, 24)
 606    DEP_FIELD(ERROR_INT_MASK_1, PWR_SUPPLY, 8, 16)
 607    DEP_FIELD(ERROR_INT_MASK_1, FPD_SWDT, 1, 13)
 608    DEP_FIELD(ERROR_INT_MASK_1, LPD_SWDT, 1, 12)
 609    DEP_FIELD(ERROR_INT_MASK_1, RPU_CCF, 1, 9)
 610    DEP_FIELD(ERROR_INT_MASK_1, RPU_LS, 2, 6)
 611    DEP_FIELD(ERROR_INT_MASK_1, FPD_TEMP, 1, 5)
 612    DEP_FIELD(ERROR_INT_MASK_1, LPD_TEMP, 1, 4)
 613    DEP_FIELD(ERROR_INT_MASK_1, RPU1, 1, 3)
 614    DEP_FIELD(ERROR_INT_MASK_1, RPU0, 1, 2)
 615    DEP_FIELD(ERROR_INT_MASK_1, OCM_ECC, 1, 1)
 616    DEP_FIELD(ERROR_INT_MASK_1, DDR_ECC, 1, 0)
 617DEP_REG32(ERROR_INT_EN_1, 0x538)
 618    DEP_FIELD(ERROR_INT_EN_1, AUX3, 1, 31)
 619    DEP_FIELD(ERROR_INT_EN_1, AUX2, 1, 30)
 620    DEP_FIELD(ERROR_INT_EN_1, AUX1, 1, 29)
 621    DEP_FIELD(ERROR_INT_EN_1, AUX0, 1, 28)
 622    DEP_FIELD(ERROR_INT_EN_1, DFT, 1, 27)
 623    DEP_FIELD(ERROR_INT_EN_1, CLK_MON, 1, 26)
 624    DEP_FIELD(ERROR_INT_EN_1, XMPU, 2, 24)
 625    DEP_FIELD(ERROR_INT_EN_1, PWR_SUPPLY, 8, 16)
 626    DEP_FIELD(ERROR_INT_EN_1, FPD_SWDT, 1, 13)
 627    DEP_FIELD(ERROR_INT_EN_1, LPD_SWDT, 1, 12)
 628    DEP_FIELD(ERROR_INT_EN_1, RPU_CCF, 1, 9)
 629    DEP_FIELD(ERROR_INT_EN_1, RPU_LS, 2, 6)
 630    DEP_FIELD(ERROR_INT_EN_1, FPD_TEMP, 1, 5)
 631    DEP_FIELD(ERROR_INT_EN_1, LPD_TEMP, 1, 4)
 632    DEP_FIELD(ERROR_INT_EN_1, RPU1, 1, 3)
 633    DEP_FIELD(ERROR_INT_EN_1, RPU0, 1, 2)
 634    DEP_FIELD(ERROR_INT_EN_1, OCM_ECC, 1, 1)
 635    DEP_FIELD(ERROR_INT_EN_1, DDR_ECC, 1, 0)
 636DEP_REG32(ERROR_INT_DIS_1, 0x53c)
 637    DEP_FIELD(ERROR_INT_DIS_1, AUX3, 1, 31)
 638    DEP_FIELD(ERROR_INT_DIS_1, AUX2, 1, 30)
 639    DEP_FIELD(ERROR_INT_DIS_1, AUX1, 1, 29)
 640    DEP_FIELD(ERROR_INT_DIS_1, AUX0, 1, 28)
 641    DEP_FIELD(ERROR_INT_DIS_1, DFT, 1, 27)
 642    DEP_FIELD(ERROR_INT_DIS_1, CLK_MON, 1, 26)
 643    DEP_FIELD(ERROR_INT_DIS_1, XMPU, 2, 24)
 644    DEP_FIELD(ERROR_INT_DIS_1, PWR_SUPPLY, 8, 16)
 645    DEP_FIELD(ERROR_INT_DIS_1, FPD_SWDT, 1, 13)
 646    DEP_FIELD(ERROR_INT_DIS_1, LPD_SWDT, 1, 12)
 647    DEP_FIELD(ERROR_INT_DIS_1, RPU_CCF, 1, 9)
 648    DEP_FIELD(ERROR_INT_DIS_1, RPU_LS, 2, 6)
 649    DEP_FIELD(ERROR_INT_DIS_1, FPD_TEMP, 1, 5)
 650    DEP_FIELD(ERROR_INT_DIS_1, LPD_TEMP, 1, 4)
 651    DEP_FIELD(ERROR_INT_DIS_1, RPU1, 1, 3)
 652    DEP_FIELD(ERROR_INT_DIS_1, RPU0, 1, 2)
 653    DEP_FIELD(ERROR_INT_DIS_1, OCM_ECC, 1, 1)
 654    DEP_FIELD(ERROR_INT_DIS_1, DDR_ECC, 1, 0)
 655DEP_REG32(ERROR_STATUS_2, 0x540)
 656    DEP_FIELD(ERROR_STATUS_2, CSU_ROM, 1, 26)
 657    DEP_FIELD(ERROR_STATUS_2, PMU_PB, 1, 25)
 658    DEP_FIELD(ERROR_STATUS_2, PMU_SERVICE, 1, 24)
 659    DEP_FIELD(ERROR_STATUS_2, PMU_FW, 4, 18)
 660    DEP_FIELD(ERROR_STATUS_2, PMU_UC, 1, 17)
 661    DEP_FIELD(ERROR_STATUS_2, CSU, 1, 16)
 662    DEP_FIELD(ERROR_STATUS_2, PLL_LOCK, 5, 8)
 663    DEP_FIELD(ERROR_STATUS_2, PL, 4, 2)
 664    DEP_FIELD(ERROR_STATUS_2, TO, 2, 0)
 665DEP_REG32(ERROR_INT_MASK_2, 0x544)
 666    DEP_FIELD(ERROR_INT_MASK_2, CSU_ROM, 1, 26)
 667    DEP_FIELD(ERROR_INT_MASK_2, PMU_PB, 1, 25)
 668    DEP_FIELD(ERROR_INT_MASK_2, PMU_SERVICE, 1, 24)
 669    DEP_FIELD(ERROR_INT_MASK_2, PMU_FW, 4, 18)
 670    DEP_FIELD(ERROR_INT_MASK_2, PMU_UC, 1, 17)
 671    DEP_FIELD(ERROR_INT_MASK_2, CSU, 1, 16)
 672    DEP_FIELD(ERROR_INT_MASK_2, PLL_LOCK, 5, 8)
 673    DEP_FIELD(ERROR_INT_MASK_2, PL, 4, 2)
 674    DEP_FIELD(ERROR_INT_MASK_2, TO, 2, 0)
 675DEP_REG32(ERROR_INT_EN_2, 0x548)
 676    DEP_FIELD(ERROR_INT_EN_2, CSU_ROM, 1, 26)
 677    DEP_FIELD(ERROR_INT_EN_2, PMU_PB, 1, 25)
 678    DEP_FIELD(ERROR_INT_EN_2, PMU_SERVICE, 1, 24)
 679    DEP_FIELD(ERROR_INT_EN_2, PMU_FW, 4, 18)
 680    DEP_FIELD(ERROR_INT_EN_2, PMU_UC, 1, 17)
 681    DEP_FIELD(ERROR_INT_EN_2, CSU, 1, 16)
 682    DEP_FIELD(ERROR_INT_EN_2, PLL_LOCK, 5, 8)
 683    DEP_FIELD(ERROR_INT_EN_2, PL, 4, 2)
 684    DEP_FIELD(ERROR_INT_EN_2, TO, 2, 0)
 685DEP_REG32(ERROR_INT_DIS_2, 0x54c)
 686    DEP_FIELD(ERROR_INT_DIS_2, CSU_ROM, 1, 26)
 687    DEP_FIELD(ERROR_INT_DIS_2, PMU_PB, 1, 25)
 688    DEP_FIELD(ERROR_INT_DIS_2, PMU_SERVICE, 1, 24)
 689    DEP_FIELD(ERROR_INT_DIS_2, PMU_FW, 4, 18)
 690    DEP_FIELD(ERROR_INT_DIS_2, PMU_UC, 1, 17)
 691    DEP_FIELD(ERROR_INT_DIS_2, CSU, 1, 16)
 692    DEP_FIELD(ERROR_INT_DIS_2, PLL_LOCK, 5, 8)
 693    DEP_FIELD(ERROR_INT_DIS_2, PL, 4, 2)
 694    DEP_FIELD(ERROR_INT_DIS_2, TO, 2, 0)
 695DEP_REG32(ERROR_POR_MASK_1, 0x550)
 696    DEP_FIELD(ERROR_POR_MASK_1, AUX3, 1, 31)
 697    DEP_FIELD(ERROR_POR_MASK_1, AUX2, 1, 30)
 698    DEP_FIELD(ERROR_POR_MASK_1, AUX1, 1, 29)
 699    DEP_FIELD(ERROR_POR_MASK_1, AUX0, 1, 28)
 700    DEP_FIELD(ERROR_POR_MASK_1, DFT, 1, 27)
 701    DEP_FIELD(ERROR_POR_MASK_1, CLK_MON, 1, 26)
 702    DEP_FIELD(ERROR_POR_MASK_1, XMPU, 2, 24)
 703    DEP_FIELD(ERROR_POR_MASK_1, PWR_SUPPLY, 8, 16)
 704    DEP_FIELD(ERROR_POR_MASK_1, FPD_SWDT, 1, 13)
 705    DEP_FIELD(ERROR_POR_MASK_1, LPD_SWDT, 1, 12)
 706    DEP_FIELD(ERROR_POR_MASK_1, RPU_CCF, 1, 9)
 707    DEP_FIELD(ERROR_POR_MASK_1, RPU_LS, 2, 6)
 708    DEP_FIELD(ERROR_POR_MASK_1, FPD_TEMP, 1, 5)
 709    DEP_FIELD(ERROR_POR_MASK_1, LPD_TEMP, 1, 4)
 710    DEP_FIELD(ERROR_POR_MASK_1, RPU1, 1, 3)
 711    DEP_FIELD(ERROR_POR_MASK_1, RPU0, 1, 2)
 712    DEP_FIELD(ERROR_POR_MASK_1, OCM_ECC, 1, 1)
 713    DEP_FIELD(ERROR_POR_MASK_1, DDR_ECC, 1, 0)
 714DEP_REG32(ERROR_POR_EN_1, 0x554)
 715    DEP_FIELD(ERROR_POR_EN_1, AUX3, 1, 31)
 716    DEP_FIELD(ERROR_POR_EN_1, AUX2, 1, 30)
 717    DEP_FIELD(ERROR_POR_EN_1, AUX1, 1, 29)
 718    DEP_FIELD(ERROR_POR_EN_1, AUX0, 1, 28)
 719    DEP_FIELD(ERROR_POR_EN_1, DFT, 1, 27)
 720    DEP_FIELD(ERROR_POR_EN_1, CLK_MON, 1, 26)
 721    DEP_FIELD(ERROR_POR_EN_1, XMPU, 2, 24)
 722    DEP_FIELD(ERROR_POR_EN_1, PWR_SUPPLY, 8, 16)
 723    DEP_FIELD(ERROR_POR_EN_1, FPD_SWDT, 1, 13)
 724    DEP_FIELD(ERROR_POR_EN_1, LPD_SWDT, 1, 12)
 725    DEP_FIELD(ERROR_POR_EN_1, RPU_CCF, 1, 9)
 726    DEP_FIELD(ERROR_POR_EN_1, RPU_LS, 2, 6)
 727    DEP_FIELD(ERROR_POR_EN_1, FPD_TEMP, 1, 5)
 728    DEP_FIELD(ERROR_POR_EN_1, LPD_TEMP, 1, 4)
 729    DEP_FIELD(ERROR_POR_EN_1, RPU1, 1, 3)
 730    DEP_FIELD(ERROR_POR_EN_1, RPU0, 1, 2)
 731    DEP_FIELD(ERROR_POR_EN_1, OCM_ECC, 1, 1)
 732    DEP_FIELD(ERROR_POR_EN_1, DDR_ECC, 1, 0)
 733DEP_REG32(ERROR_POR_DIS_1, 0x558)
 734    DEP_FIELD(ERROR_POR_DIS_1, AUX3, 1, 31)
 735    DEP_FIELD(ERROR_POR_DIS_1, AUX2, 1, 30)
 736    DEP_FIELD(ERROR_POR_DIS_1, AUX1, 1, 29)
 737    DEP_FIELD(ERROR_POR_DIS_1, AUX0, 1, 28)
 738    DEP_FIELD(ERROR_POR_DIS_1, DFT, 1, 27)
 739    DEP_FIELD(ERROR_POR_DIS_1, CLK_MON, 1, 26)
 740    DEP_FIELD(ERROR_POR_DIS_1, XMPU, 2, 24)
 741    DEP_FIELD(ERROR_POR_DIS_1, PWR_SUPPLY, 8, 16)
 742    DEP_FIELD(ERROR_POR_DIS_1, FPD_SWDT, 1, 13)
 743    DEP_FIELD(ERROR_POR_DIS_1, LPD_SWDT, 1, 12)
 744    DEP_FIELD(ERROR_POR_DIS_1, RPU_CCF, 1, 9)
 745    DEP_FIELD(ERROR_POR_DIS_1, RPU_LS, 2, 6)
 746    DEP_FIELD(ERROR_POR_DIS_1, FPD_TEMP, 1, 5)
 747    DEP_FIELD(ERROR_POR_DIS_1, LPD_TEMP, 1, 4)
 748    DEP_FIELD(ERROR_POR_DIS_1, RPU1, 1, 3)
 749    DEP_FIELD(ERROR_POR_DIS_1, RPU0, 1, 2)
 750    DEP_FIELD(ERROR_POR_DIS_1, OCM_ECC, 1, 1)
 751    DEP_FIELD(ERROR_POR_DIS_1, DDR_ECC, 1, 0)
 752DEP_REG32(ERROR_POR_MASK_2, 0x55c)
 753    DEP_FIELD(ERROR_POR_MASK_2, CSU_ROM, 1, 26)
 754    DEP_FIELD(ERROR_POR_MASK_2, PMU_PB, 1, 25)
 755    DEP_FIELD(ERROR_POR_MASK_2, PMU_SERVICE, 1, 24)
 756    DEP_FIELD(ERROR_POR_MASK_2, PMU_FW, 4, 18)
 757    DEP_FIELD(ERROR_POR_MASK_2, PMU_UC, 1, 17)
 758    DEP_FIELD(ERROR_POR_MASK_2, CSU, 1, 16)
 759    DEP_FIELD(ERROR_POR_MASK_2, PLL_LOCK, 5, 8)
 760    DEP_FIELD(ERROR_POR_MASK_2, PL, 4, 2)
 761    DEP_FIELD(ERROR_POR_MASK_2, TO, 2, 0)
 762DEP_REG32(ERROR_POR_EN_2, 0x560)
 763    DEP_FIELD(ERROR_POR_EN_2, CSU_ROM, 1, 26)
 764    DEP_FIELD(ERROR_POR_EN_2, PMU_PB, 1, 25)
 765    DEP_FIELD(ERROR_POR_EN_2, PMU_SERVICE, 1, 24)
 766    DEP_FIELD(ERROR_POR_EN_2, PMU_FW, 4, 18)
 767    DEP_FIELD(ERROR_POR_EN_2, PMU_UC, 1, 17)
 768    DEP_FIELD(ERROR_POR_EN_2, CSU, 1, 16)
 769    DEP_FIELD(ERROR_POR_EN_2, PLL_LOCK, 5, 8)
 770    DEP_FIELD(ERROR_POR_EN_2, PL, 4, 2)
 771    DEP_FIELD(ERROR_POR_EN_2, TO, 2, 0)
 772DEP_REG32(ERROR_POR_DIS_2, 0x564)
 773    DEP_FIELD(ERROR_POR_DIS_2, CSU_ROM, 1, 26)
 774    DEP_FIELD(ERROR_POR_DIS_2, PMU_PB, 1, 25)
 775    DEP_FIELD(ERROR_POR_DIS_2, PMU_SERVICE, 1, 24)
 776    DEP_FIELD(ERROR_POR_DIS_2, PMU_FW, 4, 18)
 777    DEP_FIELD(ERROR_POR_DIS_2, PMU_UC, 1, 17)
 778    DEP_FIELD(ERROR_POR_DIS_2, CSU, 1, 16)
 779    DEP_FIELD(ERROR_POR_DIS_2, PLL_LOCK, 5, 8)
 780    DEP_FIELD(ERROR_POR_DIS_2, PL, 4, 2)
 781    DEP_FIELD(ERROR_POR_DIS_2, TO, 2, 0)
 782DEP_REG32(ERROR_SRST_MASK_1, 0x568)
 783    DEP_FIELD(ERROR_SRST_MASK_1, AUX3, 1, 31)
 784    DEP_FIELD(ERROR_SRST_MASK_1, AUX2, 1, 30)
 785    DEP_FIELD(ERROR_SRST_MASK_1, AUX1, 1, 29)
 786    DEP_FIELD(ERROR_SRST_MASK_1, AUX0, 1, 28)
 787    DEP_FIELD(ERROR_SRST_MASK_1, DFT, 1, 27)
 788    DEP_FIELD(ERROR_SRST_MASK_1, CLK_MON, 1, 26)
 789    DEP_FIELD(ERROR_SRST_MASK_1, XMPU, 2, 24)
 790    DEP_FIELD(ERROR_SRST_MASK_1, PWR_SUPPLY, 8, 16)
 791    DEP_FIELD(ERROR_SRST_MASK_1, FPD_SWDT, 1, 13)
 792    DEP_FIELD(ERROR_SRST_MASK_1, LPD_SWDT, 1, 12)
 793    DEP_FIELD(ERROR_SRST_MASK_1, RPU_CCF, 1, 9)
 794    DEP_FIELD(ERROR_SRST_MASK_1, RPU_LS, 2, 6)
 795    DEP_FIELD(ERROR_SRST_MASK_1, FPD_TEMP, 1, 5)
 796    DEP_FIELD(ERROR_SRST_MASK_1, LPD_TEMP, 1, 4)
 797    DEP_FIELD(ERROR_SRST_MASK_1, RPU1, 1, 3)
 798    DEP_FIELD(ERROR_SRST_MASK_1, RPU0, 1, 2)
 799    DEP_FIELD(ERROR_SRST_MASK_1, OCM_ECC, 1, 1)
 800    DEP_FIELD(ERROR_SRST_MASK_1, DDR_ECC, 1, 0)
 801DEP_REG32(ERROR_SRST_EN_1, 0x56c)
 802    DEP_FIELD(ERROR_SRST_EN_1, AUX3, 1, 31)
 803    DEP_FIELD(ERROR_SRST_EN_1, AUX2, 1, 30)
 804    DEP_FIELD(ERROR_SRST_EN_1, AUX1, 1, 29)
 805    DEP_FIELD(ERROR_SRST_EN_1, AUX0, 1, 28)
 806    DEP_FIELD(ERROR_SRST_EN_1, DFT, 1, 27)
 807    DEP_FIELD(ERROR_SRST_EN_1, CLK_MON, 1, 26)
 808    DEP_FIELD(ERROR_SRST_EN_1, XMPU, 2, 24)
 809    DEP_FIELD(ERROR_SRST_EN_1, PWR_SUPPLY, 8, 16)
 810    DEP_FIELD(ERROR_SRST_EN_1, FPD_SWDT, 1, 13)
 811    DEP_FIELD(ERROR_SRST_EN_1, LPD_SWDT, 1, 12)
 812    DEP_FIELD(ERROR_SRST_EN_1, RPU_CCF, 1, 9)
 813    DEP_FIELD(ERROR_SRST_EN_1, RPU_LS, 2, 6)
 814    DEP_FIELD(ERROR_SRST_EN_1, FPD_TEMP, 1, 5)
 815    DEP_FIELD(ERROR_SRST_EN_1, LPD_TEMP, 1, 4)
 816    DEP_FIELD(ERROR_SRST_EN_1, RPU1, 1, 3)
 817    DEP_FIELD(ERROR_SRST_EN_1, RPU0, 1, 2)
 818    DEP_FIELD(ERROR_SRST_EN_1, OCM_ECC, 1, 1)
 819    DEP_FIELD(ERROR_SRST_EN_1, DDR_ECC, 1, 0)
 820DEP_REG32(ERROR_SRST_DIS_1, 0x570)
 821    DEP_FIELD(ERROR_SRST_DIS_1, AUX3, 1, 31)
 822    DEP_FIELD(ERROR_SRST_DIS_1, AUX2, 1, 30)
 823    DEP_FIELD(ERROR_SRST_DIS_1, AUX1, 1, 29)
 824    DEP_FIELD(ERROR_SRST_DIS_1, AUX0, 1, 28)
 825    DEP_FIELD(ERROR_SRST_DIS_1, DFT, 1, 27)
 826    DEP_FIELD(ERROR_SRST_DIS_1, CLK_MON, 1, 26)
 827    DEP_FIELD(ERROR_SRST_DIS_1, XMPU, 2, 24)
 828    DEP_FIELD(ERROR_SRST_DIS_1, PWR_SUPPLY, 8, 16)
 829    DEP_FIELD(ERROR_SRST_DIS_1, FPD_SWDT, 1, 13)
 830    DEP_FIELD(ERROR_SRST_DIS_1, LPD_SWDT, 1, 12)
 831    DEP_FIELD(ERROR_SRST_DIS_1, RPU_CCF, 1, 9)
 832    DEP_FIELD(ERROR_SRST_DIS_1, RPU_LS, 2, 6)
 833    DEP_FIELD(ERROR_SRST_DIS_1, FPD_TEMP, 1, 5)
 834    DEP_FIELD(ERROR_SRST_DIS_1, LPD_TEMP, 1, 4)
 835    DEP_FIELD(ERROR_SRST_DIS_1, RPU1, 1, 3)
 836    DEP_FIELD(ERROR_SRST_DIS_1, RPU0, 1, 2)
 837    DEP_FIELD(ERROR_SRST_DIS_1, OCM_ECC, 1, 1)
 838    DEP_FIELD(ERROR_SRST_DIS_1, DDR_ECC, 1, 0)
 839DEP_REG32(ERROR_SRST_MASK_2, 0x574)
 840    DEP_FIELD(ERROR_SRST_MASK_2, CSU_ROM, 1, 26)
 841    DEP_FIELD(ERROR_SRST_MASK_2, PMU_PB, 1, 25)
 842    DEP_FIELD(ERROR_SRST_MASK_2, PMU_SERVICE, 1, 24)
 843    DEP_FIELD(ERROR_SRST_MASK_2, PMU_FW, 4, 18)
 844    DEP_FIELD(ERROR_SRST_MASK_2, PMU_UC, 1, 17)
 845    DEP_FIELD(ERROR_SRST_MASK_2, CSU, 1, 16)
 846    DEP_FIELD(ERROR_SRST_MASK_2, PLL_LOCK, 5, 8)
 847    DEP_FIELD(ERROR_SRST_MASK_2, PL, 4, 2)
 848    DEP_FIELD(ERROR_SRST_MASK_2, TO, 2, 0)
 849DEP_REG32(ERROR_SRST_EN_2, 0x578)
 850    DEP_FIELD(ERROR_SRST_EN_2, CSU_ROM, 1, 26)
 851    DEP_FIELD(ERROR_SRST_EN_2, PMU_PB, 1, 25)
 852    DEP_FIELD(ERROR_SRST_EN_2, PMU_SERVICE, 1, 24)
 853    DEP_FIELD(ERROR_SRST_EN_2, PMU_FW, 4, 18)
 854    DEP_FIELD(ERROR_SRST_EN_2, PMU_UC, 1, 17)
 855    DEP_FIELD(ERROR_SRST_EN_2, CSU, 1, 16)
 856    DEP_FIELD(ERROR_SRST_EN_2, PLL_LOCK, 5, 8)
 857    DEP_FIELD(ERROR_SRST_EN_2, PL, 4, 2)
 858    DEP_FIELD(ERROR_SRST_EN_2, TO, 2, 0)
 859DEP_REG32(ERROR_SRST_DIS_2, 0x57c)
 860    DEP_FIELD(ERROR_SRST_DIS_2, CSU_ROM, 1, 26)
 861    DEP_FIELD(ERROR_SRST_DIS_2, PMU_PB, 1, 25)
 862    DEP_FIELD(ERROR_SRST_DIS_2, PMU_SERVICE, 1, 24)
 863    DEP_FIELD(ERROR_SRST_DIS_2, PMU_FW, 4, 18)
 864    DEP_FIELD(ERROR_SRST_DIS_2, PMU_UC, 1, 17)
 865    DEP_FIELD(ERROR_SRST_DIS_2, CSU, 1, 16)
 866    DEP_FIELD(ERROR_SRST_DIS_2, PLL_LOCK, 5, 8)
 867    DEP_FIELD(ERROR_SRST_DIS_2, PL, 4, 2)
 868    DEP_FIELD(ERROR_SRST_DIS_2, TO, 2, 0)
 869DEP_REG32(ERROR_SIG_MASK_1, 0x580)
 870    DEP_FIELD(ERROR_SIG_MASK_1, AUX3, 1, 31)
 871    DEP_FIELD(ERROR_SIG_MASK_1, AUX2, 1, 30)
 872    DEP_FIELD(ERROR_SIG_MASK_1, AUX1, 1, 29)
 873    DEP_FIELD(ERROR_SIG_MASK_1, AUX0, 1, 28)
 874    DEP_FIELD(ERROR_SIG_MASK_1, DFT, 1, 27)
 875    DEP_FIELD(ERROR_SIG_MASK_1, CLK_MON, 1, 26)
 876    DEP_FIELD(ERROR_SIG_MASK_1, XMPU, 2, 24)
 877    DEP_FIELD(ERROR_SIG_MASK_1, PWR_SUPPLY, 8, 16)
 878    DEP_FIELD(ERROR_SIG_MASK_1, FPD_SWDT, 1, 13)
 879    DEP_FIELD(ERROR_SIG_MASK_1, LPD_SWDT, 1, 12)
 880    DEP_FIELD(ERROR_SIG_MASK_1, RPU_CCF, 1, 9)
 881    DEP_FIELD(ERROR_SIG_MASK_1, RPU_LS, 2, 6)
 882    DEP_FIELD(ERROR_SIG_MASK_1, FPD_TEMP, 1, 5)
 883    DEP_FIELD(ERROR_SIG_MASK_1, LPD_TEMP, 1, 4)
 884    DEP_FIELD(ERROR_SIG_MASK_1, RPU1, 1, 3)
 885    DEP_FIELD(ERROR_SIG_MASK_1, RPU0, 1, 2)
 886    DEP_FIELD(ERROR_SIG_MASK_1, OCM_ECC, 1, 1)
 887    DEP_FIELD(ERROR_SIG_MASK_1, DDR_ECC, 1, 0)
 888DEP_REG32(ERROR_SIG_EN_1, 0x584)
 889    DEP_FIELD(ERROR_SIG_EN_1, AUX3, 1, 31)
 890    DEP_FIELD(ERROR_SIG_EN_1, AUX2, 1, 30)
 891    DEP_FIELD(ERROR_SIG_EN_1, AUX1, 1, 29)
 892    DEP_FIELD(ERROR_SIG_EN_1, AUX0, 1, 28)
 893    DEP_FIELD(ERROR_SIG_EN_1, DFT, 1, 27)
 894    DEP_FIELD(ERROR_SIG_EN_1, CLK_MON, 1, 26)
 895    DEP_FIELD(ERROR_SIG_EN_1, XMPU, 2, 24)
 896    DEP_FIELD(ERROR_SIG_EN_1, PWR_SUPPLY, 8, 16)
 897    DEP_FIELD(ERROR_SIG_EN_1, FPD_SWDT, 1, 13)
 898    DEP_FIELD(ERROR_SIG_EN_1, LPD_SWDT, 1, 12)
 899    DEP_FIELD(ERROR_SIG_EN_1, RPU_CCF, 1, 9)
 900    DEP_FIELD(ERROR_SIG_EN_1, RPU_LS, 2, 6)
 901    DEP_FIELD(ERROR_SIG_EN_1, FPD_TEMP, 1, 5)
 902    DEP_FIELD(ERROR_SIG_EN_1, LPD_TEMP, 1, 4)
 903    DEP_FIELD(ERROR_SIG_EN_1, RPU1, 1, 3)
 904    DEP_FIELD(ERROR_SIG_EN_1, RPU0, 1, 2)
 905    DEP_FIELD(ERROR_SIG_EN_1, OCM_ECC, 1, 1)
 906    DEP_FIELD(ERROR_SIG_EN_1, DDR_ECC, 1, 0)
 907DEP_REG32(ERROR_SIG_DIS_1, 0x588)
 908    DEP_FIELD(ERROR_SIG_DIS_1, AUX3, 1, 31)
 909    DEP_FIELD(ERROR_SIG_DIS_1, AUX2, 1, 30)
 910    DEP_FIELD(ERROR_SIG_DIS_1, AUX1, 1, 29)
 911    DEP_FIELD(ERROR_SIG_DIS_1, AUX0, 1, 28)
 912    DEP_FIELD(ERROR_SIG_DIS_1, DFT, 1, 27)
 913    DEP_FIELD(ERROR_SIG_DIS_1, CLK_MON, 1, 26)
 914    DEP_FIELD(ERROR_SIG_DIS_1, XMPU, 2, 24)
 915    DEP_FIELD(ERROR_SIG_DIS_1, PWR_SUPPLY, 8, 16)
 916    DEP_FIELD(ERROR_SIG_DIS_1, FPD_SWDT, 1, 13)
 917    DEP_FIELD(ERROR_SIG_DIS_1, LPD_SWDT, 1, 12)
 918    DEP_FIELD(ERROR_SIG_DIS_1, RPU_CCF, 1, 9)
 919    DEP_FIELD(ERROR_SIG_DIS_1, RPU_LS, 2, 6)
 920    DEP_FIELD(ERROR_SIG_DIS_1, FPD_TEMP, 1, 5)
 921    DEP_FIELD(ERROR_SIG_DIS_1, LPD_TEMP, 1, 4)
 922    DEP_FIELD(ERROR_SIG_DIS_1, RPU1, 1, 3)
 923    DEP_FIELD(ERROR_SIG_DIS_1, RPU0, 1, 2)
 924    DEP_FIELD(ERROR_SIG_DIS_1, OCM_ECC, 1, 1)
 925    DEP_FIELD(ERROR_SIG_DIS_1, DDR_ECC, 1, 0)
 926DEP_REG32(ERROR_SIG_MASK_2, 0x58c)
 927    DEP_FIELD(ERROR_SIG_MASK_2, CSU_ROM, 1, 26)
 928    DEP_FIELD(ERROR_SIG_MASK_2, PMU_PB, 1, 25)
 929    DEP_FIELD(ERROR_SIG_MASK_2, PMU_SERVICE, 1, 24)
 930    DEP_FIELD(ERROR_SIG_MASK_2, PMU_FW, 4, 18)
 931    DEP_FIELD(ERROR_SIG_MASK_2, PMU_UC, 1, 17)
 932    DEP_FIELD(ERROR_SIG_MASK_2, CSU, 1, 16)
 933    DEP_FIELD(ERROR_SIG_MASK_2, PLL_LOCK, 5, 8)
 934    DEP_FIELD(ERROR_SIG_MASK_2, PL, 4, 2)
 935    DEP_FIELD(ERROR_SIG_MASK_2, TO, 2, 0)
 936DEP_REG32(ERROR_SIG_EN_2, 0x590)
 937    DEP_FIELD(ERROR_SIG_EN_2, CSU_ROM, 1, 26)
 938    DEP_FIELD(ERROR_SIG_EN_2, PMU_PB, 1, 25)
 939    DEP_FIELD(ERROR_SIG_EN_2, PMU_SERVICE, 1, 24)
 940    DEP_FIELD(ERROR_SIG_EN_2, PMU_FW, 4, 18)
 941    DEP_FIELD(ERROR_SIG_EN_2, PMU_UC, 1, 17)
 942    DEP_FIELD(ERROR_SIG_EN_2, CSU, 1, 16)
 943    DEP_FIELD(ERROR_SIG_EN_2, PLL_LOCK, 5, 8)
 944    DEP_FIELD(ERROR_SIG_EN_2, PL, 4, 2)
 945    DEP_FIELD(ERROR_SIG_EN_2, TO, 2, 0)
 946DEP_REG32(ERROR_SIG_DIS_2, 0x594)
 947    DEP_FIELD(ERROR_SIG_DIS_2, CSU_ROM, 1, 26)
 948    DEP_FIELD(ERROR_SIG_DIS_2, PMU_PB, 1, 25)
 949    DEP_FIELD(ERROR_SIG_DIS_2, PMU_SERVICE, 1, 24)
 950    DEP_FIELD(ERROR_SIG_DIS_2, PMU_FW, 4, 18)
 951    DEP_FIELD(ERROR_SIG_DIS_2, PMU_UC, 1, 17)
 952    DEP_FIELD(ERROR_SIG_DIS_2, CSU, 1, 16)
 953    DEP_FIELD(ERROR_SIG_DIS_2, PLL_LOCK, 5, 8)
 954    DEP_FIELD(ERROR_SIG_DIS_2, PL, 4, 2)
 955    DEP_FIELD(ERROR_SIG_DIS_2, TO, 2, 0)
 956DEP_REG32(ERROR_EN_1, 0x5A0)
 957    DEP_FIELD(ERROR_EN_1, AUX3, 1, 31)
 958    DEP_FIELD(ERROR_EN_1, AUX2, 1, 30)
 959    DEP_FIELD(ERROR_EN_1, AUX1, 1, 29)
 960    DEP_FIELD(ERROR_EN_1, AUX0, 1, 28)
 961    DEP_FIELD(ERROR_EN_1, DFT, 1, 27)
 962    DEP_FIELD(ERROR_EN_1, CLK_MON, 1, 26)
 963    DEP_FIELD(ERROR_EN_1, XMPU, 2, 24)
 964    DEP_FIELD(ERROR_EN_1, PWR_SUPPLY, 8, 16)
 965    DEP_FIELD(ERROR_EN_1, FPD_SWDT, 1, 13)
 966    DEP_FIELD(ERROR_EN_1, LPD_SWDT, 1, 12)
 967    DEP_FIELD(ERROR_EN_1, RPU_CCF, 1, 9)
 968    DEP_FIELD(ERROR_EN_1, RPU_LS, 2, 6)
 969    DEP_FIELD(ERROR_EN_1, FPD_TEMP, 1, 5)
 970    DEP_FIELD(ERROR_EN_1, LPD_TEMP, 1, 4)
 971    DEP_FIELD(ERROR_EN_1, RPU1, 1, 3)
 972    DEP_FIELD(ERROR_EN_1, RPU0, 1, 2)
 973    DEP_FIELD(ERROR_EN_1, OCM_ECC, 1, 1)
 974    DEP_FIELD(ERROR_EN_1, DDR_ECC, 1, 0)
 975DEP_REG32(ERROR_EN_2, 0x5A4)
 976    DEP_FIELD(ERROR_EN_2, CSU_ROM, 1, 26)
 977    DEP_FIELD(ERROR_EN_2, PMU_PB, 1, 25)
 978    DEP_FIELD(ERROR_EN_2, PMU_SERVICE, 1, 24)
 979    DEP_FIELD(ERROR_EN_2, PMU_FW, 4, 18)
 980    DEP_FIELD(ERROR_EN_2, PMU_UC, 1, 17)
 981    DEP_FIELD(ERROR_EN_2, CSU, 1, 16)
 982    DEP_FIELD(ERROR_EN_2, PLL_LOCK, 5, 8)
 983    DEP_FIELD(ERROR_EN_2, PL, 4, 2)
 984    DEP_FIELD(ERROR_EN_2, TO, 2, 0)
 985DEP_REG32(AIB_CNTRL, 0x600)
 986    DEP_FIELD(AIB_CNTRL, FPD_AFI_FS, 1, 3)
 987    DEP_FIELD(AIB_CNTRL, FPD_AFI_FM, 1, 2)
 988    DEP_FIELD(AIB_CNTRL, LPDAFI_FS, 1, 1)
 989    DEP_FIELD(AIB_CNTRL, LPDAFI_FM, 1, 0)
 990DEP_REG32(AIB_STATUS, 0x604)
 991    DEP_FIELD(AIB_STATUS, FPD_AFI_FS, 1, 3)
 992    DEP_FIELD(AIB_STATUS, FPD_AFI_FM, 1, 2)
 993    DEP_FIELD(AIB_STATUS, LPDAFI_FS, 1, 1)
 994    DEP_FIELD(AIB_STATUS, LPDAFI_FM, 1, 0)
 995DEP_REG32(GLOBAL_RESET, 0x608)
 996    DEP_FIELD(GLOBAL_RESET, PS_ONLY_RST, 1, 10)
 997    DEP_FIELD(GLOBAL_RESET, FPD_RST, 1, 9)
 998    DEP_FIELD(GLOBAL_RESET, RPU_LS_RST, 1, 8)
 999DEP_REG32(ROM_VALIDATION_STATUS, 0x610)
1000    DEP_FIELD(ROM_VALIDATION_STATUS, PASS, 1, 1)
1001    DEP_FIELD(ROM_VALIDATION_STATUS, DONE, 1, 0)
1002DEP_REG32(ROM_VALIDATION_DIGEST_0, 0x614)
1003DEP_REG32(ROM_VALIDATION_DIGEST_1, 0x618)
1004DEP_REG32(ROM_VALIDATION_DIGEST_2, 0x61c)
1005DEP_REG32(ROM_VALIDATION_DIGEST_3, 0x620)
1006DEP_REG32(ROM_VALIDATION_DIGEST_4, 0x624)
1007DEP_REG32(ROM_VALIDATION_DIGEST_5, 0x628)
1008DEP_REG32(ROM_VALIDATION_DIGEST_6, 0x62c)
1009DEP_REG32(ROM_VALIDATION_DIGEST_7, 0x630)
1010DEP_REG32(ROM_VALIDATION_DIGEST_8, 0x634)
1011DEP_REG32(ROM_VALIDATION_DIGEST_9, 0x638)
1012DEP_REG32(ROM_VALIDATION_DIGEST_10, 0x63c)
1013DEP_REG32(ROM_VALIDATION_DIGEST_11, 0x640)
1014DEP_REG32(SAFETY_GATE, 0x650)
1015DEP_REG32(MBIST_RST, 0x700)
1016DEP_REG32(MBIST_PG_EN, 0x704)
1017DEP_REG32(MBIST_SETUP, 0x708)
1018DEP_REG32(MBIST_DONE, 0x710)
1019DEP_REG32(MBIST_GOOD, 0x714)
1020DEP_REG32(SAFETY_CHK, 0x800)
1021
1022#define R_MAX (R_SAFETY_CHK + 1)
1023
1024typedef struct PMU_GLOBAL {
1025    SysBusDevice parent_obj;
1026    MemoryRegion iomem;
1027    qemu_irq irq_req_pwrdwn_int;
1028    qemu_irq irq_req_swrst_int;
1029    qemu_irq irq_req_logclr_int;
1030    qemu_irq irq_req_pwrup_int;
1031    qemu_irq irq_addr_error_int;
1032    qemu_irq irq_error_int_2;
1033    qemu_irq irq_error_int_1;
1034    qemu_irq irq_req_iso_int;
1035
1036    bool fw_is_present;
1037    bool ignore_pwr_req;
1038    /* Record hardware error events, so error status register can be updated
1039     * if error is enabled in error enable register.
1040     */
1041    uint32_t error_1;
1042    uint32_t error_2;
1043
1044    uint32_t regs[R_MAX];
1045    DepRegisterInfo regs_info[R_MAX];
1046} PMU_GLOBAL;
1047
1048static void req_pwrdwn_int_update_irq(PMU_GLOBAL *s)
1049{
1050    bool pending = s->regs[R_REQ_PWRDWN_STATUS] & ~s->regs[R_REQ_PWRDWN_INT_MASK];
1051    qemu_set_irq(s->irq_req_pwrdwn_int, pending);
1052}
1053
1054static void req_pwrdwn_status_postw(DepRegisterInfo *reg, uint64_t val64)
1055{
1056    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1057    req_pwrdwn_int_update_irq(s);
1058}
1059
1060static uint64_t req_pwrdwn_int_en_prew(DepRegisterInfo *reg, uint64_t val64)
1061{
1062    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1063    uint32_t val = val64;
1064
1065    s->regs[R_REQ_PWRDWN_INT_MASK] &= ~val;
1066    req_pwrdwn_int_update_irq(s);
1067    return 0;
1068}
1069
1070static uint64_t req_pwrdwn_int_dis_prew(DepRegisterInfo *reg, uint64_t val64)
1071{
1072    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1073    uint32_t val = val64;
1074
1075    s->regs[R_REQ_PWRDWN_INT_MASK] |= val;
1076    req_pwrdwn_int_update_irq(s);
1077    return 0;
1078}
1079
1080static uint64_t req_pwrdwn_trig_prew(DepRegisterInfo *reg, uint64_t val64)
1081{
1082    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1083    uint32_t val = val64;
1084
1085    s->regs[R_REQ_PWRDWN_STATUS] |= val;
1086    req_pwrdwn_int_update_irq(s);
1087    return 0;
1088}
1089
1090static void req_swrst_int_update_irq(PMU_GLOBAL *s)
1091{
1092    bool pending = s->regs[R_REQ_SWRST_STATUS] & ~s->regs[R_REQ_SWRST_INT_MASK];
1093    qemu_set_irq(s->irq_req_swrst_int, pending);
1094}
1095
1096static void req_swrst_status_postw(DepRegisterInfo *reg, uint64_t val64)
1097{
1098    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1099    req_swrst_int_update_irq(s);
1100}
1101
1102static uint64_t req_swrst_int_en_prew(DepRegisterInfo *reg, uint64_t val64)
1103{
1104    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1105    uint32_t val = val64;
1106
1107    s->regs[R_REQ_SWRST_INT_MASK] &= ~val;
1108    req_swrst_int_update_irq(s);
1109    return 0;
1110}
1111
1112static uint64_t req_swrst_int_dis_prew(DepRegisterInfo *reg, uint64_t val64)
1113{
1114    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1115    uint32_t val = val64;
1116
1117    s->regs[R_REQ_SWRST_INT_MASK] |= val;
1118    req_swrst_int_update_irq(s);
1119    return 0;
1120}
1121
1122static uint64_t req_swrst_trig_prew(DepRegisterInfo *reg, uint64_t val64)
1123{
1124    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1125    uint32_t val = val64;
1126
1127    s->regs[R_REQ_SWRST_STATUS] |= val;
1128    req_swrst_int_update_irq(s);
1129    return 0;
1130}
1131
1132static void req_aux_int_update_irq(PMU_GLOBAL *s)
1133{
1134    bool pending = s->regs[R_REQ_AUX_STATUS] & ~s->regs[R_REQ_AUX_INT_MASK];
1135    qemu_set_irq(s->irq_req_logclr_int, pending);
1136}
1137
1138static void req_aux_status_postw(DepRegisterInfo *reg, uint64_t val64)
1139{
1140    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1141    req_aux_int_update_irq(s);
1142}
1143
1144static uint64_t req_aux_int_en_prew(DepRegisterInfo *reg, uint64_t val64)
1145{
1146    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1147    uint32_t val = val64;
1148
1149    s->regs[R_REQ_AUX_INT_MASK] &= ~val;
1150    req_aux_int_update_irq(s);
1151    return 0;
1152}
1153
1154static uint64_t req_aux_int_dis_prew(DepRegisterInfo *reg, uint64_t val64)
1155{
1156    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1157    uint32_t val = val64;
1158
1159    s->regs[R_REQ_AUX_INT_MASK] |= val;
1160    req_aux_int_update_irq(s);
1161    return 0;
1162}
1163
1164static uint64_t req_aux_trig_prew(DepRegisterInfo *reg, uint64_t val64)
1165{
1166    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1167    uint32_t val = val64;
1168
1169    s->regs[R_REQ_AUX_STATUS] |= val;
1170    req_aux_int_update_irq(s);
1171    return 0;
1172}
1173
1174static uint64_t error_srst_en_2_prew(DepRegisterInfo *reg, uint64_t val64)
1175{
1176    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1177    uint32_t val = val64;
1178
1179    s->regs[R_ERROR_SRST_MASK_2] &= ~val;
1180    return 0;
1181}
1182
1183static uint64_t error_srst_dis_2_prew(DepRegisterInfo *reg, uint64_t val64)
1184{
1185    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1186    uint32_t val = val64;
1187
1188    s->regs[R_ERROR_SRST_MASK_2] |= val;
1189    return 0;
1190}
1191
1192static uint64_t error_srst_en_1_prew(DepRegisterInfo *reg, uint64_t val64)
1193{
1194    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1195    uint32_t val = val64;
1196
1197    s->regs[R_ERROR_SRST_MASK_1] &= ~val;
1198    return 0;
1199}
1200
1201static uint64_t error_srst_dis_1_prew(DepRegisterInfo *reg, uint64_t val64)
1202{
1203    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1204    uint32_t val = val64;
1205
1206    s->regs[R_ERROR_SRST_MASK_1] |= val;
1207    return 0;
1208}
1209
1210static uint64_t error_sig_en_2_prew(DepRegisterInfo *reg, uint64_t val64)
1211{
1212    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1213    uint32_t val = val64;
1214
1215    s->regs[R_ERROR_SIG_MASK_2] &= ~val;
1216    return 0;
1217}
1218
1219static uint64_t error_sig_dis_2_prew(DepRegisterInfo *reg, uint64_t val64)
1220{
1221    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1222    uint32_t val = val64;
1223
1224    s->regs[R_ERROR_SIG_MASK_2] |= val;
1225    return 0;
1226}
1227
1228static void req_pwrup_int_update_irq(PMU_GLOBAL *s)
1229{
1230    bool pending = s->regs[R_REQ_PWRUP_STATUS] & ~s->regs[R_REQ_PWRUP_INT_MASK];
1231    qemu_set_irq(s->irq_req_pwrup_int, pending);
1232}
1233
1234static void req_pwrup_status_postw(DepRegisterInfo *reg, uint64_t val64)
1235{
1236    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1237    req_pwrup_int_update_irq(s);
1238}
1239
1240static uint64_t req_pwrup_int_en_prew(DepRegisterInfo *reg, uint64_t val64)
1241{
1242    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1243    uint32_t val = val64;
1244
1245    s->regs[R_REQ_PWRUP_INT_MASK] &= ~val;
1246    req_pwrup_int_update_irq(s);
1247    return 0;
1248}
1249
1250static uint64_t req_pwrup_int_dis_prew(DepRegisterInfo *reg, uint64_t val64)
1251{
1252    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1253    uint32_t val = val64;
1254
1255    s->regs[R_REQ_PWRUP_INT_MASK] |= val;
1256    req_pwrup_int_update_irq(s);
1257    return 0;
1258}
1259
1260static uint64_t req_pwrup_trig_prew(DepRegisterInfo *reg, uint64_t val64)
1261{
1262    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1263    uint32_t val = val64;
1264
1265    if (!s->ignore_pwr_req) {
1266        s->regs[R_REQ_PWRUP_STATUS] |= val;
1267    }
1268    req_pwrup_int_update_irq(s);
1269    return 0;
1270}
1271
1272static uint64_t error_sig_en_1_prew(DepRegisterInfo *reg, uint64_t val64)
1273{
1274    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1275    uint32_t val = val64;
1276
1277    s->regs[R_ERROR_SIG_MASK_1] &= ~val;
1278    return 0;
1279}
1280
1281static uint64_t error_sig_dis_1_prew(DepRegisterInfo *reg, uint64_t val64)
1282{
1283    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1284    uint32_t val = val64;
1285
1286    s->regs[R_ERROR_SIG_MASK_1] |= val;
1287    return 0;
1288}
1289
1290static void addr_error_int_update_irq(PMU_GLOBAL *s)
1291{
1292    bool pending = s->regs[R_ADDR_ERROR_STATUS] & ~s->regs[R_ADDR_ERROR_INT_MASK];
1293    qemu_set_irq(s->irq_addr_error_int, pending);
1294}
1295
1296static void addr_error_status_postw(DepRegisterInfo *reg, uint64_t val64)
1297{
1298    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1299    addr_error_int_update_irq(s);
1300}
1301
1302static uint64_t addr_error_int_en_prew(DepRegisterInfo *reg, uint64_t val64)
1303{
1304    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1305    uint32_t val = val64;
1306
1307    s->regs[R_ADDR_ERROR_INT_MASK] &= ~val;
1308    addr_error_int_update_irq(s);
1309    return 0;
1310}
1311
1312static uint64_t addr_error_int_dis_prew(DepRegisterInfo *reg, uint64_t val64)
1313{
1314    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1315    uint32_t val = val64;
1316
1317    s->regs[R_ADDR_ERROR_INT_MASK] |= val;
1318    addr_error_int_update_irq(s);
1319    return 0;
1320}
1321
1322static void error_int_2_update_irq(PMU_GLOBAL *s)
1323{
1324    bool pending = s->regs[R_ERROR_STATUS_2] & ~s->regs[R_ERROR_INT_MASK_2];
1325    qemu_set_irq(s->irq_error_int_2, pending);
1326}
1327
1328static void error_status_2_postw(DepRegisterInfo *reg, uint64_t val64)
1329{
1330    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1331    s->error_2 = val64;
1332    error_int_2_update_irq(s);
1333}
1334
1335static uint64_t error_int_en_2_prew(DepRegisterInfo *reg, uint64_t val64)
1336{
1337    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1338    uint32_t val = val64;
1339
1340    s->regs[R_ERROR_INT_MASK_2] &= ~val;
1341    error_int_2_update_irq(s);
1342    return 0;
1343}
1344
1345static uint64_t error_int_dis_2_prew(DepRegisterInfo *reg, uint64_t val64)
1346{
1347    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1348    uint32_t val = val64;
1349
1350    s->regs[R_ERROR_INT_MASK_2] |= val;
1351    error_int_2_update_irq(s);
1352    return 0;
1353}
1354
1355static void error_int_1_update_irq(PMU_GLOBAL *s)
1356{
1357    bool pending = s->regs[R_ERROR_STATUS_1] & ~s->regs[R_ERROR_INT_MASK_1];
1358    qemu_set_irq(s->irq_error_int_1, pending);
1359}
1360
1361/* Set error in ERROR_STATUS_1 register if it is enabled in ERROR_EN_1 and
1362 * error input is set.
1363 * Error is only cleared by explicitly writing a 1 to its corresponding
1364 * ERROR_STATUS_1 register bit.
1365 */
1366static void set_error_1(PMU_GLOBAL *s)
1367{
1368    s->regs[R_ERROR_STATUS_1] |= s->error_1 & s->regs[R_ERROR_EN_1];
1369    error_int_1_update_irq(s);
1370}
1371
1372static void error_en_1_postw(DepRegisterInfo *reg, uint64_t val64)
1373{
1374    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1375
1376    set_error_1(s);
1377}
1378
1379/* Set error in ERROR_STATUS_2 register if it is enabled in ERROR_EN_2 and
1380 * error input is set.
1381 * Error is only cleared by explicitly writing a 1 to its corresponding
1382 * ERROR_STATUS_2 register bit.
1383 */
1384static void set_error_2(PMU_GLOBAL *s)
1385{
1386    s->regs[R_ERROR_STATUS_2] |= s->error_2 & s->regs[R_ERROR_EN_2];
1387    error_int_2_update_irq(s);
1388}
1389
1390static void error_en_2_postw(DepRegisterInfo *reg, uint64_t val64)
1391{
1392    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1393
1394    set_error_2(s);
1395}
1396
1397static void error_status_1_postw(DepRegisterInfo *reg, uint64_t val64)
1398{
1399    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1400    s->error_1 = val64;
1401    error_int_1_update_irq(s);
1402}
1403
1404static uint64_t error_int_en_1_prew(DepRegisterInfo *reg, uint64_t val64)
1405{
1406    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1407    uint32_t val = val64;
1408
1409    s->regs[R_ERROR_INT_MASK_1] &= ~val;
1410    error_int_1_update_irq(s);
1411    return 0;
1412}
1413
1414static uint64_t error_int_dis_1_prew(DepRegisterInfo *reg, uint64_t val64)
1415{
1416    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1417    uint32_t val = val64;
1418
1419    s->regs[R_ERROR_INT_MASK_1] |= val;
1420    error_int_1_update_irq(s);
1421    return 0;
1422}
1423
1424static uint64_t error_por_en_2_prew(DepRegisterInfo *reg, uint64_t val64)
1425{
1426    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1427    uint32_t val = val64;
1428
1429    s->regs[R_ERROR_POR_MASK_2] &= ~val;
1430    return 0;
1431}
1432
1433static uint64_t error_por_dis_2_prew(DepRegisterInfo *reg, uint64_t val64)
1434{
1435    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1436    uint32_t val = val64;
1437
1438    s->regs[R_ERROR_POR_MASK_2] |= val;
1439    return 0;
1440}
1441
1442static uint64_t error_por_en_1_prew(DepRegisterInfo *reg, uint64_t val64)
1443{
1444    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1445    uint32_t val = val64;
1446
1447    s->regs[R_ERROR_POR_MASK_1] &= ~val;
1448    return 0;
1449}
1450
1451static uint64_t error_por_dis_1_prew(DepRegisterInfo *reg, uint64_t val64)
1452{
1453    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1454    uint32_t val = val64;
1455
1456    s->regs[R_ERROR_POR_MASK_1] |= val;
1457    return 0;
1458}
1459
1460static void req_iso_int_update_irq(PMU_GLOBAL *s)
1461{
1462    bool pending = s->regs[R_REQ_ISO_STATUS] & ~s->regs[R_REQ_ISO_INT_MASK];
1463    qemu_set_irq(s->irq_req_iso_int, pending);
1464}
1465
1466static void req_iso_status_postw(DepRegisterInfo *reg, uint64_t val64)
1467{
1468    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1469    req_iso_int_update_irq(s);
1470}
1471
1472static uint64_t req_iso_int_en_prew(DepRegisterInfo *reg, uint64_t val64)
1473{
1474    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1475    uint32_t val = val64;
1476
1477    s->regs[R_REQ_ISO_INT_MASK] &= ~val;
1478    req_iso_int_update_irq(s);
1479    return 0;
1480}
1481
1482static uint64_t req_iso_int_dis_prew(DepRegisterInfo *reg, uint64_t val64)
1483{
1484    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1485    uint32_t val = val64;
1486
1487    s->regs[R_REQ_ISO_INT_MASK] |= val;
1488    req_iso_int_update_irq(s);
1489    return 0;
1490}
1491
1492static uint64_t req_iso_trig_prew(DepRegisterInfo *reg, uint64_t val64)
1493{
1494    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1495    uint32_t val = val64;
1496
1497    s->regs[R_REQ_ISO_STATUS] |= val;
1498    req_iso_int_update_irq(s);
1499    return 0;
1500}
1501
1502static void mbist_rst_postw(DepRegisterInfo *reg, uint64_t val64)
1503{
1504    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1505
1506    /* Reset the MBIST_DONE, MBIST_GOOD registers */
1507    s->regs[R_MBIST_DONE] &= s->regs[R_MBIST_RST];
1508    s->regs[R_MBIST_GOOD] &= s->regs[R_MBIST_RST];
1509}
1510
1511static void mbist_pg_en_postw(DepRegisterInfo *reg, uint64_t val64)
1512{
1513    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(reg->opaque);
1514
1515    s->regs[R_MBIST_DONE] |= s->regs[R_MBIST_RST]
1516                           & s->regs[R_MBIST_SETUP] & s->regs[R_MBIST_PG_EN];
1517    s->regs[R_MBIST_GOOD] |= s->regs[R_MBIST_RST]
1518                           & s->regs[R_MBIST_SETUP] & s->regs[R_MBIST_PG_EN];
1519}
1520
1521static DepRegisterAccessInfo pmu_global_regs_info[] = {
1522    {   .name = "GLOBAL_CNTRL",  .decode.addr = A_GLOBAL_CNTRL,
1523        .rsvd = 0xfffe00e8,
1524        .ro = 0xffff00e8,
1525        .reset = 0x00008800,
1526        .gpios = (DepRegisterGPIOMapping[]) {
1527            { .name = "pmu_wake", .bit_pos = 0, .width = 1 },
1528            {},
1529        }
1530    },{ .name = "PS_CNTRL",  .decode.addr = A_PS_CNTRL,
1531        .rsvd = 0xfffefffc,
1532        .ro = 0xfffffffc,
1533    },{ .name = "APU_PWR_STATUS_INIT",  .decode.addr = A_APU_PWR_STATUS_INIT,
1534        .rsvd = 0xfffffff0,
1535        .ro = 0xfffffff0,
1536    },{ .name = "ADDR_ERROR_STATUS",  .decode.addr = A_ADDR_ERROR_STATUS,
1537        .rsvd = 0xfffffffe,
1538        .ro = 0xfffffffe,
1539        .w1c = 0x1,
1540        .post_write = addr_error_status_postw,
1541    },{ .name = "ADDR_ERROR_INT_MASK",  .decode.addr = A_ADDR_ERROR_INT_MASK,
1542        .reset = 0x1,
1543        .rsvd = 0xfffffffe,
1544        .ro = 0xffffffff,
1545    },{ .name = "ADDR_ERROR_INT_EN",  .decode.addr = A_ADDR_ERROR_INT_EN,
1546        .pre_write = addr_error_int_en_prew,
1547    },{ .name = "ADDR_ERROR_INT_DIS",  .decode.addr = A_ADDR_ERROR_INT_DIS,
1548        .pre_write = addr_error_int_dis_prew,
1549    },{ .name = "GLOBAL_GEN_STORAGE0",  .decode.addr = A_GLOBAL_GEN_STORAGE0,
1550    },{ .name = "GLOBAL_GEN_STORAGE1",  .decode.addr = A_GLOBAL_GEN_STORAGE1,
1551    },{ .name = "GLOBAL_GEN_STORAGE2",  .decode.addr = A_GLOBAL_GEN_STORAGE2,
1552    },{ .name = "GLOBAL_GEN_STORAGE3",  .decode.addr = A_GLOBAL_GEN_STORAGE3,
1553    },{ .name = "GLOBAL_GEN_STORAGE4",  .decode.addr = A_GLOBAL_GEN_STORAGE4,
1554    },{ .name = "GLOBAL_GEN_STORAGE5",  .decode.addr = A_GLOBAL_GEN_STORAGE5,
1555    },{ .name = "GLOBAL_GEN_STORAGE6",  .decode.addr = A_GLOBAL_GEN_STORAGE6,
1556    },{ .name = "PERS_GLOB_GEN_STORAGE0",  .decode.addr = A_PERS_GLOB_GEN_STORAGE0,
1557        .inhibit_reset = 0xFFFFFFFF,
1558    },{ .name = "PERS_GLOB_GEN_STORAGE1",  .decode.addr = A_PERS_GLOB_GEN_STORAGE1,
1559        .inhibit_reset = 0xFFFFFFFF,
1560    },{ .name = "PERS_GLOB_GEN_STORAGE2",  .decode.addr = A_PERS_GLOB_GEN_STORAGE2,
1561        .inhibit_reset = 0xFFFFFFFF,
1562    },{ .name = "PERS_GLOB_GEN_STORAGE3",  .decode.addr = A_PERS_GLOB_GEN_STORAGE3,
1563        .inhibit_reset = 0xFFFFFFFF,
1564    },{ .name = "PERS_GLOB_GEN_STORAGE4",  .decode.addr = A_PERS_GLOB_GEN_STORAGE4,
1565        .inhibit_reset = 0xFFFFFFFF,
1566    },{ .name = "PERS_GLOB_GEN_STORAGE5",  .decode.addr = A_PERS_GLOB_GEN_STORAGE5,
1567        .inhibit_reset = 0xFFFFFFFF,
1568    },{ .name = "PERS_GLOB_GEN_STORAGE6",  .decode.addr = A_PERS_GLOB_GEN_STORAGE6,
1569        .inhibit_reset = 0xFFFFFFFF,
1570    },{ .name = "PERS_GLOB_GEN_STORAGE7",  .decode.addr = A_PERS_GLOB_GEN_STORAGE7,
1571        .inhibit_reset = 0xFFFFFFFF,
1572    },{ .name = "DDR_CNTRL",  .decode.addr = A_DDR_CNTRL,
1573        .rsvd = 0xfffffffe,
1574    },{ .name = "PWR_STATE",  .decode.addr = A_PWR_STATE,
1575        .reset = 0x00fffcbf,
1576        .rsvd = 0xff000340,
1577        .ro = 0xffffffff,
1578    },{ .name = "AUX_PWR_STATE",  .decode.addr = A_AUX_PWR_STATE,
1579        .reset = 0xff080,
1580        .rsvd = 0x7f00f7f,
1581        .ro = 0xffffffff,
1582    },{ .name = "RAM_RET_CNTRL",  .decode.addr = A_RAM_RET_CNTRL,
1583        .rsvd = 0xfff00f7f,
1584        .ro = 0xfff00f7f,
1585    },{ .name = "PWR_SUPPLY_STATUS",  .decode.addr = A_PWR_SUPPLY_STATUS,
1586        /* FIXME: Added 0x3 to reset bits so FPD will be
1587         * properly powered up by PMUROM.
1588         */
1589        .reset = 0x3,
1590        .rsvd = 0xfffffffc,
1591        .ro = 0xffffffff,
1592    },{ .name = "REQ_PWRUP_STATUS",  .decode.addr = A_REQ_PWRUP_STATUS,
1593        .rsvd = 0xff000b40,
1594        .ro = 0xff000b40,
1595        .w1c = 0xfff4bf,
1596        .post_write = req_pwrup_status_postw,
1597    },{ .name = "REQ_PWRUP_INT_MASK",  .decode.addr = A_REQ_PWRUP_INT_MASK,
1598        .reset = 0xfff4bf,
1599        .rsvd = 0xff000b40,
1600        .ro = 0xffffffff,
1601    },{ .name = "REQ_PWRUP_INT_EN",  .decode.addr = A_REQ_PWRUP_INT_EN,
1602        .pre_write = req_pwrup_int_en_prew,
1603    },{ .name = "REQ_PWRUP_INT_DIS",  .decode.addr = A_REQ_PWRUP_INT_DIS,
1604        .pre_write = req_pwrup_int_dis_prew,
1605    },{ .name = "REQ_PWRUP_TRIG",  .decode.addr = A_REQ_PWRUP_TRIG,
1606        .pre_write = req_pwrup_trig_prew,
1607    },{ .name = "REQ_PWRDWN_STATUS",  .decode.addr = A_REQ_PWRDWN_STATUS,
1608        .rsvd = 0xff000b40,
1609        .ro = 0xff000b40,
1610        .w1c = 0xfff4bf,
1611        .post_write = req_pwrdwn_status_postw,
1612    },{ .name = "REQ_PWRDWN_INT_MASK",  .decode.addr = A_REQ_PWRDWN_INT_MASK,
1613        .reset = 0xfff4bf,
1614        .rsvd = 0xff000b40,
1615        .ro = 0xffffffff,
1616    },{ .name = "REQ_PWRDWN_INT_EN",  .decode.addr = A_REQ_PWRDWN_INT_EN,
1617        .pre_write = req_pwrdwn_int_en_prew,
1618    },{ .name = "REQ_PWRDWN_INT_DIS",  .decode.addr = A_REQ_PWRDWN_INT_DIS,
1619        .pre_write = req_pwrdwn_int_dis_prew,
1620    },{ .name = "REQ_PWRDWN_TRIG",  .decode.addr = A_REQ_PWRDWN_TRIG,
1621        .pre_write = req_pwrdwn_trig_prew,
1622    },{ .name = "REQ_ISO_STATUS",  .decode.addr = A_REQ_ISO_STATUS,
1623        .rsvd = 0xffffffec,
1624        .ro = 0xffffffec,
1625        .w1c = 0x13,
1626        .post_write = req_iso_status_postw,
1627    },{ .name = "REQ_ISO_INT_MASK",  .decode.addr = A_REQ_ISO_INT_MASK,
1628        .reset = 0x13,
1629        .rsvd = 0xffffffec,
1630        .ro = 0xffffffff,
1631    },{ .name = "REQ_ISO_INT_EN",  .decode.addr = A_REQ_ISO_INT_EN,
1632        .pre_write = req_iso_int_en_prew,
1633    },{ .name = "REQ_ISO_INT_DIS",  .decode.addr = A_REQ_ISO_INT_DIS,
1634        .pre_write = req_iso_int_dis_prew,
1635    },{ .name = "REQ_ISO_TRIG",  .decode.addr = A_REQ_ISO_TRIG,
1636        .pre_write = req_iso_trig_prew,
1637    },{ .name = "REQ_SWRST_STATUS",  .decode.addr = A_REQ_SWRST_STATUS,
1638        .rsvd = 0x408e820,
1639        .ro = 0x408e820,
1640        .w1c = 0xfbf717df,
1641        .post_write = req_swrst_status_postw,
1642    },{ .name = "REQ_SWRST_INT_MASK",  .decode.addr = A_REQ_SWRST_INT_MASK,
1643        .reset = 0xfbf717df,
1644        .rsvd = 0x408e820,
1645        .ro = 0xffffffff,
1646    },{ .name = "REQ_SWRST_INT_EN",  .decode.addr = A_REQ_SWRST_INT_EN,
1647        .pre_write = req_swrst_int_en_prew,
1648    },{ .name = "REQ_SWRST_INT_DIS",  .decode.addr = A_REQ_SWRST_INT_DIS,
1649        .pre_write = req_swrst_int_dis_prew,
1650    },{ .name = "REQ_SWRST_TRIG",  .decode.addr = A_REQ_SWRST_TRIG,
1651        .pre_write = req_swrst_trig_prew,
1652    },{ .name = "REQ_AUX_STATUS",  .decode.addr = A_REQ_AUX_STATUS,
1653        .rsvd = 0xfffccb30,
1654        .ro = 0xfffccb30,
1655        .w1c = 0x334cf,
1656        .post_write = req_aux_status_postw,
1657    },{ .name = "REQ_AUX_INT_MASK",  .decode.addr = A_REQ_AUX_INT_MASK,
1658        .reset = 0x334cf,
1659        .rsvd = 0xfffccb30,
1660        .ro = 0xffffffff,
1661    },{ .name = "REQ_AUX_INT_EN",  .decode.addr = A_REQ_AUX_INT_EN,
1662        .pre_write = req_aux_int_en_prew,
1663    },{ .name = "REQ_AUX_INT_DIS",  .decode.addr = A_REQ_AUX_INT_DIS,
1664        .pre_write = req_aux_int_dis_prew,
1665    },{ .name = "REQ_AUX_TRIG",  .decode.addr = A_REQ_AUX_TRIG,
1666        .pre_write = req_aux_trig_prew,
1667    },{ .name = "LOGCLR_STATUS",  .decode.addr = A_LOGCLR_STATUS,
1668        .rsvd = 0xfffccb30,
1669        .ro = 0xffffffff,
1670    },{ .name = "CSU_BR_ERROR",  .decode.addr = A_CSU_BR_ERROR,
1671        .rsvd = 0x7fff0000,
1672        .ro = 0x7fff0000,
1673    },{ .name = "MB_FAULT_STATUS",  .decode.addr = A_MB_FAULT_STATUS,
1674        .rsvd = 0xf000f0,
1675        .ro = 0xffffffff,
1676    },{ .name = "ERROR_STATUS_1",  .decode.addr = A_ERROR_STATUS_1,
1677        .rsvd = 0xcd00,
1678        .ro = 0xcd00,
1679        .w1c = 0x3ff32ff,
1680        .post_write = error_status_1_postw,
1681    },{ .name = "ERROR_INT_MASK_1",  .decode.addr = A_ERROR_INT_MASK_1,
1682        .reset = 0x3ff32ff,
1683        .rsvd = 0xcd00,
1684        .ro = 0x3ffffff,
1685    },{ .name = "ERROR_INT_EN_1",  .decode.addr = A_ERROR_INT_EN_1,
1686        .rsvd = 0xcd00,
1687        .pre_write = error_int_en_1_prew,
1688    },{ .name = "ERROR_INT_DIS_1",  .decode.addr = A_ERROR_INT_DIS_1,
1689        .rsvd = 0xcd00,
1690        .pre_write = error_int_dis_1_prew,
1691    },{ .name = "ERROR_STATUS_2",  .decode.addr = A_ERROR_STATUS_2,
1692        .rsvd = 0xf8c0e0c0,
1693        .ro = 0xf8c0e0c0,
1694        .w1c = 0x73f1f3f,
1695        .post_write = error_status_2_postw,
1696    },{ .name = "ERROR_INT_MASK_2",  .decode.addr = A_ERROR_INT_MASK_2,
1697        .reset = 0x13f1f3f,
1698        .rsvd = 0xf8c0e0c0,
1699        .ro = 0xffffffff,
1700    },{ .name = "ERROR_INT_EN_2",  .decode.addr = A_ERROR_INT_EN_2,
1701        .rsvd = 0xf8c0e0c0,
1702        .pre_write = error_int_en_2_prew,
1703    },{ .name = "ERROR_INT_DIS_2",  .decode.addr = A_ERROR_INT_DIS_2,
1704        .rsvd = 0xf8c0e0c0,
1705        .pre_write = error_int_dis_2_prew,
1706    },{ .name = "ERROR_POR_MASK_1",  .decode.addr = A_ERROR_POR_MASK_1,
1707        .reset = 0x3ff32ff,
1708        .rsvd = 0xcd00,
1709        .ro = 0x3ffffff,
1710    },{ .name = "ERROR_POR_EN_1",  .decode.addr = A_ERROR_POR_EN_1,
1711        .rsvd = 0xcd00,
1712        .pre_write = error_por_en_1_prew,
1713    },{ .name = "ERROR_POR_DIS_1",  .decode.addr = A_ERROR_POR_DIS_1,
1714        .rsvd = 0xcd00,
1715        .pre_write = error_por_dis_1_prew,
1716    },{ .name = "ERROR_POR_MASK_2",  .decode.addr = A_ERROR_POR_MASK_2,
1717        .reset = 0x13f1f3f,
1718        .rsvd = 0xf8c0e0c0,
1719        .ro = 0xffffffff,
1720    },{ .name = "ERROR_POR_EN_2",  .decode.addr = A_ERROR_POR_EN_2,
1721        .rsvd = 0xf8c0e0c0,
1722        .pre_write = error_por_en_2_prew,
1723    },{ .name = "ERROR_POR_DIS_2",  .decode.addr = A_ERROR_POR_DIS_2,
1724        .rsvd = 0xf8c0e0c0,
1725        .pre_write = error_por_dis_2_prew,
1726    },{ .name = "ERROR_SRST_MASK_1",  .decode.addr = A_ERROR_SRST_MASK_1,
1727        .reset = 0x3ff32ff,
1728        .rsvd = 0xcd00,
1729        .ro = 0x3ffffff,
1730    },{ .name = "ERROR_SRST_EN_1",  .decode.addr = A_ERROR_SRST_EN_1,
1731        .rsvd = 0xcd00,
1732        .pre_write = error_srst_en_1_prew,
1733    },{ .name = "ERROR_SRST_DIS_1",  .decode.addr = A_ERROR_SRST_DIS_1,
1734        .rsvd = 0xcd00,
1735        .pre_write = error_srst_dis_1_prew,
1736    },{ .name = "ERROR_SRST_MASK_2",  .decode.addr = A_ERROR_SRST_MASK_2,
1737        .reset = 0x13f1f3f,
1738        .rsvd = 0xf8c0e0c0,
1739        .ro = 0xffffffff,
1740    },{ .name = "ERROR_SRST_EN_2",  .decode.addr = A_ERROR_SRST_EN_2,
1741        .rsvd = 0xf8c0e0c0,
1742        .pre_write = error_srst_en_2_prew,
1743    },{ .name = "ERROR_SRST_DIS_2",  .decode.addr = A_ERROR_SRST_DIS_2,
1744        .rsvd = 0xf8c0e0c0,
1745        .pre_write = error_srst_dis_2_prew,
1746    },{ .name = "ERROR_SIG_MASK_1",  .decode.addr = A_ERROR_SIG_MASK_1,
1747        .rsvd = 0xcd00,
1748        .ro = 0x3ffffff,
1749    },{ .name = "ERROR_SIG_EN_1",  .decode.addr = A_ERROR_SIG_EN_1,
1750        .rsvd = 0xcd00,
1751        .pre_write = error_sig_en_1_prew,
1752    },{ .name = "ERROR_SIG_DIS_1",  .decode.addr = A_ERROR_SIG_DIS_1,
1753        .rsvd = 0xcd00,
1754        .pre_write = error_sig_dis_1_prew,
1755    },{ .name = "ERROR_SIG_MASK_2",  .decode.addr = A_ERROR_SIG_MASK_2,
1756        .rsvd = 0xf8c0e0c0,
1757        .ro = 0xffffffff,
1758    },{ .name = "ERROR_SIG_EN_2",  .decode.addr = A_ERROR_SIG_EN_2,
1759        .rsvd = 0xf8c0e0c0,
1760        .pre_write = error_sig_en_2_prew,
1761    },{ .name = "ERROR_SIG_DIS_2",  .decode.addr = A_ERROR_SIG_DIS_2,
1762        .rsvd = 0xf8c0e0c0,
1763        .pre_write = error_sig_dis_2_prew,
1764    },{ .name = "ERROR_EN_1",  .decode.addr = A_ERROR_EN_1,
1765        .post_write = error_en_1_postw,
1766    },{ .name = "ERROR_EN_2",  .decode.addr = A_ERROR_EN_2,
1767        .post_write = error_en_2_postw,
1768    },{ .name = "AIB_CNTRL",  .decode.addr = A_AIB_CNTRL,
1769        .rsvd = 0xfffffff0,
1770    },{ .name = "AIB_STATUS",  .decode.addr = A_AIB_STATUS,
1771        .rsvd = 0xfffffff0,
1772        .ro = 0xffffffff,
1773    },{ .name = "GLOBAL_RESET",  .decode.addr = A_GLOBAL_RESET,
1774        .rsvd = 0xfffff8ff,
1775        .ro = 0xfffff8ff,
1776        .gpios = (DepRegisterGPIOMapping[]) {
1777            { .name = "FPD_RST", .bit_pos = 9, .width = 1 },
1778            { .name = "PS_ONLY_RST", .bit_pos = 10, .width = 1 },
1779            {},
1780        }
1781    },{ .name = "ROM_VALIDATION_STATUS",  .decode.addr = A_ROM_VALIDATION_STATUS,
1782        .rsvd = 0xfffffffc,
1783        .ro = 0xffffffff,
1784    },{ .name = "ROM_VALIDATION_DIGEST_0",  .decode.addr = A_ROM_VALIDATION_DIGEST_0,
1785        .ro = 0xffffffff,
1786    },{ .name = "ROM_VALIDATION_DIGEST_1",  .decode.addr = A_ROM_VALIDATION_DIGEST_1,
1787        .ro = 0xffffffff,
1788    },{ .name = "ROM_VALIDATION_DIGEST_2",  .decode.addr = A_ROM_VALIDATION_DIGEST_2,
1789        .ro = 0xffffffff,
1790    },{ .name = "ROM_VALIDATION_DIGEST_3",  .decode.addr = A_ROM_VALIDATION_DIGEST_3,
1791        .ro = 0xffffffff,
1792    },{ .name = "ROM_VALIDATION_DIGEST_4",  .decode.addr = A_ROM_VALIDATION_DIGEST_4,
1793        .ro = 0xffffffff,
1794    },{ .name = "ROM_VALIDATION_DIGEST_5",  .decode.addr = A_ROM_VALIDATION_DIGEST_5,
1795        .ro = 0xffffffff,
1796    },{ .name = "ROM_VALIDATION_DIGEST_6",  .decode.addr = A_ROM_VALIDATION_DIGEST_6,
1797        .ro = 0xffffffff,
1798    },{ .name = "ROM_VALIDATION_DIGEST_7",  .decode.addr = A_ROM_VALIDATION_DIGEST_7,
1799        .ro = 0xffffffff,
1800    },{ .name = "ROM_VALIDATION_DIGEST_8",  .decode.addr = A_ROM_VALIDATION_DIGEST_8,
1801        .ro = 0xffffffff,
1802    },{ .name = "ROM_VALIDATION_DIGEST_9",  .decode.addr = A_ROM_VALIDATION_DIGEST_9,
1803        .ro = 0xffffffff,
1804    },{ .name = "ROM_VALIDATION_DIGEST_10",  .decode.addr = A_ROM_VALIDATION_DIGEST_10,
1805        .ro = 0xffffffff,
1806    },{ .name = "ROM_VALIDATION_DIGEST_11",  .decode.addr = A_ROM_VALIDATION_DIGEST_11,
1807        .ro = 0xffffffff,
1808    },{ .name = "SAFETY_GATE",  .decode.addr = A_SAFETY_GATE,
1809    },{ .name = "MBIST_RST",  .decode.addr = A_MBIST_RST,
1810        .post_write = mbist_rst_postw,
1811    },{ .name = "MBIST_PG_EN",  .decode.addr = A_MBIST_PG_EN,
1812        .post_write = mbist_pg_en_postw,
1813    },{ .name = "MBIST_SETUP",  .decode.addr = A_MBIST_SETUP,
1814    },{ .name = "MBIST_DONE",  .decode.addr = A_MBIST_DONE, .ro = 0xffffffff,
1815    },{ .name = "MBIST_GOOD",  .decode.addr = A_MBIST_GOOD, .ro = 0xffffffff,
1816    },{ .name = "SAFETY_CHK",  .decode.addr = A_SAFETY_CHK,
1817    }
1818};
1819
1820static void pmu_global_reset(DeviceState *dev)
1821{
1822    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(dev);
1823    unsigned int i;
1824
1825    for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
1826        dep_register_reset(&s->regs_info[i]);
1827    }
1828
1829    s->error_1 = 0;
1830    s->error_2 = 0;
1831
1832    req_pwrdwn_int_update_irq(s);
1833    req_swrst_int_update_irq(s);
1834    req_aux_int_update_irq(s);
1835    req_pwrup_int_update_irq(s);
1836    addr_error_int_update_irq(s);
1837    error_int_2_update_irq(s);
1838    error_int_1_update_irq(s);
1839    req_iso_int_update_irq(s);
1840
1841    DEP_AF_DP32(s->regs, GLOBAL_CNTRL, FW_IS_PRESENT, s->fw_is_present);
1842}
1843
1844static void pwr_state_handler(void *opaque, int n, int level)
1845{
1846    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1847
1848    s->regs[R_PWR_STATE] = deposit32(s->regs[R_PWR_STATE], n, 1, level);
1849}
1850
1851static void error_handler(void *opaque, int n, int level)
1852{
1853    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1854
1855    /* First 32 gpios are for ERROR_STATUS_1 */
1856    if (n < 32) {
1857        s->error_1 = deposit32(s->error_1, n, 1, level);
1858        set_error_1(s);
1859    } else {
1860        s->error_2 = deposit32(s->error_2, n, 1, level);
1861        set_error_2(s);
1862    }
1863}
1864
1865static uint64_t pmu_global_read(void *opaque, hwaddr addr, unsigned size,
1866                                MemTxAttrs attr)
1867{
1868    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1869    DepRegisterInfo *r = &s->regs_info[addr / 4];
1870
1871    if (!r->data) {
1872        qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
1873                 object_get_canonical_path(OBJECT(s)),
1874                 addr);
1875        s->regs[R_ADDR_ERROR_STATUS] |= R_ADDR_ERROR_STATUS_STATUS_MASK;
1876        addr_error_int_update_irq(s);
1877        return 0;
1878    }
1879    return dep_register_read(r);
1880}
1881
1882static void pmu_global_write(void *opaque, hwaddr addr, uint64_t value,
1883                      unsigned size, MemTxAttrs attr)
1884{
1885    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1886    DepRegisterInfo *r = &s->regs_info[addr / 4];
1887
1888    if (!r->data) {
1889        qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
1890                 object_get_canonical_path(OBJECT(s)),
1891                 addr, value);
1892        s->regs[R_ADDR_ERROR_STATUS] |= R_ADDR_ERROR_STATUS_STATUS_MASK;
1893        addr_error_int_update_irq(s);
1894        return;
1895    }
1896    dep_register_write(r, value, ~0);
1897}
1898
1899static void pmu_global_access(MemoryTransaction *tr)
1900{
1901    MemTxAttrs attr = tr->attr;
1902    void *opaque = tr->opaque;
1903    hwaddr addr = tr->addr;
1904    unsigned size = tr->size;
1905    uint64_t value = tr->data.u64;;
1906    bool is_write = tr->rw;
1907
1908    if (!attr.secure) {
1909        /* Ignore NS accesses.  */
1910        if (!is_write) {
1911            tr->data.u64 = 0;
1912        }
1913        qemu_log_mask(LOG_GUEST_ERROR,
1914                      "Non secure accesses to PMU global are invalid\n");
1915        return;
1916    }
1917
1918    if (is_write) {
1919        pmu_global_write(opaque, addr, value, size, attr);
1920    } else {
1921        tr->data.u64 = pmu_global_read(opaque, addr, size, attr);
1922    }
1923}
1924
1925static const MemoryRegionOps pmu_global_ops = {
1926    .access = pmu_global_access,
1927    .endianness = DEVICE_LITTLE_ENDIAN,
1928    .valid = {
1929        .min_access_size = 4,
1930        .max_access_size = 4,
1931    },
1932};
1933
1934static void gpio_mb_sleep_h(void *opaque, int n, int level)
1935{
1936    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(opaque);
1937    DEP_AF_DP32(s->regs, GLOBAL_CNTRL, MB_SLEEP, !!level);
1938}
1939
1940static void pmu_global_realize(DeviceState *dev, Error **errp)
1941{
1942    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(dev);
1943    const char *prefix = object_get_canonical_path(OBJECT(dev));
1944    unsigned int i;
1945
1946    for (i = 0; i < ARRAY_SIZE(pmu_global_regs_info); ++i) {
1947        DepRegisterInfo *r = &s->regs_info[pmu_global_regs_info[i].decode.addr/4];
1948
1949        *r = (DepRegisterInfo) {
1950            .data = (uint8_t *)&s->regs[
1951                    pmu_global_regs_info[i].decode.addr/4],
1952            .data_size = sizeof(uint32_t),
1953            .access = &pmu_global_regs_info[i],
1954            .debug = XILINX_PMU_GLOBAL_ERR_DEBUG,
1955            .prefix = prefix,
1956            .opaque = s,
1957        };
1958        dep_register_init(r);
1959        qdev_pass_all_gpios(DEVICE(r), dev);
1960    }
1961}
1962
1963static void pmu_global_init(Object *obj)
1964{
1965    PMU_GLOBAL *s = XILINX_PMU_GLOBAL(obj);
1966    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
1967
1968    memory_region_init_io(&s->iomem, obj, &pmu_global_ops, s,
1969                          TYPE_XILINX_PMU_GLOBAL, R_MAX * 4);
1970    sysbus_init_mmio(sbd, &s->iomem);
1971    sysbus_init_irq(sbd, &s->irq_req_logclr_int); /* 23 */
1972    sysbus_init_irq(sbd, &s->irq_req_iso_int);    /* 24 */
1973    sysbus_init_irq(sbd, &s->irq_req_swrst_int);  /* 26 */
1974    sysbus_init_irq(sbd, &s->irq_req_pwrup_int);  /* 27 */
1975    sysbus_init_irq(sbd, &s->irq_req_pwrdwn_int); /* 28 */
1976    sysbus_init_irq(sbd, &s->irq_addr_error_int); /* 29 */
1977
1978    qdev_init_gpio_in_named(DEVICE(obj), gpio_mb_sleep_h, "mb_sleep", 1);
1979    qdev_init_gpio_in_named(DEVICE(obj), pwr_state_handler, "pwr_state", 24);
1980    qdev_init_gpio_out_named(DEVICE(obj), &s->irq_error_int_1,
1981                             "error_1_out", 1);
1982    qdev_init_gpio_out_named(DEVICE(obj), &s->irq_error_int_2,
1983                             "error_2_out", 1);
1984
1985    /* GPIOs that can be used from qtest */
1986    qdev_init_gpio_in(DEVICE(obj), error_handler, 64);
1987}
1988
1989static const VMStateDescription vmstate_pmu_global = {
1990    .name = TYPE_XILINX_PMU_GLOBAL,
1991    .version_id = 1,
1992    .minimum_version_id = 1,
1993    .minimum_version_id_old = 1,
1994    .fields = (VMStateField[]) {
1995        VMSTATE_UINT32_ARRAY(regs, PMU_GLOBAL, R_MAX),
1996        VMSTATE_END_OF_LIST(),
1997    }
1998};
1999
2000static const FDTGenericGPIOSet pmu_gpios[] = {
2001    {
2002      .names = &fdt_generic_gpio_name_set_gpio,
2003      .gpios = (FDTGenericGPIOConnection[]) {
2004        { .name = "pmu_wake", .fdt_index = 0 },
2005        { .name = "FPD_RST", .fdt_index = 2 },
2006        { .name = "PS_ONLY_RST", .fdt_index = 3 },
2007        { },
2008      },
2009    },
2010    { },
2011};
2012
2013static const FDTGenericGPIONameSet pwr_state_gpios_names = {
2014    .propname = "pwr-state-gpios",
2015    .cells_propname = "#gpio-cells",
2016    .names_propname = "pwr-state-gpio-names",
2017};
2018
2019static const FDTGenericGPIONameSet error_out_gpios_names = {
2020    .propname = "error-out-gpios",
2021    .cells_propname = "#gpio-cells",
2022    .names_propname = "error-out-names",
2023};
2024
2025static const FDTGenericGPIOSet pmu_global_client_gpios[] = {
2026    {
2027      .names = &pwr_state_gpios_names,
2028      .gpios = (FDTGenericGPIOConnection[]) {
2029        { .name = "pwr_state", .fdt_index = 0, .range = 24 },
2030        { },
2031      },
2032    },
2033    {
2034      .names = &fdt_generic_gpio_name_set_gpio,
2035      .gpios = (FDTGenericGPIOConnection[]) {
2036        { .name = "mb_sleep", .fdt_index = 1 },
2037        { },
2038      },
2039    },
2040    {
2041      .names = &error_out_gpios_names,
2042      .gpios = (FDTGenericGPIOConnection[]) {
2043        { .name = "error_1_out", .fdt_index = 0 },
2044        { .name = "error_2_out", .fdt_index = 1 },
2045        { },
2046      },
2047    },
2048    { },
2049};
2050
2051static Property pmu_global_properties[] = {
2052    DEFINE_PROP_BOOL("fw-is-present", PMU_GLOBAL, fw_is_present, false),
2053    DEFINE_PROP_BOOL("ignore-pwr-req", PMU_GLOBAL, ignore_pwr_req, false),
2054    DEFINE_PROP_END_OF_LIST(),
2055};
2056
2057static void pmu_global_class_init(ObjectClass *klass, void *data)
2058{
2059    DeviceClass *dc = DEVICE_CLASS(klass);
2060    FDTGenericGPIOClass *fggc = FDT_GENERIC_GPIO_CLASS(klass);
2061
2062    dc->reset = pmu_global_reset;
2063    dc->realize = pmu_global_realize;
2064    dc->vmsd = &vmstate_pmu_global;
2065    dc->props = pmu_global_properties;
2066    fggc->controller_gpios = pmu_gpios;
2067    fggc->client_gpios = pmu_global_client_gpios;
2068}
2069
2070static const TypeInfo pmu_global_info = {
2071    .name          = TYPE_XILINX_PMU_GLOBAL,
2072    .parent        = TYPE_SYS_BUS_DEVICE,
2073    .instance_size = sizeof(PMU_GLOBAL),
2074    .class_init    = pmu_global_class_init,
2075    .instance_init = pmu_global_init,
2076    .interfaces    = (InterfaceInfo[]) {
2077        { TYPE_FDT_GENERIC_GPIO },
2078        { }
2079    },
2080};
2081
2082static void pmu_global_register_types(void)
2083{
2084    type_register_static(&pmu_global_info);
2085}
2086
2087type_init(pmu_global_register_types)
2088